1 // VGA bios implementation
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
10 // * introduce "struct vregs", or add ebp to struct bregs.
11 // * define structs for save/restore state
12 // * review correctness of converted asm by comparing with RBIL
13 // * refactor redundant code into sub-functions
14 // * See if there is a method to the in/out stuff that can be encapsulated.
15 // * remove "biosfn" prefixes
16 // * verify all funcs static
18 // * convert vbe/clext code
20 // * separate code into separate files
21 // * extract hw code from bios interfaces
23 #include "bregs.h" // struct bregs
24 #include "biosvar.h" // GET_BDA
25 #include "util.h" // memset
26 #include "vgatables.h" // vga_modes
30 #define CONFIG_CIRRUS 0
33 #define DEBUG_VGA_POST 1
34 #define DEBUG_VGA_10 3
36 #define SET_VGA(var, val) SET_FARVAR(get_global_seg(), (var), (val))
39 // ===================================================================
43 // ===================================================================
45 // -------------------------------------------------------------------
47 call16_vgaint(u32 eax, u32 ebx)
60 memcpy16_far(u16 d_seg, void *d_far, u16 s_seg, const void *s_far, size_t len)
62 memcpy_far(d_seg, d_far, s_seg, s_far, len);
66 // ===================================================================
70 // ===================================================================
72 // -------------------------------------------------------------------
74 biosfn_perform_gray_scale_summing(u16 start, u16 count)
76 inb(VGAREG_ACTL_RESET);
77 outb(0x00, VGAREG_ACTL_ADDRESS);
80 for (i = start; i < start+count; i++) {
81 // set read address and switch to read mode
82 outb(i, VGAREG_DAC_READ_ADDRESS);
83 // get 6-bit wide RGB data values
84 u8 r = inb(VGAREG_DAC_DATA);
85 u8 g = inb(VGAREG_DAC_DATA);
86 u8 b = inb(VGAREG_DAC_DATA);
88 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
89 u16 intensity = ((77 * r + 151 * g + 28 * b) + 0x80) >> 8;
94 // set write address and switch to write mode
95 outb(i, VGAREG_DAC_WRITE_ADDRESS);
96 // write new intensity value
97 outb(intensity & 0xff, VGAREG_DAC_DATA);
98 outb(intensity & 0xff, VGAREG_DAC_DATA);
99 outb(intensity & 0xff, VGAREG_DAC_DATA);
101 inb(VGAREG_ACTL_RESET);
102 outb(0x20, VGAREG_ACTL_ADDRESS);
105 // -------------------------------------------------------------------
107 biosfn_set_cursor_shape(u8 CH, u8 CL)
112 u16 curs = (CH << 8) + CL;
113 SET_BDA(cursor_type, curs);
115 u8 modeset_ctl = GET_BDA(modeset_ctl);
116 u16 cheight = GET_BDA(char_height);
117 if ((modeset_ctl & 0x01) && (cheight > 8) && (CL < 8) && (CH < 0x20)) {
119 CH = ((CH + 1) * cheight / 8) - 1;
121 CH = ((CL + 1) * cheight / 8) - 2;
122 CL = ((CL + 1) * cheight / 8) - 1;
124 // CTRC regs 0x0a and 0x0b
125 u16 crtc_addr = GET_BDA(crtc_address);
126 outb(0x0a, crtc_addr);
127 outb(CH, crtc_addr + 1);
128 outb(0x0b, crtc_addr);
129 outb(CL, crtc_addr + 1);
133 biosfn_get_cursor_shape(u8 page)
137 // FIXME should handle VGA 14/16 lines
138 return GET_BDA(cursor_type);
141 // -------------------------------------------------------------------
143 biosfn_set_cursor_pos(u8 page, u16 cursor)
145 // Should not happen...
150 SET_BDA(cursor_pos[page], cursor);
152 // Set the hardware cursor
153 u8 current = GET_BDA(video_page);
157 // Get the dimensions
158 u16 nbcols = GET_BDA(video_cols);
159 u16 nbrows = GET_BDA(video_rows) + 1;
161 u8 xcurs = cursor & 0x00ff;
162 u8 ycurs = (cursor & 0xff00) >> 8;
164 // Calculate the address knowing nbcols nbrows and page num
165 u16 address = SCREEN_IO_START(nbcols, nbrows, page) + xcurs + ycurs * nbcols;
167 // CRTC regs 0x0e and 0x0f
168 u16 crtc_addr = GET_BDA(crtc_address);
169 outb(0x0e, crtc_addr);
170 outb((address & 0xff00) >> 8, crtc_addr + 1);
171 outb(0x0f, crtc_addr);
172 outb(address & 0x00ff, crtc_addr + 1);
176 biosfn_get_cursor_pos(u8 page)
180 // FIXME should handle VGA 14/16 lines
181 return GET_BDA(cursor_pos[page]);
184 // -------------------------------------------------------------------
186 biosfn_set_active_page(u8 page)
192 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
196 // Get pos curs pos for the right page
197 u16 cursor = biosfn_get_cursor_pos(page);
200 if (GET_GLOBAL(vmode_g->class) == TEXT) {
201 // Get the dimensions
202 u16 nbcols = GET_BDA(video_cols);
203 u16 nbrows = GET_BDA(video_rows) + 1;
205 // Calculate the address knowing nbcols nbrows and page num
206 address = SCREEN_MEM_START(nbcols, nbrows, page);
207 SET_BDA(video_pagestart, address);
210 address = SCREEN_IO_START(nbcols, nbrows, page);
212 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
213 address = page * GET_GLOBAL(vparam_g->slength);
216 // CRTC regs 0x0c and 0x0d
217 u16 crtc_addr = GET_BDA(crtc_address);
218 outb(0x0c, crtc_addr);
219 outb((address & 0xff00) >> 8, crtc_addr + 1);
220 outb(0x0d, crtc_addr);
221 outb(address & 0x00ff, crtc_addr + 1);
223 // And change the BIOS page
224 SET_BDA(video_page, page);
226 dprintf(1, "Set active page %02x address %04x\n", page, address);
228 // Display the cursor, now the page is active
229 biosfn_set_cursor_pos(page, cursor);
233 biosfn_set_video_mode(u8 mode)
234 { // mode: Bit 7 is 1 if no clear screen
236 cirrus_set_video_mode(mode);
239 if (vbe_has_vbe_display())
240 dispi_set_enable(VBE_DISPI_DISABLED);
244 u8 noclearmem = mode & 0x80;
247 // find the entry in the video modes
248 struct vgamode_s *vmode_g = find_vga_entry(mode);
249 dprintf(1, "mode search %02x found %p\n", mode, vmode_g);
253 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
254 u16 twidth = GET_GLOBAL(vparam_g->twidth);
255 u16 theightm1 = GET_GLOBAL(vparam_g->theightm1);
256 u16 cheight = GET_GLOBAL(vparam_g->cheight);
258 // Read the bios mode set control
259 u8 modeset_ctl = GET_BDA(modeset_ctl);
261 // Then we know the number of lines
264 // if palette loading (bit 3 of modeset ctl = 0)
265 if ((modeset_ctl & 0x08) == 0) { // Set the PEL mask
266 outb(GET_GLOBAL(vmode_g->pelmask), VGAREG_PEL_MASK);
268 // Set the whole dac always, from 0
269 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
271 // From which palette
272 u8 *palette_g = GET_GLOBAL(vmode_g->dac);
273 u16 palsize = GET_GLOBAL(vmode_g->dacsize);
274 // Always 256*3 values
276 for (i = 0; i < 0x0100; i++) {
278 outb(GET_GLOBAL(palette_g[(i * 3) + 0]), VGAREG_DAC_DATA);
279 outb(GET_GLOBAL(palette_g[(i * 3) + 1]), VGAREG_DAC_DATA);
280 outb(GET_GLOBAL(palette_g[(i * 3) + 2]), VGAREG_DAC_DATA);
282 outb(0, VGAREG_DAC_DATA);
283 outb(0, VGAREG_DAC_DATA);
284 outb(0, VGAREG_DAC_DATA);
287 if ((modeset_ctl & 0x02) == 0x02)
288 biosfn_perform_gray_scale_summing(0x00, 0x100);
290 // Reset Attribute Ctl flip-flop
291 inb(VGAREG_ACTL_RESET);
295 for (i = 0; i <= 0x13; i++) {
296 outb(i, VGAREG_ACTL_ADDRESS);
297 outb(GET_GLOBAL(vparam_g->actl_regs[i]), VGAREG_ACTL_WRITE_DATA);
299 outb(0x14, VGAREG_ACTL_ADDRESS);
300 outb(0x00, VGAREG_ACTL_WRITE_DATA);
303 outb(0, VGAREG_SEQU_ADDRESS);
304 outb(0x03, VGAREG_SEQU_DATA);
305 for (i = 1; i <= 4; i++) {
306 outb(i, VGAREG_SEQU_ADDRESS);
307 outb(GET_GLOBAL(vparam_g->sequ_regs[i - 1]), VGAREG_SEQU_DATA);
311 for (i = 0; i <= 8; i++) {
312 outb(i, VGAREG_GRDC_ADDRESS);
313 outb(GET_GLOBAL(vparam_g->grdc_regs[i]), VGAREG_GRDC_DATA);
316 // Set CRTC address VGA or MDA
317 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
318 if (GET_GLOBAL(vmode_g->memmodel) == MTEXT)
319 crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
321 // Disable CRTC write protection
322 outw(0x0011, crtc_addr);
324 for (i = 0; i <= 0x18; i++) {
326 outb(GET_GLOBAL(vparam_g->crtc_regs[i]), crtc_addr + 1);
329 // Set the misc register
330 outb(GET_GLOBAL(vparam_g->miscreg), VGAREG_WRITE_MISC_OUTPUT);
333 outb(0x20, VGAREG_ACTL_ADDRESS);
334 inb(VGAREG_ACTL_RESET);
336 if (noclearmem == 0x00) {
337 if (GET_GLOBAL(vmode_g->class) == TEXT) {
338 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0720, 32*1024);
341 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 32*1024);
343 outb(0x02, VGAREG_SEQU_ADDRESS);
344 u8 mmask = inb(VGAREG_SEQU_DATA);
345 outb(0x0f, VGAREG_SEQU_DATA); // all planes
346 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 64*1024);
347 outb(mmask, VGAREG_SEQU_DATA);
352 SET_BDA(video_mode, mode);
353 SET_BDA(video_cols, twidth);
354 SET_BDA(video_pagesize, GET_GLOBAL(vparam_g->slength));
355 SET_BDA(crtc_address, crtc_addr);
356 SET_BDA(video_rows, theightm1);
357 SET_BDA(char_height, cheight);
358 SET_BDA(video_ctl, (0x60 | noclearmem));
359 SET_BDA(video_switches, 0xF9);
360 SET_BDA(modeset_ctl, GET_BDA(modeset_ctl) & 0x7f);
362 // FIXME We nearly have the good tables. to be reworked
363 SET_BDA(dcc_index, 0x08); // 8 is VGA should be ok for now
364 SET_BDA(video_savetable_ptr, (u32)video_save_pointer_table);
365 SET_BDA(video_savetable_seg, get_global_seg());
368 SET_BDA(video_msr, 0x00); // Unavailable on vanilla vga, but...
369 SET_BDA(video_pal, 0x00); // Unavailable on vanilla vga, but...
372 if (GET_GLOBAL(vmode_g->class) == TEXT)
373 biosfn_set_cursor_shape(0x06, 0x07);
374 // Set cursor pos for page 0..7
375 for (i = 0; i < 8; i++)
376 biosfn_set_cursor_pos(i, 0x0000);
379 biosfn_set_active_page(0x00);
381 // Write the fonts in memory
382 if (GET_GLOBAL(vmode_g->class) == TEXT) {
383 call16_vgaint(0x1104, 0);
384 call16_vgaint(0x1103, 0);
386 // Set the ints 0x1F and 0x43
387 SET_IVT(0x1f, get_global_seg(), (u32)&vgafont8[128 * 8]);
391 SET_IVT(0x43, get_global_seg(), (u32)vgafont8);
394 SET_IVT(0x43, get_global_seg(), (u32)vgafont14);
397 SET_IVT(0x43, get_global_seg(), (u32)vgafont16);
402 // -------------------------------------------------------------------
404 vgamem_copy_pl4(u8 xstart, u8 ysrc, u8 ydest, u8 cols, u8 nbcols,
407 u16 src = ysrc * cheight * nbcols + xstart;
408 u16 dest = ydest * cheight * nbcols + xstart;
409 outw(0x0105, VGAREG_GRDC_ADDRESS);
411 for (i = 0; i < cheight; i++)
412 memcpy_far(SEG_GRAPH, (void*)(dest + i * nbcols)
413 , SEG_GRAPH, (void*)(src + i * nbcols), cols);
414 outw(0x0005, VGAREG_GRDC_ADDRESS);
417 // -------------------------------------------------------------------
419 vgamem_fill_pl4(u8 xstart, u8 ystart, u8 cols, u8 nbcols, u8 cheight,
422 u16 dest = ystart * cheight * nbcols + xstart;
423 outw(0x0205, VGAREG_GRDC_ADDRESS);
425 for (i = 0; i < cheight; i++)
426 memset_far(SEG_GRAPH, (void*)(dest + i * nbcols), attr, cols);
427 outw(0x0005, VGAREG_GRDC_ADDRESS);
430 // -------------------------------------------------------------------
432 vgamem_copy_cga(u8 xstart, u8 ysrc, u8 ydest, u8 cols, u8 nbcols,
435 u16 src = ((ysrc * cheight * nbcols) >> 1) + xstart;
436 u16 dest = ((ydest * cheight * nbcols) >> 1) + xstart;
438 for (i = 0; i < cheight; i++)
440 memcpy_far(SEG_CTEXT, (void*)(0x2000 + dest + (i >> 1) * nbcols)
441 , SEG_CTEXT, (void*)(0x2000 + src + (i >> 1) * nbcols)
444 memcpy_far(SEG_CTEXT, (void*)(dest + (i >> 1) * nbcols)
445 , SEG_CTEXT, (void*)(src + (i >> 1) * nbcols), cols);
448 // -------------------------------------------------------------------
450 vgamem_fill_cga(u8 xstart, u8 ystart, u8 cols, u8 nbcols, u8 cheight,
453 u16 dest = ((ystart * cheight * nbcols) >> 1) + xstart;
455 for (i = 0; i < cheight; i++)
457 memset_far(SEG_CTEXT, (void*)(0x2000 + dest + (i >> 1) * nbcols)
460 memset_far(SEG_CTEXT, (void*)(dest + (i >> 1) * nbcols), attr, cols);
463 // -------------------------------------------------------------------
465 biosfn_scroll(u8 nblines, u8 attr, u8 rul, u8 cul, u8 rlr, u8 clr, u8 page,
468 // page == 0xFF if current
475 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
479 // Get the dimensions
480 u16 nbrows = GET_BDA(video_rows) + 1;
481 u16 nbcols = GET_BDA(video_cols);
483 // Get the current page
485 page = GET_BDA(video_page);
491 if (nblines > nbrows)
493 u8 cols = clr - cul + 1;
495 if (GET_GLOBAL(vmode_g->class) == TEXT) {
496 // Compute the address
497 void *address_far = (void*)(SCREEN_MEM_START(nbcols, nbrows, page));
498 dprintf(3, "Scroll, address %p (%d %d %02x)\n"
499 , address_far, nbrows, nbcols, page);
501 if (nblines == 0 && rul == 0 && cul == 0 && rlr == nbrows - 1
502 && clr == nbcols - 1) {
503 memset16_far(GET_GLOBAL(vmode_g->sstart), address_far
504 , (u16)attr * 0x100 + ' ', nbrows * nbcols * 2);
505 } else { // if Scroll up
506 if (dir == SCROLL_UP) {
508 for (i = rul; i <= rlr; i++)
509 if ((i + nblines > rlr) || (nblines == 0))
510 memset16_far(GET_GLOBAL(vmode_g->sstart)
511 , address_far + (i * nbcols + cul) * 2
512 , (u16)attr * 0x100 + ' ', cols * 2);
514 memcpy16_far(GET_GLOBAL(vmode_g->sstart)
515 , address_far + (i * nbcols + cul) * 2
516 , GET_GLOBAL(vmode_g->sstart)
517 , (void*)(((i + nblines) * nbcols + cul) * 2)
521 for (i = rlr; i >= rul; i--) {
522 if ((i < rul + nblines) || (nblines == 0))
523 memset16_far(GET_GLOBAL(vmode_g->sstart)
524 , address_far + (i * nbcols + cul) * 2
525 , (u16)attr * 0x100 + ' ', cols * 2);
527 memcpy16_far(GET_GLOBAL(vmode_g->sstart)
528 , address_far + (i * nbcols + cul) * 2
529 , GET_GLOBAL(vmode_g->sstart)
530 , (void*)(((i - nblines) * nbcols + cul) * 2)
540 // FIXME gfx mode not complete
541 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
542 u8 cheight = GET_GLOBAL(vparam_g->cheight);
543 switch (GET_GLOBAL(vmode_g->memmodel)) {
546 if (nblines == 0 && rul == 0 && cul == 0 && rlr == nbrows - 1
547 && clr == nbcols - 1) {
548 outw(0x0205, VGAREG_GRDC_ADDRESS);
549 memset_far(GET_GLOBAL(vmode_g->sstart), 0, attr,
550 nbrows * nbcols * cheight);
551 outw(0x0005, VGAREG_GRDC_ADDRESS);
552 } else { // if Scroll up
553 if (dir == SCROLL_UP) {
555 for (i = rul; i <= rlr; i++)
556 if ((i + nblines > rlr) || (nblines == 0))
557 vgamem_fill_pl4(cul, i, cols, nbcols, cheight,
560 vgamem_copy_pl4(cul, i + nblines, i, cols,
564 for (i = rlr; i >= rul; i--) {
565 if ((i < rul + nblines) || (nblines == 0))
566 vgamem_fill_pl4(cul, i, cols, nbcols, cheight,
569 vgamem_copy_pl4(cul, i, i - nblines, cols,
578 u8 bpp = GET_GLOBAL(vmode_g->pixbits);
579 if (nblines == 0 && rul == 0 && cul == 0 && rlr == nbrows - 1
580 && clr == nbcols - 1) {
581 memset_far(GET_GLOBAL(vmode_g->sstart), 0, attr,
582 nbrows * nbcols * cheight * bpp);
590 if (dir == SCROLL_UP) {
592 for (i = rul; i <= rlr; i++)
593 if ((i + nblines > rlr) || (nblines == 0))
594 vgamem_fill_cga(cul, i, cols, nbcols, cheight,
597 vgamem_copy_cga(cul, i + nblines, i, cols,
601 for (i = rlr; i >= rul; i--) {
602 if ((i < rul + nblines) || (nblines == 0))
603 vgamem_fill_cga(cul, i, cols, nbcols, cheight,
606 vgamem_copy_cga(cul, i, i - nblines, cols,
616 dprintf(1, "Scroll in graphics mode\n");
620 // -------------------------------------------------------------------
622 biosfn_read_char_attr(u8 page, u16 *car)
625 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
629 // Get the cursor pos for the page
630 u16 cursor = biosfn_get_cursor_pos(page);
631 u8 xcurs = cursor & 0x00ff;
632 u8 ycurs = (cursor & 0xff00) >> 8;
634 // Get the dimensions
635 u16 nbrows = GET_BDA(video_rows) + 1;
636 u16 nbcols = GET_BDA(video_cols);
638 if (GET_GLOBAL(vmode_g->class) == TEXT) {
639 // Compute the address
640 u16 *address_far = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
641 + (xcurs + ycurs * nbcols) * 2);
643 *car = GET_FARVAR(GET_GLOBAL(vmode_g->sstart), *address_far);
646 dprintf(1, "Read char in graphics mode\n");
650 // -------------------------------------------------------------------
652 write_gfx_char_pl4(u8 car, u8 attr, u8 xcurs, u8 ycurs, u8 nbcols,
666 u16 addr = xcurs + ycurs * cheight * nbcols;
667 u16 src = car * cheight;
668 outw(0x0f02, VGAREG_SEQU_ADDRESS);
669 outw(0x0205, VGAREG_GRDC_ADDRESS);
671 outw(0x1803, VGAREG_GRDC_ADDRESS);
673 outw(0x0003, VGAREG_GRDC_ADDRESS);
675 for (i = 0; i < cheight; i++) {
676 u8 *dest_far = (void*)(addr + i * nbcols);
678 for (j = 0; j < 8; j++) {
680 outw((mask << 8) | 0x08, VGAREG_GRDC_ADDRESS);
681 GET_FARVAR(SEG_GRAPH, *dest_far);
682 if (GET_GLOBAL(fdata_g[src + i]) & mask)
683 SET_FARVAR(SEG_GRAPH, *dest_far, attr & 0x0f);
685 SET_FARVAR(SEG_GRAPH, *dest_far, 0x00);
688 outw(0xff08, VGAREG_GRDC_ADDRESS);
689 outw(0x0005, VGAREG_GRDC_ADDRESS);
690 outw(0x0003, VGAREG_GRDC_ADDRESS);
693 // -------------------------------------------------------------------
695 write_gfx_char_cga(u8 car, u8 attr, u8 xcurs, u8 ycurs, u8 nbcols, u8 bpp)
697 u8 *fdata_g = vgafont8;
698 u16 addr = (xcurs * bpp) + ycurs * 320;
701 for (i = 0; i < 8; i++) {
702 u8 *dest_far = (void*)(addr + (i >> 1) * 80);
709 data = GET_FARVAR(SEG_CTEXT, *dest_far);
711 for (j = 0; j < 8; j++) {
712 if (GET_GLOBAL(fdata_g[src + i]) & mask) {
714 data ^= (attr & 0x01) << (7 - j);
716 data |= (attr & 0x01) << (7 - j);
720 SET_FARVAR(SEG_CTEXT, *dest_far, data);
725 data = GET_FARVAR(SEG_CTEXT, *dest_far);
727 for (j = 0; j < 4; j++) {
728 if (GET_GLOBAL(fdata_g[src + i]) & mask) {
730 data ^= (attr & 0x03) << ((3 - j) * 2);
732 data |= (attr & 0x03) << ((3 - j) * 2);
736 SET_FARVAR(SEG_CTEXT, *dest_far, data);
743 // -------------------------------------------------------------------
745 write_gfx_char_lin(u8 car, u8 attr, u8 xcurs, u8 ycurs, u8 nbcols)
747 u8 *fdata_g = vgafont8;
748 u16 addr = xcurs * 8 + ycurs * nbcols * 64;
751 for (i = 0; i < 8; i++) {
752 u8 *dest_far = (void*)(addr + i * nbcols * 8);
755 for (j = 0; j < 8; j++) {
757 if (GET_GLOBAL(fdata_g[src + i]) & mask)
759 SET_FARVAR(SEG_GRAPH, dest_far[j], data);
765 // -------------------------------------------------------------------
767 biosfn_write_char_attr(u8 car, u8 page, u8 attr, u16 count)
770 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
774 // Get the cursor pos for the page
775 u16 cursor = biosfn_get_cursor_pos(page);
776 u8 xcurs = cursor & 0x00ff;
777 u8 ycurs = (cursor & 0xff00) >> 8;
779 // Get the dimensions
780 u16 nbrows = GET_BDA(video_rows) + 1;
781 u16 nbcols = GET_BDA(video_cols);
783 if (GET_GLOBAL(vmode_g->class) == TEXT) {
784 // Compute the address
785 void *address_far = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
786 + (xcurs + ycurs * nbcols) * 2);
788 u16 dummy = ((u16)attr << 8) + car;
789 memset16_far(GET_GLOBAL(vmode_g->sstart), address_far, dummy, count * 2);
793 // FIXME gfx mode not complete
794 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
795 u8 cheight = GET_GLOBAL(vparam_g->cheight);
796 u8 bpp = GET_GLOBAL(vmode_g->pixbits);
797 while ((count-- > 0) && (xcurs < nbcols)) {
798 switch (GET_GLOBAL(vmode_g->memmodel)) {
801 write_gfx_char_pl4(car, attr, xcurs, ycurs, nbcols,
805 write_gfx_char_cga(car, attr, xcurs, ycurs, nbcols, bpp);
808 write_gfx_char_lin(car, attr, xcurs, ycurs, nbcols);
815 // -------------------------------------------------------------------
817 biosfn_write_char_only(u8 car, u8 page, u8 attr, u16 count)
820 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
824 // Get the cursor pos for the page
825 u16 cursor = biosfn_get_cursor_pos(page);
826 u8 xcurs = cursor & 0x00ff;
827 u8 ycurs = (cursor & 0xff00) >> 8;
829 // Get the dimensions
830 u16 nbrows = GET_BDA(video_rows) + 1;
831 u16 nbcols = GET_BDA(video_cols);
833 if (GET_GLOBAL(vmode_g->class) == TEXT) {
834 // Compute the address
835 u8 *address_far = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
836 + (xcurs + ycurs * nbcols) * 2);
837 while (count-- > 0) {
838 SET_FARVAR(GET_GLOBAL(vmode_g->sstart), *address_far, car);
844 // FIXME gfx mode not complete
845 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
846 u8 cheight = GET_GLOBAL(vparam_g->cheight);
847 u8 bpp = GET_GLOBAL(vmode_g->pixbits);
848 while ((count-- > 0) && (xcurs < nbcols)) {
849 switch (GET_GLOBAL(vmode_g->memmodel)) {
852 write_gfx_char_pl4(car, attr, xcurs, ycurs, nbcols,
856 write_gfx_char_cga(car, attr, xcurs, ycurs, nbcols, bpp);
859 write_gfx_char_lin(car, attr, xcurs, ycurs, nbcols);
866 // -------------------------------------------------------------------
868 biosfn_set_border_color(struct bregs *regs)
870 inb(VGAREG_ACTL_RESET);
871 outb(0x00, VGAREG_ACTL_ADDRESS);
872 u8 al = regs->bl & 0x0f;
875 outb(al, VGAREG_ACTL_WRITE_DATA);
876 u8 bl = regs->bl & 0x10;
879 for (i = 1; i < 4; i++) {
880 outb(i, VGAREG_ACTL_ADDRESS);
882 al = inb(VGAREG_ACTL_READ_DATA);
885 outb(al, VGAREG_ACTL_WRITE_DATA);
887 outb(0x20, VGAREG_ACTL_ADDRESS);
891 biosfn_set_palette(struct bregs *regs)
893 inb(VGAREG_ACTL_RESET);
894 u8 bl = regs->bl & 0x01;
896 for (i = 1; i < 4; i++) {
897 outb(i, VGAREG_ACTL_ADDRESS);
899 u8 al = inb(VGAREG_ACTL_READ_DATA);
902 outb(al, VGAREG_ACTL_WRITE_DATA);
904 outb(0x20, VGAREG_ACTL_ADDRESS);
907 // -------------------------------------------------------------------
909 biosfn_write_pixel(u8 BH, u8 AL, u16 CX, u16 DX)
912 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
915 if (GET_GLOBAL(vmode_g->class) == TEXT)
918 u8 *addr_far, mask, attr, data;
919 switch (GET_GLOBAL(vmode_g->memmodel)) {
922 addr_far = (void*)(CX / 8 + DX * GET_BDA(video_cols));
923 mask = 0x80 >> (CX & 0x07);
924 outw((mask << 8) | 0x08, VGAREG_GRDC_ADDRESS);
925 outw(0x0205, VGAREG_GRDC_ADDRESS);
926 data = GET_FARVAR(SEG_GRAPH, *addr_far);
928 outw(0x1803, VGAREG_GRDC_ADDRESS);
929 SET_FARVAR(SEG_GRAPH, *addr_far, AL);
930 outw(0xff08, VGAREG_GRDC_ADDRESS);
931 outw(0x0005, VGAREG_GRDC_ADDRESS);
932 outw(0x0003, VGAREG_GRDC_ADDRESS);
935 if (GET_GLOBAL(vmode_g->pixbits) == 2)
936 addr_far = (void*)((CX >> 2) + (DX >> 1) * 80);
938 addr_far = (void*)((CX >> 3) + (DX >> 1) * 80);
941 data = GET_FARVAR(SEG_CTEXT, *addr_far);
942 if (GET_GLOBAL(vmode_g->pixbits) == 2) {
943 attr = (AL & 0x03) << ((3 - (CX & 0x03)) * 2);
944 mask = 0x03 << ((3 - (CX & 0x03)) * 2);
946 attr = (AL & 0x01) << (7 - (CX & 0x07));
947 mask = 0x01 << (7 - (CX & 0x07));
955 SET_FARVAR(SEG_CTEXT, *addr_far, data);
958 addr_far = (void*)(CX + DX * (GET_BDA(video_cols) * 8));
959 SET_FARVAR(SEG_GRAPH, *addr_far, AL);
964 // -------------------------------------------------------------------
966 biosfn_read_pixel(u8 BH, u16 CX, u16 DX, u16 *AX)
969 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
972 if (GET_GLOBAL(vmode_g->class) == TEXT)
975 u8 *addr_far, mask, attr=0, data, i;
976 switch (GET_GLOBAL(vmode_g->memmodel)) {
979 addr_far = (void*)(CX / 8 + DX * GET_BDA(video_cols));
980 mask = 0x80 >> (CX & 0x07);
982 for (i = 0; i < 4; i++) {
983 outw((i << 8) | 0x04, VGAREG_GRDC_ADDRESS);
984 data = GET_FARVAR(SEG_GRAPH, *addr_far) & mask;
990 addr_far = (void*)((CX >> 2) + (DX >> 1) * 80);
993 data = GET_FARVAR(SEG_CTEXT, *addr_far);
994 if (GET_GLOBAL(vmode_g->pixbits) == 2)
995 attr = (data >> ((3 - (CX & 0x03)) * 2)) & 0x03;
997 attr = (data >> (7 - (CX & 0x07))) & 0x01;
1000 addr_far = (void*)(CX + DX * (GET_BDA(video_cols) * 8));
1001 attr = GET_FARVAR(SEG_GRAPH, *addr_far);
1004 *AX = (*AX & 0xff00) | attr;
1007 // -------------------------------------------------------------------
1009 biosfn_write_teletype(u8 car, u8 page, u8 attr, u8 flag)
1010 { // flag = WITH_ATTR / NO_ATTR
1011 // special case if page is 0xff, use current page
1013 page = GET_BDA(video_page);
1016 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
1020 // Get the cursor pos for the page
1021 u16 cursor = biosfn_get_cursor_pos(page);
1022 u8 xcurs = cursor & 0x00ff;
1023 u8 ycurs = (cursor & 0xff00) >> 8;
1025 // Get the dimensions
1026 u16 nbrows = GET_BDA(video_rows) + 1;
1027 u16 nbcols = GET_BDA(video_cols);
1049 biosfn_write_teletype(' ', page, attr, flag);
1050 cursor = biosfn_get_cursor_pos(page);
1051 xcurs = cursor & 0x00ff;
1052 ycurs = (cursor & 0xff00) >> 8;
1053 } while (xcurs % 8 == 0);
1058 if (GET_GLOBAL(vmode_g->class) == TEXT) {
1059 // Compute the address
1060 u8 *address_far = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
1061 + (xcurs + ycurs * nbcols) * 2);
1063 SET_FARVAR(GET_GLOBAL(vmode_g->sstart), address_far[0], car);
1064 if (flag == WITH_ATTR)
1065 SET_FARVAR(GET_GLOBAL(vmode_g->sstart), address_far[1], attr);
1067 // FIXME gfx mode not complete
1068 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
1069 u8 cheight = GET_GLOBAL(vparam_g->cheight);
1070 u8 bpp = GET_GLOBAL(vmode_g->pixbits);
1071 switch (GET_GLOBAL(vmode_g->memmodel)) {
1074 write_gfx_char_pl4(car, attr, xcurs, ycurs, nbcols, cheight);
1077 write_gfx_char_cga(car, attr, xcurs, ycurs, nbcols, bpp);
1080 write_gfx_char_lin(car, attr, xcurs, ycurs, nbcols);
1087 // Do we need to wrap ?
1088 if (xcurs == nbcols) {
1092 // Do we need to scroll ?
1093 if (ycurs == nbrows) {
1094 if (GET_GLOBAL(vmode_g->class) == TEXT)
1095 biosfn_scroll(0x01, 0x07, 0, 0, nbrows - 1, nbcols - 1, page,
1098 biosfn_scroll(0x01, 0x00, 0, 0, nbrows - 1, nbcols - 1, page,
1102 // Set the cursor for the page
1106 biosfn_set_cursor_pos(page, cursor);
1109 // -------------------------------------------------------------------
1111 biosfn_get_video_mode(struct bregs *regs)
1113 regs->bh = GET_BDA(video_page);
1114 regs->al = GET_BDA(video_mode) | (GET_BDA(video_ctl) & 0x80);
1115 regs->ah = GET_BDA(video_cols);
1118 // -------------------------------------------------------------------
1120 biosfn_set_overscan_border_color(struct bregs *regs)
1122 inb(VGAREG_ACTL_RESET);
1123 outb(0x11, VGAREG_ACTL_ADDRESS);
1124 outb(regs->bh, VGAREG_ACTL_WRITE_DATA);
1125 outb(0x20, VGAREG_ACTL_ADDRESS);
1128 // -------------------------------------------------------------------
1130 biosfn_set_all_palette_reg(struct bregs *regs)
1132 inb(VGAREG_ACTL_RESET);
1134 u8 *data_far = (u8*)(regs->dx + 0);
1136 for (i = 0; i < 0x10; i++) {
1137 outb(i, VGAREG_ACTL_ADDRESS);
1138 u8 val = GET_FARVAR(regs->es, *data_far);
1139 outb(val, VGAREG_ACTL_WRITE_DATA);
1142 outb(0x11, VGAREG_ACTL_ADDRESS);
1143 outb(GET_FARVAR(regs->es, *data_far), VGAREG_ACTL_WRITE_DATA);
1144 outb(0x20, VGAREG_ACTL_ADDRESS);
1147 // -------------------------------------------------------------------
1149 biosfn_toggle_intensity(struct bregs *regs)
1151 inb(VGAREG_ACTL_RESET);
1152 outb(0x10, VGAREG_ACTL_ADDRESS);
1153 u8 val = (inb(VGAREG_ACTL_READ_DATA) & 0x7f) | ((regs->bl & 0x01) << 3);
1154 outb(val, VGAREG_ACTL_WRITE_DATA);
1155 outb(0x20, VGAREG_ACTL_ADDRESS);
1158 // -------------------------------------------------------------------
1160 biosfn_set_single_palette_reg(u8 reg, u8 val)
1162 inb(VGAREG_ACTL_RESET);
1163 outb(reg, VGAREG_ACTL_ADDRESS);
1164 outb(val, VGAREG_ACTL_WRITE_DATA);
1165 outb(0x20, VGAREG_ACTL_ADDRESS);
1168 // -------------------------------------------------------------------
1170 biosfn_get_single_palette_reg(u8 reg)
1172 inb(VGAREG_ACTL_RESET);
1173 outb(reg, VGAREG_ACTL_ADDRESS);
1174 u8 v = inb(VGAREG_ACTL_READ_DATA);
1175 inb(VGAREG_ACTL_RESET);
1176 outb(0x20, VGAREG_ACTL_ADDRESS);
1180 // -------------------------------------------------------------------
1182 biosfn_read_overscan_border_color(struct bregs *regs)
1184 inb(VGAREG_ACTL_RESET);
1185 outb(0x11, VGAREG_ACTL_ADDRESS);
1186 regs->bh = inb(VGAREG_ACTL_READ_DATA);
1187 inb(VGAREG_ACTL_RESET);
1188 outb(0x20, VGAREG_ACTL_ADDRESS);
1191 // -------------------------------------------------------------------
1193 biosfn_get_all_palette_reg(struct bregs *regs)
1195 u8 *data_far = (u8*)(regs->dx + 0);
1197 for (i = 0; i < 0x10; i++) {
1198 inb(VGAREG_ACTL_RESET);
1199 outb(i, VGAREG_ACTL_ADDRESS);
1200 SET_FARVAR(regs->es, *data_far, inb(VGAREG_ACTL_READ_DATA));
1203 inb(VGAREG_ACTL_RESET);
1204 outb(0x11, VGAREG_ACTL_ADDRESS);
1205 SET_FARVAR(regs->es, *data_far, inb(VGAREG_ACTL_READ_DATA));
1206 inb(VGAREG_ACTL_RESET);
1207 outb(0x20, VGAREG_ACTL_ADDRESS);
1210 // -------------------------------------------------------------------
1212 biosfn_set_single_dac_reg(struct bregs *regs)
1214 outb(regs->bl, VGAREG_DAC_WRITE_ADDRESS);
1215 outb(regs->dh, VGAREG_DAC_DATA);
1216 outb(regs->ch, VGAREG_DAC_DATA);
1217 outb(regs->cl, VGAREG_DAC_DATA);
1220 // -------------------------------------------------------------------
1222 biosfn_set_all_dac_reg(struct bregs *regs)
1224 outb(regs->bl, VGAREG_DAC_WRITE_ADDRESS);
1225 u8 *data_far = (u8*)(regs->dx + 0);
1226 int count = regs->cx;
1228 outb(GET_FARVAR(regs->es, *data_far), VGAREG_DAC_DATA);
1230 outb(GET_FARVAR(regs->es, *data_far), VGAREG_DAC_DATA);
1232 outb(GET_FARVAR(regs->es, *data_far), VGAREG_DAC_DATA);
1238 // -------------------------------------------------------------------
1240 biosfn_select_video_dac_color_page(struct bregs *regs)
1242 inb(VGAREG_ACTL_RESET);
1243 outb(0x10, VGAREG_ACTL_ADDRESS);
1244 u8 val = inb(VGAREG_ACTL_READ_DATA);
1245 if (!(regs->bl & 0x01)) {
1246 val = (val & 0x7f) | (regs->bh << 7);
1247 outb(val, VGAREG_ACTL_WRITE_DATA);
1248 outb(0x20, VGAREG_ACTL_ADDRESS);
1251 inb(VGAREG_ACTL_RESET);
1252 outb(0x14, VGAREG_ACTL_ADDRESS);
1257 outb(bh, VGAREG_ACTL_WRITE_DATA);
1258 outb(0x20, VGAREG_ACTL_ADDRESS);
1261 // -------------------------------------------------------------------
1263 biosfn_read_single_dac_reg(struct bregs *regs)
1265 outb(regs->bl, VGAREG_DAC_READ_ADDRESS);
1266 regs->dh = inb(VGAREG_DAC_DATA);
1267 regs->ch = inb(VGAREG_DAC_DATA);
1268 regs->cl = inb(VGAREG_DAC_DATA);
1271 // -------------------------------------------------------------------
1273 biosfn_read_all_dac_reg(struct bregs *regs)
1275 outb(regs->bl, VGAREG_DAC_READ_ADDRESS);
1276 u8 *data_far = (u8*)(regs->dx + 0);
1277 int count = regs->cx;
1279 SET_FARVAR(regs->es, *data_far, inb(VGAREG_DAC_DATA));
1281 SET_FARVAR(regs->es, *data_far, inb(VGAREG_DAC_DATA));
1283 SET_FARVAR(regs->es, *data_far, inb(VGAREG_DAC_DATA));
1289 // -------------------------------------------------------------------
1291 biosfn_set_pel_mask(struct bregs *regs)
1293 outb(regs->bl, VGAREG_PEL_MASK);
1296 // -------------------------------------------------------------------
1298 biosfn_read_pel_mask(struct bregs *regs)
1300 regs->bl = inb(VGAREG_PEL_MASK);
1303 // -------------------------------------------------------------------
1305 biosfn_read_video_dac_state(struct bregs *regs)
1307 inb(VGAREG_ACTL_RESET);
1308 outb(0x10, VGAREG_ACTL_ADDRESS);
1309 u8 val1 = inb(VGAREG_ACTL_READ_DATA) >> 7;
1311 inb(VGAREG_ACTL_RESET);
1312 outb(0x14, VGAREG_ACTL_ADDRESS);
1313 u8 val2 = inb(VGAREG_ACTL_READ_DATA) & 0x0f;
1317 inb(VGAREG_ACTL_RESET);
1318 outb(0x20, VGAREG_ACTL_ADDRESS);
1324 // -------------------------------------------------------------------
1328 outw(0x0100, VGAREG_SEQU_ADDRESS);
1329 outw(0x0402, VGAREG_SEQU_ADDRESS);
1330 outw(0x0704, VGAREG_SEQU_ADDRESS);
1331 outw(0x0300, VGAREG_SEQU_ADDRESS);
1332 outw(0x0204, VGAREG_GRDC_ADDRESS);
1333 outw(0x0005, VGAREG_GRDC_ADDRESS);
1334 outw(0x0406, VGAREG_GRDC_ADDRESS);
1338 release_font_access()
1340 outw(0x0100, VGAREG_SEQU_ADDRESS);
1341 outw(0x0302, VGAREG_SEQU_ADDRESS);
1342 outw(0x0304, VGAREG_SEQU_ADDRESS);
1343 outw(0x0300, VGAREG_SEQU_ADDRESS);
1344 u16 v = inw(VGAREG_READ_MISC_OUTPUT);
1345 v = ((v & 0x01) << 10) | 0x0a06;
1346 outw(v, VGAREG_GRDC_ADDRESS);
1347 outw(0x0004, VGAREG_GRDC_ADDRESS);
1348 outw(0x1005, VGAREG_GRDC_ADDRESS);
1352 set_scan_lines(u8 lines)
1354 u16 crtc_addr = GET_BDA(crtc_address);
1355 outb(0x09, crtc_addr);
1356 u8 crtc_r9 = inb(crtc_addr + 1);
1357 crtc_r9 = (crtc_r9 & 0xe0) | (lines - 1);
1358 outb(crtc_r9, crtc_addr + 1);
1360 biosfn_set_cursor_shape(0x06, 0x07);
1362 biosfn_set_cursor_shape(lines - 4, lines - 3);
1363 SET_BDA(char_height, lines);
1364 outb(0x12, crtc_addr);
1365 u16 vde = inb(crtc_addr + 1);
1366 outb(0x07, crtc_addr);
1367 u8 ovl = inb(crtc_addr + 1);
1368 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
1369 u8 rows = vde / lines;
1370 SET_BDA(video_rows, rows - 1);
1371 u16 cols = GET_BDA(video_cols);
1372 SET_BDA(video_pagesize, rows * cols * 2);
1376 biosfn_load_text_user_pat(u8 AL, u16 ES, u16 BP, u16 CX, u16 DX, u8 BL,
1380 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1382 for (i = 0; i < CX; i++) {
1383 void *src_far = (void*)(BP + i * BH);
1384 void *dest_far = (void*)(blockaddr + (DX + i) * 32);
1385 memcpy_far(SEG_GRAPH, dest_far, ES, src_far, BH);
1387 release_font_access();
1393 biosfn_load_text_8_14_pat(u8 AL, u8 BL)
1396 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1398 for (i = 0; i < 0x100; i++) {
1400 void *dest_far = (void*)(blockaddr + i * 32);
1401 memcpy_far(SEG_GRAPH, dest_far, get_global_seg(), &vgafont14[src], 14);
1403 release_font_access();
1409 biosfn_load_text_8_8_pat(u8 AL, u8 BL)
1412 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1414 for (i = 0; i < 0x100; i++) {
1416 void *dest_far = (void*)(blockaddr + i * 32);
1417 memcpy_far(SEG_GRAPH, dest_far, get_global_seg(), &vgafont8[src], 8);
1419 release_font_access();
1424 // -------------------------------------------------------------------
1426 biosfn_set_text_block_specifier(struct bregs *regs)
1428 outw((regs->bl << 8) | 0x03, VGAREG_SEQU_ADDRESS);
1431 // -------------------------------------------------------------------
1433 biosfn_load_text_8_16_pat(u8 AL, u8 BL)
1436 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1438 for (i = 0; i < 0x100; i++) {
1440 void *dest_far = (void*)(blockaddr + i * 32);
1441 memcpy_far(SEG_GRAPH, dest_far, get_global_seg(), &vgafont16[src], 16);
1443 release_font_access();
1448 // -------------------------------------------------------------------
1450 biosfn_get_font_info(u8 BH, u16 *ES, u16 *BP, u16 *CX, u16 *DX)
1454 u32 segoff = GET_IVT(0x1f).segoff;
1460 u32 segoff = GET_IVT(0x43).segoff;
1466 *ES = get_global_seg();
1467 *BP = (u32)vgafont14;
1470 *ES = get_global_seg();
1471 *BP = (u32)vgafont8;
1474 *ES = get_global_seg();
1475 *BP = (u32)vgafont8 + 128 * 8;
1478 *ES = get_global_seg();
1479 *BP = (u32)vgafont14alt;
1482 *ES = get_global_seg();
1483 *BP = (u32)vgafont16;
1486 *ES = get_global_seg();
1487 *BP = (u32)vgafont16alt;
1490 dprintf(1, "Get font info BH(%02x) was discarded\n", BH);
1493 // Set byte/char of on screen font
1494 *CX = GET_BDA(char_height) & 0xff;
1496 // Set Highest char row
1497 *DX = GET_BDA(video_rows);
1500 // -------------------------------------------------------------------
1502 biosfn_get_ega_info(struct bregs *regs)
1504 regs->cx = GET_BDA(video_switches) & 0x0f;
1505 regs->ax = GET_BDA(crtc_address);
1506 if (regs->ax == VGAREG_MDA_CRTC_ADDRESS)
1512 // -------------------------------------------------------------------
1514 biosfn_select_vert_res(struct bregs *regs)
1516 u8 mctl = GET_BDA(modeset_ctl);
1517 u8 vswt = GET_BDA(video_switches);
1522 mctl = (mctl & ~0x10) | 0x80;
1523 vswt = (vswt & ~0x0f) | 0x08;
1528 vswt = (vswt & ~0x0f) | 0x09;
1532 mctl = (mctl & ~0x80) | 0x10;
1533 vswt = (vswt & ~0x0f) | 0x09;
1536 dprintf(1, "Select vert res (%02x) was discarded\n", regs->al);
1539 SET_BDA(modeset_ctl, mctl);
1540 SET_BDA(video_switches, vswt);
1545 biosfn_enable_default_palette_loading(struct bregs *regs)
1547 u8 v = (regs->al & 0x01) << 3;
1548 u8 mctl = GET_BDA(video_ctl) & ~0x08;
1549 SET_BDA(video_ctl, mctl | v);
1554 biosfn_enable_video_addressing(struct bregs *regs)
1556 u8 v = ((regs->al << 1) & 0x02) ^ 0x02;
1557 u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
1558 outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
1564 biosfn_enable_grayscale_summing(struct bregs *regs)
1566 u8 v = ((regs->al << 1) & 0x02) ^ 0x02;
1567 u8 v2 = GET_BDA(modeset_ctl) & ~0x02;
1568 SET_BDA(modeset_ctl, v | v2);
1573 biosfn_enable_cursor_emulation(struct bregs *regs)
1575 u8 v = (regs->al & 0x01) ^ 0x01;
1576 u8 v2 = GET_BDA(modeset_ctl) & ~0x01;
1577 SET_BDA(modeset_ctl, v | v2);
1581 // -------------------------------------------------------------------
1583 biosfn_write_string(u8 flag, u8 page, u8 attr, u16 count, u8 row, u8 col,
1584 u16 seg, u8 *offset_far)
1586 // Read curs info for the page
1587 u16 oldcurs = biosfn_get_cursor_pos(page);
1589 // if row=0xff special case : use current cursor position
1591 col = oldcurs & 0x00ff;
1592 row = (oldcurs & 0xff00) >> 8;
1598 biosfn_set_cursor_pos(page, newcurs);
1600 while (count-- != 0) {
1601 u8 car = GET_FARVAR(seg, *offset_far);
1603 if ((flag & 0x02) != 0) {
1604 attr = GET_FARVAR(seg, *offset_far);
1608 biosfn_write_teletype(car, page, attr, WITH_ATTR);
1611 // Set back curs pos
1612 if ((flag & 0x01) == 0)
1613 biosfn_set_cursor_pos(page, oldcurs);
1616 // -------------------------------------------------------------------
1618 biosfn_read_display_code(struct bregs *regs)
1620 regs->bx = GET_BDA(dcc_index);
1625 biosfn_set_display_code(struct bregs *regs)
1627 SET_BDA(dcc_index, regs->bl);
1628 dprintf(1, "Alternate Display code (%02x) was discarded\n", regs->bh);
1632 // -------------------------------------------------------------------
1634 biosfn_read_state_info(u16 BX, u16 ES, u16 DI)
1636 // Address of static functionality table
1637 SET_FARVAR(ES, *(u16*)(DI + 0x00), (u32)static_functionality);
1638 SET_FARVAR(ES, *(u16*)(DI + 0x02), get_global_seg());
1640 // Hard coded copy from BIOS area. Should it be cleaner ?
1641 memcpy_far(ES, (void*)(DI + 0x04), SEG_BDA, (void*)0x49, 30);
1642 memcpy_far(ES, (void*)(DI + 0x22), SEG_BDA, (void*)0x84, 3);
1644 SET_FARVAR(ES, *(u8*)(DI + 0x25), GET_BDA(dcc_index));
1645 SET_FARVAR(ES, *(u8*)(DI + 0x26), 0);
1646 SET_FARVAR(ES, *(u8*)(DI + 0x27), 16);
1647 SET_FARVAR(ES, *(u8*)(DI + 0x28), 0);
1648 SET_FARVAR(ES, *(u8*)(DI + 0x29), 8);
1649 SET_FARVAR(ES, *(u8*)(DI + 0x2a), 2);
1650 SET_FARVAR(ES, *(u8*)(DI + 0x2b), 0);
1651 SET_FARVAR(ES, *(u8*)(DI + 0x2c), 0);
1652 SET_FARVAR(ES, *(u8*)(DI + 0x31), 3);
1653 SET_FARVAR(ES, *(u8*)(DI + 0x32), 0);
1655 memset_far(ES, (void*)(DI + 0x33), 0, 13);
1658 // -------------------------------------------------------------------
1659 // -------------------------------------------------------------------
1661 biosfn_read_video_state_size(u16 CX)
1667 size += (5 + 8 + 5) * 2 + 6;
1669 size += 3 + 256 * 3 + 1;
1674 biosfn_save_video_state(u16 CX, u16 ES, u16 BX)
1676 u16 crtc_addr = GET_BDA(crtc_address);
1678 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_ADDRESS));
1680 SET_FARVAR(ES, *(u8*)(BX+0), inb(crtc_addr));
1682 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_GRDC_ADDRESS));
1684 inb(VGAREG_ACTL_RESET);
1685 u16 ar_index = inb(VGAREG_ACTL_ADDRESS);
1686 SET_FARVAR(ES, *(u8*)(BX+0), ar_index);
1688 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_READ_FEATURE_CTL));
1692 for (i = 1; i <= 4; i++) {
1693 outb(i, VGAREG_SEQU_ADDRESS);
1694 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_DATA));
1697 outb(0, VGAREG_SEQU_ADDRESS);
1698 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_DATA));
1701 for (i = 0; i <= 0x18; i++) {
1703 SET_FARVAR(ES, *(u8*)(BX+0), inb(crtc_addr + 1));
1707 for (i = 0; i <= 0x13; i++) {
1708 inb(VGAREG_ACTL_RESET);
1709 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
1710 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_ACTL_READ_DATA));
1713 inb(VGAREG_ACTL_RESET);
1715 for (i = 0; i <= 8; i++) {
1716 outb(i, VGAREG_GRDC_ADDRESS);
1717 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_GRDC_DATA));
1721 SET_FARVAR(ES, *(u16*)(BX+0), crtc_addr);
1724 /* XXX: read plane latches */
1725 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1727 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1729 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1731 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1735 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_mode));
1737 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_cols));
1739 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_pagesize));
1741 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(crtc_address));
1743 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_rows));
1745 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(char_height));
1747 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_ctl));
1749 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_switches));
1751 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(modeset_ctl));
1753 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(cursor_type));
1756 for (i = 0; i < 8; i++) {
1757 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(cursor_pos[i]));
1760 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_pagestart));
1762 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_page));
1765 SET_FARVAR(ES, *(u16*)(BX+0), GET_FARVAR(0, *(u16*)(0x1f * 4)));
1767 SET_FARVAR(ES, *(u16*)(BX+0), GET_FARVAR(0, *(u16*)(0x1f * 4 + 2)));
1769 SET_FARVAR(ES, *(u16*)(BX+0), GET_FARVAR(0, *(u16*)(0x43 * 4)));
1771 SET_FARVAR(ES, *(u16*)(BX+0), GET_FARVAR(0, *(u16*)(0x43 * 4 + 2)));
1775 /* XXX: check this */
1776 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_STATE));
1777 BX++; /* read/write mode dac */
1778 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_WRITE_ADDRESS));
1779 BX++; /* pix address */
1780 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_PEL_MASK));
1782 // Set the whole dac always, from 0
1783 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
1785 for (i = 0; i < 256 * 3; i++) {
1786 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_DATA));
1789 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1790 BX++; /* color select register */
1796 biosfn_restore_video_state(u16 CX, u16 ES, u16 BX)
1799 // Reset Attribute Ctl flip-flop
1800 inb(VGAREG_ACTL_RESET);
1802 u16 crtc_addr = GET_FARVAR(ES, *(u16*)(BX + 0x40));
1807 for (i = 1; i <= 4; i++) {
1808 outb(i, VGAREG_SEQU_ADDRESS);
1809 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_SEQU_DATA);
1812 outb(0, VGAREG_SEQU_ADDRESS);
1813 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_SEQU_DATA);
1816 // Disable CRTC write protection
1817 outw(0x0011, crtc_addr);
1819 for (i = 0; i <= 0x18; i++) {
1822 outb(GET_FARVAR(ES, *(u8*)(BX+0)), crtc_addr + 1);
1826 // select crtc base address
1827 u16 v = inb(VGAREG_READ_MISC_OUTPUT) & ~0x01;
1828 if (crtc_addr == VGAREG_VGA_CRTC_ADDRESS)
1830 outb(v, VGAREG_WRITE_MISC_OUTPUT);
1832 // enable write protection if needed
1833 outb(0x11, crtc_addr);
1834 outb(GET_FARVAR(ES, *(u8*)(BX - 0x18 + 0x11)), crtc_addr + 1);
1836 // Set Attribute Ctl
1837 u16 ar_index = GET_FARVAR(ES, *(u8*)(addr1 + 0x03));
1838 inb(VGAREG_ACTL_RESET);
1839 for (i = 0; i <= 0x13; i++) {
1840 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
1841 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_ACTL_WRITE_DATA);
1844 outb(ar_index, VGAREG_ACTL_ADDRESS);
1845 inb(VGAREG_ACTL_RESET);
1847 for (i = 0; i <= 8; i++) {
1848 outb(i, VGAREG_GRDC_ADDRESS);
1849 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_GRDC_DATA);
1852 BX += 2; /* crtc_addr */
1853 BX += 4; /* plane latches */
1855 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), VGAREG_SEQU_ADDRESS);
1857 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), crtc_addr);
1859 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), VGAREG_GRDC_ADDRESS);
1862 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), crtc_addr - 0x4 + 0xa);
1866 SET_BDA(video_mode, GET_FARVAR(ES, *(u8*)(BX+0)));
1868 SET_BDA(video_cols, GET_FARVAR(ES, *(u16*)(BX+0)));
1870 SET_BDA(video_pagesize, GET_FARVAR(ES, *(u16*)(BX+0)));
1872 SET_BDA(crtc_address, GET_FARVAR(ES, *(u16*)(BX+0)));
1874 SET_BDA(video_rows, GET_FARVAR(ES, *(u8*)(BX+0)));
1876 SET_BDA(char_height, GET_FARVAR(ES, *(u16*)(BX+0)));
1878 SET_BDA(video_ctl, GET_FARVAR(ES, *(u8*)(BX+0)));
1880 SET_BDA(video_switches, GET_FARVAR(ES, *(u8*)(BX+0)));
1882 SET_BDA(modeset_ctl, GET_FARVAR(ES, *(u8*)(BX+0)));
1884 SET_BDA(cursor_type, GET_FARVAR(ES, *(u16*)(BX+0)));
1887 for (i = 0; i < 8; i++) {
1888 SET_BDA(cursor_pos[i], GET_FARVAR(ES, *(u16*)(BX+0)));
1891 SET_BDA(video_pagestart, GET_FARVAR(ES, *(u16*)(BX+0)));
1893 SET_BDA(video_page, GET_FARVAR(ES, *(u8*)(BX+0)));
1896 SET_IVT(0x1f, GET_FARVAR(ES, *(u16*)(BX+2)), GET_FARVAR(ES, *(u16*)(BX+0)));
1898 SET_IVT(0x43, GET_FARVAR(ES, *(u16*)(BX+2)), GET_FARVAR(ES, *(u16*)(BX+0)));
1903 u16 v = GET_FARVAR(ES, *(u8*)(BX+0));
1905 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_PEL_MASK);
1907 // Set the whole dac always, from 0
1908 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
1910 for (i = 0; i < 256 * 3; i++) {
1911 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_DAC_DATA);
1915 outb(v, VGAREG_DAC_WRITE_ADDRESS);
1921 /****************************************************************
1922 * VGA int 10 handler
1923 ****************************************************************/
1926 handle_1000(struct bregs *regs)
1929 biosfn_set_video_mode(regs->al);
1930 switch(regs->al & 0x7F) {
1949 handle_1001(struct bregs *regs)
1951 biosfn_set_cursor_shape(regs->ch, regs->cl);
1955 handle_1002(struct bregs *regs)
1957 biosfn_set_cursor_pos(regs->bh, regs->dx);
1961 handle_1003(struct bregs *regs)
1963 regs->cx = biosfn_get_cursor_shape(regs->bh);
1964 regs->dx = biosfn_get_cursor_pos(regs->bh);
1967 // Read light pen pos (unimplemented)
1969 handle_1004(struct bregs *regs)
1972 regs->ax = regs->bx = regs->cx = regs->dx = 0;
1976 handle_1005(struct bregs *regs)
1978 biosfn_set_active_page(regs->al);
1982 handle_1006(struct bregs *regs)
1984 biosfn_scroll(regs->al, regs->bh, regs->ch, regs->cl, regs->dh, regs->dl
1989 handle_1007(struct bregs *regs)
1991 biosfn_scroll(regs->al, regs->bh, regs->ch, regs->cl, regs->dh, regs->dl
1992 , 0xFF, SCROLL_DOWN);
1996 handle_1008(struct bregs *regs)
1999 biosfn_read_char_attr(regs->bh, ®s->ax);
2003 handle_1009(struct bregs *regs)
2006 biosfn_write_char_attr(regs->al, regs->bh, regs->bl, regs->cx);
2010 handle_100a(struct bregs *regs)
2013 biosfn_write_char_only(regs->al, regs->bh, regs->bl, regs->cx);
2018 handle_100b00(struct bregs *regs)
2021 biosfn_set_border_color(regs);
2025 handle_100b01(struct bregs *regs)
2028 biosfn_set_palette(regs);
2032 handle_100bXX(struct bregs *regs)
2038 handle_100b(struct bregs *regs)
2041 case 0x00: handle_100b00(regs); break;
2042 case 0x01: handle_100b01(regs); break;
2043 default: handle_100bXX(regs); break;
2049 handle_100c(struct bregs *regs)
2052 biosfn_write_pixel(regs->bh, regs->al, regs->cx, regs->dx);
2056 handle_100d(struct bregs *regs)
2059 biosfn_read_pixel(regs->bh, regs->cx, regs->dx, ®s->ax);
2063 handle_100e(struct bregs *regs)
2065 // Ralf Brown Interrupt list is WRONG on bh(page)
2066 // We do output only on the current page !
2067 biosfn_write_teletype(regs->al, 0xff, regs->bl, NO_ATTR);
2071 handle_100f(struct bregs *regs)
2074 biosfn_get_video_mode(regs);
2079 handle_101000(struct bregs *regs)
2081 if (regs->bl > 0x14)
2083 biosfn_set_single_palette_reg(regs->bl, regs->bh);
2087 handle_101001(struct bregs *regs)
2090 biosfn_set_overscan_border_color(regs);
2094 handle_101002(struct bregs *regs)
2097 biosfn_set_all_palette_reg(regs);
2101 handle_101003(struct bregs *regs)
2104 biosfn_toggle_intensity(regs);
2108 handle_101007(struct bregs *regs)
2110 if (regs->bl > 0x14)
2112 regs->bh = biosfn_get_single_palette_reg(regs->bl);
2116 handle_101008(struct bregs *regs)
2119 biosfn_read_overscan_border_color(regs);
2123 handle_101009(struct bregs *regs)
2126 biosfn_get_all_palette_reg(regs);
2130 handle_101010(struct bregs *regs)
2133 biosfn_set_single_dac_reg(regs);
2137 handle_101012(struct bregs *regs)
2140 biosfn_set_all_dac_reg(regs);
2144 handle_101013(struct bregs *regs)
2147 biosfn_select_video_dac_color_page(regs);
2151 handle_101015(struct bregs *regs)
2154 biosfn_read_single_dac_reg(regs);
2158 handle_101017(struct bregs *regs)
2161 biosfn_read_all_dac_reg(regs);
2165 handle_101018(struct bregs *regs)
2168 biosfn_set_pel_mask(regs);
2172 handle_101019(struct bregs *regs)
2175 biosfn_read_pel_mask(regs);
2179 handle_10101a(struct bregs *regs)
2182 biosfn_read_video_dac_state(regs);
2186 handle_10101b(struct bregs *regs)
2188 biosfn_perform_gray_scale_summing(regs->bx, regs->cx);
2192 handle_1010XX(struct bregs *regs)
2198 handle_1010(struct bregs *regs)
2201 case 0x00: handle_101000(regs); break;
2202 case 0x01: handle_101001(regs); break;
2203 case 0x02: handle_101002(regs); break;
2204 case 0x03: handle_101003(regs); break;
2205 case 0x07: handle_101007(regs); break;
2206 case 0x08: handle_101008(regs); break;
2207 case 0x09: handle_101009(regs); break;
2208 case 0x10: handle_101010(regs); break;
2209 case 0x12: handle_101012(regs); break;
2210 case 0x13: handle_101013(regs); break;
2211 case 0x15: handle_101015(regs); break;
2212 case 0x17: handle_101017(regs); break;
2213 case 0x18: handle_101018(regs); break;
2214 case 0x19: handle_101019(regs); break;
2215 case 0x1a: handle_10101a(regs); break;
2216 case 0x1b: handle_10101b(regs); break;
2217 default: handle_1010XX(regs); break;
2223 handle_101100(struct bregs *regs)
2226 biosfn_load_text_user_pat(regs->al, regs->es, 0 // XXX - regs->bp
2227 , regs->cx, regs->dx, regs->bl, regs->bh);
2231 handle_101101(struct bregs *regs)
2234 biosfn_load_text_8_14_pat(regs->al, regs->bl);
2238 handle_101102(struct bregs *regs)
2241 biosfn_load_text_8_8_pat(regs->al, regs->bl);
2245 handle_101103(struct bregs *regs)
2248 biosfn_set_text_block_specifier(regs);
2252 handle_101104(struct bregs *regs)
2255 biosfn_load_text_8_16_pat(regs->al, regs->bl);
2259 handle_101110(struct bregs *regs)
2261 handle_101100(regs);
2265 handle_101111(struct bregs *regs)
2267 handle_101101(regs);
2271 handle_101112(struct bregs *regs)
2273 handle_101102(regs);
2277 handle_101114(struct bregs *regs)
2279 handle_101104(regs);
2283 handle_101130(struct bregs *regs)
2286 biosfn_get_font_info(regs->bh, ®s->es, 0 // ®s->bp
2287 , ®s->cx, ®s->dx);
2291 handle_1011XX(struct bregs *regs)
2297 handle_1011(struct bregs *regs)
2300 case 0x00: handle_101100(regs); break;
2301 case 0x01: handle_101101(regs); break;
2302 case 0x02: handle_101102(regs); break;
2303 case 0x03: handle_101103(regs); break;
2304 case 0x04: handle_101104(regs); break;
2305 case 0x10: handle_101110(regs); break;
2306 case 0x11: handle_101111(regs); break;
2307 case 0x12: handle_101112(regs); break;
2308 case 0x14: handle_101114(regs); break;
2309 case 0x30: handle_101130(regs); break;
2310 default: handle_1011XX(regs); break;
2316 handle_101210(struct bregs *regs)
2319 biosfn_get_ega_info(regs);
2323 handle_101230(struct bregs *regs)
2326 biosfn_select_vert_res(regs);
2330 handle_101231(struct bregs *regs)
2333 biosfn_enable_default_palette_loading(regs);
2337 handle_101232(struct bregs *regs)
2340 biosfn_enable_video_addressing(regs);
2344 handle_101233(struct bregs *regs)
2347 biosfn_enable_grayscale_summing(regs);
2351 handle_101234(struct bregs *regs)
2354 biosfn_enable_cursor_emulation(regs);
2358 handle_101235(struct bregs *regs)
2365 handle_101236(struct bregs *regs)
2372 handle_1012XX(struct bregs *regs)
2378 handle_1012(struct bregs *regs)
2381 case 0x10: handle_101210(regs); break;
2382 case 0x30: handle_101230(regs); break;
2383 case 0x31: handle_101231(regs); break;
2384 case 0x32: handle_101232(regs); break;
2385 case 0x33: handle_101233(regs); break;
2386 case 0x34: handle_101234(regs); break;
2387 case 0x35: handle_101235(regs); break;
2388 case 0x36: handle_101236(regs); break;
2389 default: handle_1012XX(regs); break;
2392 // XXX - cirrus has 1280, 1281, 1282, 1285, 129a, 12a0, 12a1, 12a2, 12ae
2397 handle_1013(struct bregs *regs)
2400 biosfn_write_string(regs->al, regs->bh, regs->bl, regs->cx
2401 , regs->dh, regs->dl, regs->es, 0); // regs->bp);
2406 handle_101a00(struct bregs *regs)
2409 biosfn_read_display_code(regs);
2413 handle_101a01(struct bregs *regs)
2416 biosfn_set_display_code(regs);
2420 handle_101aXX(struct bregs *regs)
2426 handle_101a(struct bregs *regs)
2429 case 0x00: handle_101a00(regs); break;
2430 case 0x01: handle_101a01(regs); break;
2431 default: handle_101aXX(regs); break;
2437 handle_101b(struct bregs *regs)
2440 biosfn_read_state_info(regs->bx, regs->es, regs->di);
2446 handle_101c00(struct bregs *regs)
2449 regs->bx = biosfn_read_video_state_size(regs->cx);
2453 handle_101c01(struct bregs *regs)
2456 biosfn_save_video_state(regs->cx, regs->es, regs->bx);
2460 handle_101c02(struct bregs *regs)
2463 biosfn_restore_video_state(regs->cx, regs->es, regs->bx);
2467 handle_101cXX(struct bregs *regs)
2473 handle_101c(struct bregs *regs)
2476 case 0x00: handle_101c00(regs); break;
2477 case 0x01: handle_101c01(regs); break;
2478 case 0x02: handle_101c02(regs); break;
2479 default: handle_101cXX(regs); break;
2485 handle_104f00(struct bregs *regs)
2487 // XXX - vbe_biosfn_return_controller_information(&AX,ES,DI);
2488 // XXX - OR cirrus_vesa_00h
2492 handle_104f01(struct bregs *regs)
2494 // XXX - vbe_biosfn_return_mode_information(&AX,CX,ES,DI);
2495 // XXX - OR cirrus_vesa_01h
2499 handle_104f02(struct bregs *regs)
2501 // XXX - vbe_biosfn_set_mode(&AX,BX,ES,DI);
2502 // XXX - OR cirrus_vesa_02h
2506 handle_104f03(struct bregs *regs)
2508 // XXX - vbe_biosfn_return_current_mode
2509 // XXX - OR cirrus_vesa_03h
2513 handle_104f04(struct bregs *regs)
2515 // XXX - vbe_biosfn_save_restore_state(&AX, CX, DX, ES, &BX);
2519 handle_104f05(struct bregs *regs)
2521 // XXX - vbe_biosfn_display_window_control
2522 // XXX - OR cirrus_vesa_05h
2526 handle_104f06(struct bregs *regs)
2528 // XXX - vbe_biosfn_set_get_logical_scan_line_length
2529 // XXX - OR cirrus_vesa_06h
2533 handle_104f07(struct bregs *regs)
2535 // XXX - vbe_biosfn_set_get_display_start
2536 // XXX - OR cirrus_vesa_07h
2540 handle_104f08(struct bregs *regs)
2542 // XXX - vbe_biosfn_set_get_dac_palette_format
2546 handle_104f0a(struct bregs *regs)
2548 // XXX - vbe_biosfn_return_protected_mode_interface
2552 handle_104fXX(struct bregs *regs)
2559 handle_104f(struct bregs *regs)
2562 handle_104fXX(regs);
2566 // XXX - check vbe_has_vbe_display()?
2569 case 0x00: handle_104f00(regs); break;
2570 case 0x01: handle_104f01(regs); break;
2571 case 0x02: handle_104f02(regs); break;
2572 case 0x03: handle_104f03(regs); break;
2573 case 0x04: handle_104f04(regs); break;
2574 case 0x05: handle_104f05(regs); break;
2575 case 0x06: handle_104f06(regs); break;
2576 case 0x07: handle_104f07(regs); break;
2577 case 0x08: handle_104f08(regs); break;
2578 case 0x0a: handle_104f0a(regs); break;
2579 default: handle_104fXX(regs); break;
2585 handle_10XX(struct bregs *regs)
2590 // INT 10h Video Support Service Entry Point
2592 handle_10(struct bregs *regs)
2594 debug_enter(regs, DEBUG_VGA_10);
2596 case 0x00: handle_1000(regs); break;
2597 case 0x01: handle_1001(regs); break;
2598 case 0x02: handle_1002(regs); break;
2599 case 0x03: handle_1003(regs); break;
2600 case 0x04: handle_1004(regs); break;
2601 case 0x05: handle_1005(regs); break;
2602 case 0x06: handle_1006(regs); break;
2603 case 0x07: handle_1007(regs); break;
2604 case 0x08: handle_1008(regs); break;
2605 case 0x09: handle_1009(regs); break;
2606 case 0x0a: handle_100a(regs); break;
2607 case 0x0b: handle_100b(regs); break;
2608 case 0x0c: handle_100c(regs); break;
2609 case 0x0d: handle_100d(regs); break;
2610 case 0x0e: handle_100e(regs); break;
2611 case 0x0f: handle_100f(regs); break;
2612 case 0x10: handle_1010(regs); break;
2613 case 0x11: handle_1011(regs); break;
2614 case 0x12: handle_1012(regs); break;
2615 case 0x13: handle_1013(regs); break;
2616 case 0x1a: handle_101a(regs); break;
2617 case 0x1b: handle_101b(regs); break;
2618 case 0x1c: handle_101c(regs); break;
2619 case 0x4f: handle_104f(regs); break;
2620 default: handle_10XX(regs); break;
2625 /****************************************************************
2627 ****************************************************************/
2632 // init detected hardware BIOS Area
2633 // set 80x25 color (not clear from RBIL but usual)
2634 u16 eqf = GET_BDA(equipment_list_flags);
2635 SET_BDA(equipment_list_flags, (eqf & 0xffcf) | 0x20);
2637 // Just for the first int10 find its children
2639 // the default char height
2640 SET_BDA(char_height, 0x10);
2643 SET_BDA(video_ctl, 0x60);
2645 // Set the basic screen we have
2646 SET_BDA(video_switches, 0xf9);
2648 // Set the basic modeset options
2649 SET_BDA(modeset_ctl, 0x51);
2651 // Set the default MSR
2652 SET_BDA(video_msr, 0x09);
2658 // switch to color mode and enable CPU access 480 lines
2659 outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
2660 // more than 64k 3C4/04
2661 outb(0x04, VGAREG_SEQU_ADDRESS);
2662 outb(0x02, VGAREG_SEQU_DATA);
2666 vga_post(struct bregs *regs)
2668 debug_enter(regs, DEBUG_VGA_POST);
2676 extern void entry_10(void);
2677 SET_IVT(0x10, get_global_seg(), (u32)entry_10);
2682 // XXX - clear screen and display info
2685 SET_VGA(video_save_pointer_table[0], (u32)video_param_table);
2686 SET_VGA(video_save_pointer_table[1], get_global_seg());
2689 extern u8 _rom_header_size, _rom_header_checksum;
2690 SET_VGA(_rom_header_checksum, 0);
2691 u8 sum = -checksum_far(get_global_seg(), 0, _rom_header_size * 512);
2692 SET_VGA(_rom_header_checksum, sum);