2 * This file is part of the superiotool project.
4 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include "superiotool.h"
23 #define DEVICE_ID_REG_OLD 0x09
25 #define DEVICE_ID_REG 0x20
26 #define DEVICE_REV_REG 0x21
29 * The ID entries must be in 0xYYZ format, where YY is the device ID,
30 * and Z is bits 7..4 of the device revision register. We do not match
31 * bits 3..0 of the device revision here (at least for newer Super I/Os).
33 * But some of the older versions use both bytes (0x20 and 0x21), where
34 * register 0x21 holds the ID and the full 8 bits of 0x21 hold the revision.
36 * Some other Super I/Os only use bits 3..0 of 0x09 as ID.
38 const static struct superio_registers reg_table[] = {
39 {0x527, "W83977CTF", {
41 {0x52f, "W83977EF/EG", {
45 {0x601, "W83697HF/F/HG", { /* No G version? */
47 {0x07,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x28,0x29,
49 {NANA,0x60,NANA,0xff,0x00,0x00,0x00,0x00,0x00,0x00,
51 /* Some register defaults depend on the value of PNPCSV. */
53 {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,
55 {0x01,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00,
57 {0x1, "Parallel port",
58 {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
59 {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}},
61 {0x30,0x60,0x61,0x70,0xf0,EOT},
62 {0x01,0x03,0xf8,0x04,0x00,EOT}},
64 {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
65 {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}},
67 {0x30,0x60,0x61,0x70,EOT},
68 {0x00,0x00,0x00,0x00,EOT}},
69 {0x7, "Game port, GPIO 1",
70 {0x30,0x60,0x61,0x62,0x63,0xf0,0xf1,0xf2,EOT},
71 {0x00,0x02,0x01,0x00,0x00,0xff,0x00,0x00,EOT}},
72 {0x8, "MIDI port, GPIO 5",
73 {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3,
75 {0x00,0x03,0x30,0x00,0x00,0x09,0xff,0x00,0x00,0x00,
77 {0x9, "GPIO 2, GPIO 3, GPIO 4",
78 {0x30,0x60,0x61,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,
80 {0x00,0x00,0x00,0xff,0x00,0x00,0xff,0x00,0x00,0xff,
83 {0x30,0x70,0xe0,0xe1,0xe2,0xe5,0xe6,0xe7,
84 0xf0,0xf1,0xf3,0xf4,0xf6,0xf7,0xf9,EOT},
85 {0x00,0x00,0x00,0x00,NANA,0x00,0x00,0x00,
86 0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}},
87 {0xb, "Hardware monitor",
88 {0x30,0x60,0x61,0x70,EOT},
89 {0x00,0x00,0x00,0x00,EOT}},
91 {0x610, "W83L517D/D-F", {
93 {0x681, "W83697UF/UG", {
97 {0x828, "W83627THF/THG", { /* We assume rev is bits 3..0 of 0x21. */
99 {0x886, "W83627EHF/EF/EHG/EG", {
101 {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,
102 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT},
103 {0x88,MISC,0xff,0x00,MISC,0x00,MISC,RSVD,0x50,
104 0x04,0x00,RSVD,0x00,0x21,0x00,0x00,EOT}},
106 {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,
108 {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,
110 {0x1, "Parallel port",
111 {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
112 {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}},
114 {0x30,0x60,0x61,0x70,0xf0,EOT},
115 {0x01,0x03,0xf8,0x04,0x00,EOT}},
117 {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
118 {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}},
120 {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT},
121 {0x01,0x00,0x60,0x00,0x64,0x01,0x0c,0x83,EOT}},
122 {0x6, "Serial flash interface",
123 {0x30,0x62,0x63,EOT},
124 {0x00,0x00,0x00,EOT}},
125 {0x7, "GPIO 1, GPIO 6, game port, MIDI port",
126 {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3,
127 0xf4,0xf5,0xf6,0xf7,EOT},
128 {0x00,0x02,0x01,0x03,0x30,0x09,0xff,0x00,0x00,0x00,
129 0xff,0x00,0x00,0x00,EOT}},
131 {0x30,0xf5,0xf6,0xf7,EOT},
132 {0x00,0x00,0x00,0x00,EOT}},
133 {0x9, "GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED",
134 {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xf0,0xf1,0xf2,
135 0xf3,0xf4,0xf5,0xf6,0xf7,EOT},
136 {0x00,0xff,0x00,0x00,0xff,0x00,0x00,0xff,0x00,0x00,
137 0x00,0xff,0x00,0x00,0x00,EOT}},
139 {0x30,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,
140 0xe8,0xf2,0xf3,0xf4,0xf6,0xf7,EOT},
141 {0x00,0x00,0x01,0x00,0xff,0x08,0x00,RSVD,0x00,0x00,
142 RSVD,0x7c,0x00,0x00,0x00,0x00,EOT}},
143 {0xb, "Hardware monitor",
144 {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
145 {0x00,0x00,0x00,0x00,0xc1,0x00,EOT}},
147 {0xa23, "W83627UHG", {
149 {0x9771, "W83977F-A/G-A/AF-A/AG-A", {
151 {0x9773, "W83977TF", {
153 {0x9774, "W83977ATF", {
155 {0x52, "W83627HF/F/HG/G", {
166 static void enter_conf_mode_winbond_88(uint16_t port)
171 static void enter_conf_mode_winbond_89(uint16_t port)
176 static void enter_conf_mode_winbond_86(uint16_t port)
182 void probe_idregs_winbond_helper(const char *init, uint16_t port)
185 uint8_t devid, rev, olddevid;
187 devid = regval(port, DEVICE_ID_REG);
188 rev = regval(port, DEVICE_REV_REG);
189 olddevid = regval(port, DEVICE_ID_REG_OLD);
192 id = devid; /* ID only */
193 else if ((devid == 0x97) && ((rev & 0xf0) == 7))
194 id = (devid << 8) | rev; /* ID and rev */
196 id = (devid << 4) | ((rev & 0xf0) >> 4); /* ID and rev[3..0] */
198 if (olddevid == 0x0a || olddevid == 0x0c || olddevid == 0x0d)
199 id = olddevid & 0x0f; /* ID[3..0] */
201 if (superio_unknown(reg_table, id)) {
202 no_superio_found("Winbond", init, port);
203 exit_conf_mode_winbond_fintek_ite_8787(port);
207 if (olddevid == 0x0a || olddevid == 0x0c || olddevid == 0x0d)
208 printf("Found Winbond %s (id=0x%02x) at 0x%x\n",
209 get_superio_name(reg_table, id), olddevid, port);
211 printf("Found Winbond %s (id=0x%02x, rev=0x%02x) at 0x%x\n",
212 get_superio_name(reg_table, id), devid, rev, port);
214 /* TODO: Special notes in dump output for the MISC entries. */
215 dump_superio("Winbond", reg_table, port, id);
216 dump_superio_readable(port); /* TODO */
219 void probe_idregs_winbond(uint16_t port)
221 /* TODO: Not all init sequences are valid for all ports. */
223 enter_conf_mode_winbond_88(port);
224 probe_idregs_winbond_helper("(init=0x88) ", port);
225 exit_conf_mode_winbond_fintek_ite_8787(port);
227 enter_conf_mode_winbond_89(port);
228 probe_idregs_winbond_helper("(init=0x89) ", port);
229 exit_conf_mode_winbond_fintek_ite_8787(port);
231 enter_conf_mode_winbond_86(port);
232 probe_idregs_winbond_helper("(init=0x86,0x86) ", port);
233 exit_conf_mode_winbond_fintek_ite_8787(port);
235 enter_conf_mode_winbond_fintek_ite_8787(port);
236 probe_idregs_winbond_helper("(init=0x87,0x87) ", port);
237 exit_conf_mode_winbond_fintek_ite_8787(port);