2 * This file is part of the superiotool project.
4 * Copyright (C) 2006 Ronald Minnich <rminnich@gmail.com>
5 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include "superiotool.h"
24 #define CHIP_ID_REG 0x20 /* Super I/O ID (SID) / family */
25 #define CHIP_REV_REG 0x27 /* Super I/O revision ID (SRID) */
27 static const struct superio_registers reg_table[] = {
28 {0xd0, "PC87371", { /* From sensors-detect */
30 {0xdf, "PC97371", { /* From sensors-detect */
34 {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x2a,
35 0x2b,0x2c,0x2d,0x2e,EOT},
36 {0xe1,0x11,0x00,0x03,0x00,0x00,0x00,NANA,0x00,MISC,
37 0x00,0x00,0x00,RSVD,EOT}},
39 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT},
40 {0x00,0x03,0xf2,0x06,0x03,0x02,0x04,0x24,0x00,EOT}},
41 {0x1, "Parallel port",
42 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
43 {0x00,0x02,0x78,0x07,0x02,0x04,0x04,0xf2,EOT}},
45 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
46 {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}},
48 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
49 {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}},
50 {0x4, "System wake-up control (SWC)",
51 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT},
52 {0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}},
54 {0x30,0x70,0x71,0x74,0x75,EOT},
55 {0x00,0x0c,0x02,0x04,0x04,EOT}},
57 {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,0xf0,
59 {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x04,0x04,0x40,
62 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf2,
64 {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,0x00,0x00,
66 {0x8, "ACCESS.bus (ACB)",
67 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
68 {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,EOT}},
69 {0x9, "Fan speed control and monitor (FSCM)",
70 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
71 {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,EOT}},
72 {0xa, "Watchdog timer",
73 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
74 {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x02,EOT}},
78 {0x20,0x21,0x22,0x23,0x24,0x27,0x2e,EOT},
79 {0xe2,0x11,0xa1,0x00,MISC,NANA,RSVD,EOT}},
81 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT},
82 {0x00,0x03,0xf2,0x06,0x03,0x02,0x04,0x24,0x00,EOT}},
83 {0x1, "Parallel port",
84 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
85 {0x00,0x02,0x78,0x07,0x02,0x04,0x04,0xf2,EOT}},
87 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
88 {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}},
90 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
91 {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}},
92 {0x4, "System wake-up control (SWC)",
93 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,EOT},
94 {0x00,0x00,0x00,0x00,0x03,0x04,0x04,EOT}},
96 {0x30,0x70,0x71,0x74,0x75,EOT},
97 {0x00,0x0c,0x02,0x04,0x04,EOT}},
99 {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,
101 {0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x04,0x04,
104 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,EOT},
105 {0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,0x00,EOT}},
106 {0x8, "Fan speed control",
107 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
108 {0x00,0x00,0x00,0x00,0x00,0x04,0x04,0x00,EOT}},
112 {0xe5, "PC87365", { /* SRID[7..0] == chip revision */
119 /* SID[7..0]: family, SRID[7..5]: ID, SRID[4..0]: rev. */
123 /* SRID[7..5]: 000=PC87591E, 001=PC87591S, 100=PC87591L */
126 /* SRID[7..5] is marked as "not applicable for the PC8741x". */
132 {0x10,0x12,0x13,0x20,0x21,0x22,0x23,0x24,0x25,0x26,
133 0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT},
134 {0x00,0x00,0x00,0xf1,0x11,0x00,0x00,0x00,RSVD,0x00,
135 MISC,RSVD,0x01,0x2e,RSVD,RSVD,RSVD,RSVD,RSVD,EOT}},
137 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,0xf8,
139 {0x00,0x03,0xf2,0x06,0x03,0x02,0x04,0x24,0x00,0x24,
141 {0x1, "Parallel port",
142 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf8,EOT},
143 {0x00,0x02,0x78,0x07,0x02,0x04,0x04,0xf2,0x07,EOT}},
145 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
146 {0x00,0x02,0xf8,0x03,0x03,0x04,0x04,0x02,EOT}},
148 {0x30,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
149 {0x00,0x03,0xf8,0x04,0x03,0x04,0x04,0x02,EOT}},
150 {0x4, "System wake-up control (SWC)",
151 {0x30,0x50,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,
153 {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,
156 {0x30,0x70,0x71,0x74,0x75,EOT},
157 {0x00,0x0c,0x02,0x04,0x04,EOT}},
159 {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0x74,0x75,0xf0,
161 {0x00,0x00,0x60,0x00,0x64,0x01,0x02,0x04,0x04,0x40,
164 {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,0xf1,
166 {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x00,MISC,
167 0x00,MISC,0x01,EOT}},
168 {0x8, "Health management",
169 {0x30,0x50,0x60,0x61,0x70,0x71,0x74,0x75,0xf0,EOT},
170 {0x00,0x00,0x00,0x00,0x00,0x03,0x04,0x04,0x05,EOT}},
173 /* SRID[7..5] is marked as "not applicable for the PC87427". */
180 void probe_idregs_nsc(uint16_t port)
184 probing_for("NSC", "", port);
186 outb(CHIP_ID_REG, port);
187 if (inb(port) != CHIP_ID_REG) {
189 printf(NOTFOUND "port=0x%02x, port+1=0x%02x\n",
190 inb(port), inb(port + 1));
195 outb(CHIP_REV_REG, port);
196 if (inb(port) != CHIP_REV_REG) {
197 printf("Warning: Can't get chip revision. Setting to 0xff.\n");
203 if (superio_unknown(reg_table, id)) {
205 printf(NOTFOUND "sid=0x%02x, srid=0x%02x\n", id, rev);
209 printf("Found NSC %s (sid=0x%02x, srid=0x%02x) at 0x%x\n",
210 get_superio_name(reg_table, id), id, rev, port);
213 dump_superio("NSC", reg_table, port, id);