1 #define HAVE_STRING_SUPPORT 1
2 #define HAVE_CAST_SUPPORT 1
3 #define HAVE_STATIC_ARRAY_SUPPORT 1
4 #define HAVE_POINTER_SUPPORT 1
5 #define HAVE_CONSTANT_PROPOGATION 0
6 #define CALCULATE_DRB_REG 1
8 void outb(unsigned char value, unsigned short port)
10 __builtin_outb(value, port);
13 void outw(unsigned short value, unsigned short port)
15 __builtin_outw(value, port);
18 void outl(unsigned int value, unsigned short port)
20 __builtin_outl(value, port);
23 unsigned char inb(unsigned short port)
25 return __builtin_inb(port);
28 unsigned char inw(unsigned short port)
30 return __builtin_inw(port);
33 unsigned char inl(unsigned short port)
35 return __builtin_inl(port);
38 static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where)
40 return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3);
43 static unsigned char pcibios_read_config_byte(
44 unsigned char bus, unsigned devfn, unsigned where)
46 outl(config_cmd(bus, devfn, where), 0xCF8);
47 return inb(0xCFC + (where & 3));
50 static unsigned short pcibios_read_config_word(
51 unsigned char bus, unsigned devfn, unsigned where)
53 outl(config_cmd(bus, devfn, where), 0xCF8);
54 return inw(0xCFC + (where & 2));
57 static unsigned int pcibios_read_config_dword(
58 unsigned char bus, unsigned devfn, unsigned where)
60 outl(config_cmd(bus, devfn, where), 0xCF8);
65 static void pcibios_write_config_byte(
66 unsigned char bus, unsigned devfn, unsigned where, unsigned char value)
68 outl(config_cmd(bus, devfn, where), 0xCF8);
69 outb(value, 0xCFC + (where & 3));
72 static void pcibios_write_config_word(
73 unsigned char bus, unsigned devfn, unsigned where, unsigned short value)
75 outl(config_cmd(bus, devfn, where), 0xCF8);
76 outw(value, 0xCFC + (where & 2));
79 static void pcibios_write_config_dword(
80 unsigned char bus, unsigned devfn, unsigned where, unsigned int value)
82 outl(config_cmd(bus, devfn, where), 0xCF8);
88 /* __builtin_bsr is a exactly equivalent to the x86 machine
89 * instruction with the exception that it returns -1
90 * when the value presented to it is zero.
91 * Otherwise __builtin_bsr returns the zero based index of
92 * the highest bit set.
94 return __builtin_bsr(value);
99 #ifndef CONFIG_TTYS0_BASE
100 #define CONFIG_TTYS0_BASE 0x3f8
103 #ifndef CONFIG_TTYS0_BAUD
104 #define CONFIG_TTYS0_BAUD 115200
107 #if ((115200%CONFIG_TTYS0_BAUD) != 0)
108 #error Bad ttys0 baud rate
111 #define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
113 /* Line Control Settings */
114 #ifndef CONFIG_TTYS0_LCS
115 /* Set 8bit, 1 stop bit, no parity */
116 #define CONFIG_TTYS0_LCS 0x3
119 #define UART_LCS CONFIG_TTYS0_LCS
122 #define UART_RBR 0x00
123 #define UART_TBR 0x00
126 #define UART_IER 0x01
127 #define UART_IIR 0x02
128 #define UART_FCR 0x02
129 #define UART_LCR 0x03
130 #define UART_MCR 0x04
131 #define UART_DLL 0x00
132 #define UART_DLM 0x01
135 #define UART_LSR 0x05
136 #define UART_MSR 0x06
137 #define UART_SCR 0x07
139 int uart_can_tx_byte(void)
141 return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
144 void uart_wait_to_tx_byte(void)
146 while(!uart_can_tx_byte())
150 void uart_wait_until_sent(void)
152 while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
156 void uart_tx_byte(unsigned char data)
158 uart_wait_to_tx_byte();
159 outb(data, CONFIG_TTYS0_BASE + UART_TBR);
160 /* Make certain the data clears the fifos */
161 uart_wait_until_sent();
166 /* disable interrupts */
167 outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
169 outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
170 /* Set Baud Rate Divisor to 12 ==> 115200 Baud */
171 outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
172 outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
173 outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
174 outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
177 void __console_tx_char(unsigned char byte)
181 void __console_tx_nibble(unsigned nibble)
184 digit = nibble + '0';
188 __console_tx_char(digit);
190 void __console_tx_hex8(unsigned char byte)
192 __console_tx_nibble(byte >> 4);
193 __console_tx_nibble(byte & 0x0f);
196 void __console_tx_hex32(unsigned char value)
198 __console_tx_nibble((value >> 28) & 0x0f);
199 __console_tx_nibble((value >> 24) & 0x0f);
200 __console_tx_nibble((value >> 20) & 0x0f);
201 __console_tx_nibble((value >> 16) & 0x0f);
202 __console_tx_nibble((value >> 12) & 0x0f);
203 __console_tx_nibble((value >> 8) & 0x0f);
204 __console_tx_nibble((value >> 4) & 0x0f);
205 __console_tx_nibble(value & 0x0f);
208 #if HAVE_STRING_SUPPORT
209 void __console_tx_string(char *str)
212 while((ch = *str++) != '\0') {
213 __console_tx_char(ch);
217 void __console_tx_string(char *str)
223 void print_emerg_char(unsigned char byte) { __console_tx_char(byte); }
224 void print_emerg_hex8(unsigned char value) { __console_tx_hex8(value); }
225 void print_emerg_hex32(unsigned int value) { __console_tx_hex32(value); }
226 void print_emerg(char *str) { __console_tx_string(str); }
228 void print_alert_char(unsigned char byte) { __console_tx_char(byte); }
229 void print_alert_hex8(unsigned char value) { __console_tx_hex8(value); }
230 void print_alert_hex32(unsigned int value) { __console_tx_hex32(value); }
231 void print_alert(char *str) { __console_tx_string(str); }
233 void print_crit_char(unsigned char byte) { __console_tx_char(byte); }
234 void print_crit_hex8(unsigned char value) { __console_tx_hex8(value); }
235 void print_crit_hex32(unsigned int value) { __console_tx_hex32(value); }
236 void print_crit(char *str) { __console_tx_string(str); }
238 void print_err_char(unsigned char byte) { __console_tx_char(byte); }
239 void print_err_hex8(unsigned char value) { __console_tx_hex8(value); }
240 void print_err_hex32(unsigned int value) { __console_tx_hex32(value); }
241 void print_err(char *str) { __console_tx_string(str); }
243 void print_warning_char(unsigned char byte) { __console_tx_char(byte); }
244 void print_warning_hex8(unsigned char value) { __console_tx_hex8(value); }
245 void print_warning_hex32(unsigned int value) { __console_tx_hex32(value); }
246 void print_warning(char *str) { __console_tx_string(str); }
248 void print_notice_char(unsigned char byte) { __console_tx_char(byte); }
249 void print_notice_hex8(unsigned char value) { __console_tx_hex8(value); }
250 void print_notice_hex32(unsigned int value) { __console_tx_hex32(value); }
251 void print_notice(char *str) { __console_tx_string(str); }
253 void print_info_char(unsigned char byte) { __console_tx_char(byte); }
254 void print_info_hex8(unsigned char value) { __console_tx_hex8(value); }
255 void print_info_hex32(unsigned int value) { __console_tx_hex32(value); }
256 void print_info(char *str) { __console_tx_string(str); }
258 void print_debug_char(unsigned char byte) { __console_tx_char(byte); }
259 void print_debug_hex8(unsigned char value) { __console_tx_hex8(value); }
260 void print_debug_hex32(unsigned int value) { __console_tx_hex32(value); }
261 void print_debug(char *str) { __console_tx_string(str); }
263 void print_spew_char(unsigned char byte) { __console_tx_char(byte); }
264 void print_spew_hex8(unsigned char value) { __console_tx_hex8(value); }
265 void print_spew_hex32(unsigned int value) { __console_tx_hex32(value); }
266 void print_spew(char *str) { __console_tx_string(str); }
268 #define PIIX4_DEVFN 0x90
269 #define SMBUS_MEM_DEVICE_START 0x50
270 #define SMBUS_MEM_DEVICE_END 0x53
271 #define SMBUS_MEM_DEVICE_INC 1
275 #define PM_DEVFN (PIIX4_DEVFN+3)
277 #if HAVE_CONSTANT_PROPOGATION
278 #define SMBUS_IO_BASE 0x1000
287 static void smbus_wait_until_ready(void)
289 while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
294 static void smbus_wait_until_done(void)
298 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
299 }while((byte &1) == 1);
300 while( (byte & ~1) == 0) {
301 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
305 int smbus_read_byte(unsigned device, unsigned address)
307 unsigned char host_status_register;
311 smbus_wait_until_ready();
313 /* setup transaction */
314 /* disable interrupts */
315 outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
316 /* set the device I'm talking too */
317 outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD);
318 /* set the command/address... */
319 outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
320 /* set up for a byte data read */
321 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
323 /* clear any lingering errors, so the transaction will run */
324 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
326 /* clear the data byte...*/
327 outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
329 /* start the command */
330 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
332 /* poll for transaction completion */
333 smbus_wait_until_done();
335 host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
337 /* read results of transaction */
338 byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
341 if (host_status_register != 0x02) {
347 #else /* !HAVE_CONSTANT_PROPOGATION */
349 #define SMBUS_IO_HSTSTAT 0x1000
350 #define SMBUS_IO_HSTCTL 0x1002
351 #define SMBUS_IO_HSTCMD 0x1003
352 #define SMBUS_IO_HSTADD 0x1004
353 #define SMBUS_IO_HSTDAT0 0x1005
354 #define SMBUS_IO_HSTDAT1 0x1006
355 #define SMBUS_IO_HSTBLKDAT 0x1007
358 static void smbus_wait_until_ready(void)
360 while((inb(SMBUS_IO_HSTSTAT) & 1) == 1) {
365 static void smbus_wait_until_done(void)
369 byte = inb(SMBUS_IO_HSTSTAT);
370 }while((byte &1) == 1);
371 while( (byte & ~1) == 0) {
372 byte = inb(SMBUS_IO_HSTSTAT);
376 short smbus_read_byte(unsigned char device, unsigned char address)
378 unsigned char host_status_register;
381 smbus_wait_until_ready();
383 /* setup transaction */
384 /* disable interrupts */
385 outb(inb(SMBUS_IO_HSTCTL) & (~1), SMBUS_IO_HSTCTL);
386 /* set the device I'm talking too */
387 outb(((device & 0x7f) << 1) | 1, SMBUS_IO_HSTADD);
388 /* set the command/address... */
389 outb(address & 0xFF, SMBUS_IO_HSTCMD);
390 /* set up for a byte data read */
391 outb((inb(SMBUS_IO_HSTCTL) & 0xE3) | 8, SMBUS_IO_HSTCTL);
393 /* clear any lingering errors, so the transaction will run */
394 outb(inb(SMBUS_IO_HSTSTAT), SMBUS_IO_HSTSTAT);
396 /* clear the data byte...*/
397 outb(0, SMBUS_IO_HSTDAT0);
399 /* start the command */
400 outb((inb(SMBUS_IO_HSTCTL) | 0x40), SMBUS_IO_HSTCTL);
402 /* poll for transaction completion */
403 smbus_wait_until_done();
405 host_status_register = inb(SMBUS_IO_HSTSTAT);
407 /* read results of transaction */
408 result = inb(SMBUS_IO_HSTDAT0);
410 if (host_status_register != 0x02) {
415 #endif /* HAVE_CONSTANT_PROPOGATION */
418 #define I440GX_DEVFN ((0x00 << 3) + 0)
421 static void spd_set_drb(void)
424 * Effects: Uses serial presence detect to set the
425 * DRB registers which holds the ending memory address assigned
428 unsigned end_of_memory;
429 unsigned char device;
430 unsigned char drb_reg;
432 end_of_memory = 0; /* in multiples of 8MiB */
433 device = SMBUS_MEM_DEVICE_START;
434 #if !CALCULATE_DRB_REG
437 while (device <= SMBUS_MEM_DEVICE_END) {
438 unsigned side1_bits, side2_bits;
441 side1_bits = side2_bits = -1;
444 byte = smbus_read_byte(device, 3);
446 side1_bits += byte & 0xf;
449 byte = smbus_read_byte(device, 4);
450 side1_bits += byte & 0xf;
453 byte = smbus_read_byte(device, 17);
454 side1_bits += log2(byte);
456 /* Get the module data width and convert it to a power of two */
458 byte = smbus_read_byte(device, 6);
461 byte2 = smbus_read_byte(device, 7);
462 #if HAVE_CAST_SUPPORT
463 side1_bits += log2((((unsigned long)byte2 << 8)| byte));
465 side1_bits += log2((((byte2 << 8) | byte));
468 /* now I have the ram size in bits as a power of two (less 1) */
469 /* Make it mulitples of 8MB */
474 /* number of physical banks */
475 byte = smbus_read_byte(device, 5);
477 /* for now only handle the symmetrical case */
478 side2_bits = side1_bits;
482 /* Compute the end address for the DRB register */
483 /* Only process dimms < 2GB (2^8 * 8MB) */
484 if (side1_bits < 8) {
485 end_of_memory += (1 << side1_bits);
487 #if CALCULATE_DRB_REG
488 drb_reg = ((device - SMBUS_MEM_DEVICE_START) << 1) + 0x60;
491 #if HAVE_STRING_SUPPORT
492 print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n");
494 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, drb_reg, end_of_memory);
496 if (side2_bits < 8 ) {
497 end_of_memory += (1 << side2_bits);
499 #if HAVE_STRING_SUPPORT
500 print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n");
502 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, drb_reg +1, end_of_memory);
504 #if !CALCULATE_DRB_REG
507 device += SMBUS_MEM_DEVICE_INC;