1 #define HAVE_STRING_SUPPORT 0
2 #define HAVE_CAST_SUPPORT 1
3 #define HAVE_STATIC_ARRAY_SUPPORT 1
4 #define HAVE_POINTER_SUPPORT 1
5 #define HAVE_MACRO_ARG_SUPPORT 0
7 void outb(unsigned char value, unsigned short port)
9 __builtin_outb(value, port);
12 void outw(unsigned short value, unsigned short port)
14 __builtin_outw(value, port);
17 void outl(unsigned int value, unsigned short port)
19 __builtin_outl(value, port);
22 unsigned char inb(unsigned short port)
24 return __builtin_inb(port);
27 unsigned char inw(unsigned short port)
29 return __builtin_inw(port);
32 unsigned char inl(unsigned short port)
34 return __builtin_inl(port);
37 static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where)
39 return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3);
42 static unsigned char pcibios_read_config_byte(
43 unsigned char bus, unsigned devfn, unsigned where)
45 outl(config_cmd(bus, devfn, where), 0xCF8);
46 return inb(0xCFC + (where & 3));
49 static unsigned short pcibios_read_config_word(
50 unsigned char bus, unsigned devfn, unsigned where)
52 outl(config_cmd(bus, devfn, where), 0xCF8);
53 return inw(0xCFC + (where & 2));
56 static unsigned int pcibios_read_config_dword(
57 unsigned char bus, unsigned devfn, unsigned where)
59 outl(config_cmd(bus, devfn, where), 0xCF8);
64 static void pcibios_write_config_byte(
65 unsigned char bus, unsigned devfn, unsigned where, unsigned char value)
67 outl(config_cmd(bus, devfn, where), 0xCF8);
68 outb(value, 0xCFC + (where & 3));
71 static void pcibios_write_config_word(
72 unsigned char bus, unsigned devfn, unsigned where, unsigned short value)
74 outl(config_cmd(bus, devfn, where), 0xCF8);
75 outw(value, 0xCFC + (where & 2));
78 static void pcibios_write_config_dword(
79 unsigned char bus, unsigned devfn, unsigned where, unsigned int value)
81 outl(config_cmd(bus, devfn, where), 0xCF8);
86 #ifndef CONFIG_TTYS0_BASE
87 #define CONFIG_TTYS0_BASE 0x3f8
90 #ifndef CONFIG_TTYS0_BAUD
91 #define CONFIG_TTYS0_BAUD 115200
94 #if ((115200%CONFIG_TTYS0_BAUD) != 0)
95 #error Bad ttys0 baud rate
98 #define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
100 /* Line Control Settings */
101 #ifndef CONFIG_TTYS0_LCS
102 /* Set 8bit, 1 stop bit, no parity */
103 #define CONFIG_TTYS0_LCS 0x3
106 #define UART_LCS CONFIG_TTYS0_LCS
109 #define UART_RBR 0x00
110 #define UART_TBR 0x00
113 #define UART_IER 0x01
114 #define UART_IIR 0x02
115 #define UART_FCR 0x02
116 #define UART_LCR 0x03
117 #define UART_MCR 0x04
118 #define UART_DLL 0x00
119 #define UART_DLM 0x01
122 #define UART_LSR 0x05
123 #define UART_MSR 0x06
124 #define UART_SCR 0x07
126 int uart_can_tx_byte(void)
128 return inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x20;
131 void uart_wait_to_tx_byte(void)
133 while(!uart_can_tx_byte())
137 void uart_wait_until_sent(void)
139 while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40))
143 void uart_tx_byte(unsigned char data)
145 uart_wait_to_tx_byte();
146 outb(data, CONFIG_TTYS0_BASE + UART_TBR);
147 /* Make certain the data clears the fifos */
148 uart_wait_until_sent();
153 /* disable interrupts */
154 outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
156 outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
157 /* Set Baud Rate Divisor to 12 ==> 115200 Baud */
158 outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
159 outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
160 outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
161 outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
164 void __console_tx_char(unsigned char byte)
168 void __console_tx_nibble(unsigned nibble)
171 digit = nibble + '0';
175 __console_tx_char(digit);
177 void __console_tx_hex8(unsigned char byte)
179 __console_tx_nibble(byte >> 4);
180 __console_tx_nibble(byte & 0x0f);
183 void __console_tx_hex32(unsigned char value)
185 __console_tx_nibble((value >> 28) & 0x0f);
186 __console_tx_nibble((value >> 24) & 0x0f);
187 __console_tx_nibble((value >> 20) & 0x0f);
188 __console_tx_nibble((value >> 16) & 0x0f);
189 __console_tx_nibble((value >> 12) & 0x0f);
190 __console_tx_nibble((value >> 8) & 0x0f);
191 __console_tx_nibble((value >> 4) & 0x0f);
192 __console_tx_nibble(value & 0x0f);
195 #if HAVE_STRING_SUPPORT
196 void __console_tx_string(char *str)
199 while((ch = *str++) != '\0') {
200 __console_tx_char(ch);
204 void __console_tx_string(char *str)
210 void print_emerg_char(unsigned char byte) { __console_tx_char(byte); }
211 void print_emerg_hex8(unsigned char value) { __console_tx_hex8(value); }
212 void print_emerg_hex32(unsigned int value) { __console_tx_hex32(value); }
213 void print_emerg(char *str) { __console_tx_string(str); }
215 void print_alert_char(unsigned char byte) { __console_tx_char(byte); }
216 void print_alert_hex8(unsigned char value) { __console_tx_hex8(value); }
217 void print_alert_hex32(unsigned int value) { __console_tx_hex32(value); }
218 void print_alert(char *str) { __console_tx_string(str); }
220 void print_crit_char(unsigned char byte) { __console_tx_char(byte); }
221 void print_crit_hex8(unsigned char value) { __console_tx_hex8(value); }
222 void print_crit_hex32(unsigned int value) { __console_tx_hex32(value); }
223 void print_crit(char *str) { __console_tx_string(str); }
225 void print_err_char(unsigned char byte) { __console_tx_char(byte); }
226 void print_err_hex8(unsigned char value) { __console_tx_hex8(value); }
227 void print_err_hex32(unsigned int value) { __console_tx_hex32(value); }
228 void print_err(char *str) { __console_tx_string(str); }
230 void print_warning_char(unsigned char byte) { __console_tx_char(byte); }
231 void print_warning_hex8(unsigned char value) { __console_tx_hex8(value); }
232 void print_warning_hex32(unsigned int value) { __console_tx_hex32(value); }
233 void print_warning(char *str) { __console_tx_string(str); }
235 void print_notice_char(unsigned char byte) { __console_tx_char(byte); }
236 void print_notice_hex8(unsigned char value) { __console_tx_hex8(value); }
237 void print_notice_hex32(unsigned int value) { __console_tx_hex32(value); }
238 void print_notice(char *str) { __console_tx_string(str); }
240 void print_info_char(unsigned char byte) { __console_tx_char(byte); }
241 void print_info_hex8(unsigned char value) { __console_tx_hex8(value); }
242 void print_info_hex32(unsigned int value) { __console_tx_hex32(value); }
243 void print_info(char *str) { __console_tx_string(str); }
245 void print_debug_char(unsigned char byte) { __console_tx_char(byte); }
246 void print_debug_hex8(unsigned char value) { __console_tx_hex8(value); }
247 void print_debug_hex32(unsigned int value) { __console_tx_hex32(value); }
248 void print_debug(char *str) { __console_tx_string(str); }
250 void print_spew_char(unsigned char byte) { __console_tx_char(byte); }
251 void print_spew_hex8(unsigned char value) { __console_tx_hex8(value); }
252 void print_spew_hex32(unsigned int value) { __console_tx_hex32(value); }
253 void print_spew(char *str) { __console_tx_string(str); }
255 #define PIIX4_DEVFN 0x90
256 #define SMBUS_MEM_DEVICE_START 0x50
257 #define SMBUS_MEM_DEVICE_END 0x53
258 #define SMBUS_MEM_DEVICE_INC 1
262 #define PM_DEVFN (PIIX4_DEVFN+3)
264 #define SMBUS_IO_BASE 0x1000
273 void smbus_enable(void)
276 pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x90, SMBUS_IO_BASE | 1);
278 pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0xd2, (0x4 << 1) | 1);
280 pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1);
283 void smbus_setup(void)
285 outb(0, SMBUS_IO_BASE + SMBHSTSTAT);
288 static void smbus_wait_until_ready(void)
290 while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
295 static void smbus_wait_until_done(void)
299 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
300 }while((byte &1) == 1);
301 while( (byte & ~1) == 0) {
302 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
306 int smbus_read_byte(unsigned device, unsigned address)
308 unsigned char host_status_register;
312 smbus_wait_until_ready();
314 /* setup transaction */
315 /* disable interrupts */
316 outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
317 /* set the device I'm talking too */
318 outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD);
319 /* set the command/address... */
320 outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
321 /* set up for a byte data read */
322 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
324 /* clear any lingering errors, so the transaction will run */
325 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
327 /* clear the data byte...*/
328 outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
330 /* start the command */
331 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
333 /* poll for transaction completion */
334 smbus_wait_until_done();
336 host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
338 /* read results of transaction */
339 byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
342 if (host_status_register != 0x02) {
349 #define I440GX_DEVFN ((0x00 << 3) + 0)
353 #define CAS_LATENCY 3
356 #if (CAS_LATENCY == 2)
362 #define CAS_MODE 0x2a
370 #if (CAS_LATENCY == 3)
376 #define CAS_MODE 0x3a
384 #error "Nothing defined"
387 /* Default values for config registers */
389 static void set_nbxcfg(void)
391 /* NBXCFG 0x50 - 0x53 */
400 * SDRAM Row without ECC:
409 * Host Bus Fast Data Ready Enable == 0 Disabled
410 * IDSEL_REDIRECT == 0 (430TX compatibility disable?)
411 * WSC# Hanshake Disable == 0 enable (Use External IOAPIC)
412 * Host/DRAM Frequence == 00 100Mhz
413 * AGP to PCI Access Enable == 0 Disable
414 * PCI Agent to Aperture Access Disable == 0 Enable (Ignored)
415 * Aperture Access Global Enable == 0 Disable
416 * DRAM Data Integrity Mode == 11 (Error Checking/Correction)
417 * ECC Diagnostic Mode Enable == 0 Not Enabled
418 * MDA present == 0 Not Present
419 * USWC Write Post During During I/O Bridge Access Enable == 1 Enabled
420 * In Order Queue Depth (IQD) (RO) == ??
422 pcibios_write_config_dword(I440GX_BUS, I440GX_DEVFN, 0x50, 0xff00000c);
425 static void set_dramc(void)
429 * Not registered SDRAM
432 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, 0x8);
435 static void set_pam(void)
437 /* PAM - Programmable Attribute Map Registers */
438 /* Ideally we want to enable all of these as DRAM and teach
439 * linux it is o.k. to use them...
441 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x59, 0x00);
442 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5a, 0x00);
443 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5b, 0x00);
444 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5d, 0x00);
445 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5e, 0x00);
446 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x5f, 0x00);
449 static void set_drb(void)
451 /* DRB - DRAM Row Boundary Registers */
452 /* Conservative setting 8MB of ram on first DIMM... */
453 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x60, 0x01);
454 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x61, 0x01);
455 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x62, 0x01);
456 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x63, 0x01);
457 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x64, 0x01);
458 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x65, 0x01);
459 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x66, 0x01);
460 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x67, 0x01);
463 static void set_fdhc(void)
465 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x68, 0x00);
467 static void set_mbsc(void)
469 /* MBSC - Memory Buffer Strength Control */
483 * MAA[14:0]#, WEA#, SRASA#, SCASA# Buffer Strengths == 3x
484 * MAB[14,13,10,12:11,9:0]#, WEB#, SRASB#, SCASB# Buffer Strengths == 3x
485 * MD[63:0]# Buffer Strength Control 2 == 3x
486 * MD[63:0]# Buffer Strength Control 1 == 3x
487 * MECC[7:0] Buffer Strength Control 2 == 3x
488 * MECC[7:0] Buffer Strength Control 1 == 3x
489 * CSB7# Buffer Strength == 3x
490 * CSA7# Buffer Strength == 3x
491 * CSB6# Buffer Strength == 3x
492 * CSA6# Buffer Strength == 3x
493 * CSA5#/CSB5# Buffer Strength == 2x
494 * CSA4#/CSB4# Buffer Strength == 2x
495 * CSA3#/CSB3# Buffer Strength == 2x
496 * CSA2#/CSB2# Buffer Strength == 2x
497 * CSA1#/CSB1# Buffer Strength == 2x
498 * CSA0#/CSB0# Buffer Strength == 2x
499 * DQMA5 Buffer Strength == 2x
500 * DQMA1 Buffer Strength == 3x
501 * DQMB5 Buffer Strength == 2x
502 * DQMB1 Buffer Strength == 2x
503 * DQMA[7:6,4:2,0] Buffer Strength == 3x
504 * GCKE Buffer Strength == 1x
505 * FENA Buffer Strength == 3x
507 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x69, 0xB3);
508 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6a, 0xee);
509 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6b, 0xff);
510 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6c, 0xff);
511 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6d, 0xff);
512 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x6e, 0x03);
515 static void set_smram(void)
520 * SMM Compatible base segment == 010 (Hardcoded value)
524 static void set_esramc(void)
529 static void set_rps(void)
531 /* RPS - Row Page Size Register */
546 pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x74, 0x5555);
549 static void set_sdramc(void)
551 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76, CAS_NB);
554 static void set_pgpol(void)
556 /* PGPOL - Paging Policy Register */
570 * Dram Idle Timer (DIT) == 32 clocks
572 pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x78, 0xff07);
575 static void set_mbfs(void)
577 /* MBFS - Memory Buffer Frequencey Select Register */
585 * MAA[14:0], WEA#, SRASA#, SCASA# == 100Mhz Buffers Enabled
586 * MAB[14,13,10,12:11,9:0], WEB#, SRASB#, SCASB# == 100Mhz Buffers Enabled
587 * MD[63:0] Control 2 == 100 Mhz Buffer Enable
588 * MD[63:0] Control 1 == 100 Mhz B
589 * MECC[7:0] Control 2 == 100 Mhz B
592 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xca, 0xff);
593 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcb, 0xff);
594 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcc, 0x7f);
597 static void set_dwtc(void)
599 /* DWTC - DRAM Write Thermal Throttle Control */
600 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe0, 0xb4);
601 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe1, 0xbe);
602 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe2, 0xff);
603 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe3, 0xd7);
604 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe4, 0x97);
605 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe5, 0x3e);
606 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe6, 0x00);
607 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe7, 0x80);
610 static void set_drtc(void)
612 /* DRTC - DRAM Read Thermal Throttle Control */
613 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe8, 0x2c);
614 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xe9, 0xd3);
615 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xea, 0xf7);
616 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xeb, 0xcf);
617 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xec, 0x9d);
618 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xed, 0x3e);
619 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xee, 0x00);
620 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xef, 0x00);
623 static void set_pmcr(void)
625 /* PMCR -- BIOS sets 0x90 into it.
627 * we have never used it. So why did this ever work?
629 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x7a, 0x90);
632 void sdram_set_registers(void)
653 /* __builtin_bsr is a exactly equivalent to the x86 machine
654 * instruction with the exception that it returns -1
655 * when the value presented to it is zero.
656 * Otherwise __builtin_bsr returns the zero based index of
657 * the highest bit set.
659 return __builtin_bsr(value);
663 static void spd_set_drb(void)
666 * Effects: Uses serial presence detect to set the
667 * DRB registers which holds the ending memory address assigned
670 unsigned end_of_memory;
674 end_of_memory = 0; /* in multiples of 8MiB */
675 device = SMBUS_MEM_DEVICE_START;
677 while (device <= SMBUS_MEM_DEVICE_END) {
678 unsigned side1_bits, side2_bits;
681 side1_bits = side2_bits = -1;
684 byte = smbus_read_byte(device, 3);
686 side1_bits += byte & 0xf;
689 byte = smbus_read_byte(device, 4);
690 side1_bits += byte & 0xf;
693 byte = smbus_read_byte(device, 17);
694 side1_bits += log2(byte);
696 /* Get the moduel data width and convert it to a power of two */
698 byte = smbus_read_byte(device, 6);
701 byte2 = smbus_read_byte(device, 7);
702 #if HAVE_CAST_SUPPORT
703 side1_bits += log2((((unsigned long)byte2 << 8)| byte));
705 side1_bits += log2((byte2 << 8) | byte);
708 /* now I have the ram size in bits as a power of two (less 1) */
709 /* Make it mulitples of 8MB */
714 /* number of physical banks */
715 byte = smbus_read_byte(device, 5);
717 /* for now only handle the symmetrical case */
718 side2_bits = side1_bits;
722 /* Compute the end address for the DRB register */
723 /* Only process dimms < 2GB (2^8 * 8MB) */
724 if (side1_bits < 8) {
725 end_of_memory += (1 << side1_bits);
727 #if HAVE_STRING_SUPPORT
728 print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n");
730 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, drb_reg, end_of_memory);
732 if (side2_bits < 8 ) {
733 end_of_memory += (1 << side2_bits);
735 #if HAVE_STRING_SUPPORT
736 print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n");
738 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, drb_reg +1, end_of_memory);
741 device += SMBUS_MEM_DEVICE_INC;
745 void sdram_no_memory(void)
747 #if HAVE_STRING_SUPPORT
748 print_err("No memory!!\n");
753 static void spd_set_dramc(void)
756 * Effects: Uses serial presence detect to set the
757 * DRAMC register, which records if ram is registerd or not,
758 * and controls the refresh rate.
759 * The refresh rate is not set here, as memory refresh
760 * cannot be enbaled until after memory is initialized.
761 * see spd_enable_refresh.
763 /* auto detect if ram is registered or not. */
764 /* The DRAMC register also contorls the refresh rate but we can't
765 * set that here because we must leave refresh disabled.
766 * see: spd_enable_refresh
768 /* Find the first dimm and assume the rest are the same */
769 /* FIXME Check for illegal/unsupported ram configurations and abort */
774 device = SMBUS_MEM_DEVICE_START;
776 while ((byte < 0) && (device <= SMBUS_MEM_DEVICE_END)) {
777 byte = smbus_read_byte(device, 21);
778 device += SMBUS_MEM_DEVICE_INC;
781 /* We couldn't find anything we must have no memory */
785 if ((byte & 0x12) != 0) {
786 /* this is a registered part.
787 * observation: for register parts, BIOS zeros (!)
788 * registers CA-CC. This has an undocumented meaning.
790 /* But it does make sense the oppisite of registered
791 * sdram is buffered and 0xca - 0xcc control the buffers.
792 * Clearing them aparently disables them.
794 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xca, 0);
795 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcb, 0);
796 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0xcc, 0);
799 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, dramc);
802 static void spd_enable_refresh(void)
805 * Effects: Uses serial presence detect to set the
806 * refresh rate in the DRAMC register.
807 * see spd_set_dramc for the other values.
808 * FIXME: Check for illegal/unsupported ram configurations and abort
810 #if HAVE_STATIC_ARRAY_SUPPORT
811 static const unsigned char refresh_rates[] = {
812 0x01, /* Normal 15.625 us -> 15.6 us */
813 0x05, /* Reduced(.25X) 3.9 us -> 7.8 us */
814 0x05, /* Reduced(.5X) 7.8 us -> 7.8 us */
815 0x02, /* Extended(2x) 31.3 us -> 31.2 us */
816 0x03, /* Extended(4x) 62.5 us -> 62.4 us */
817 0x04, /* Extended(8x) 125 us -> 124.8 us */
820 /* Find the first dimm and assume the rest are the same */
824 unsigned refresh_rate;
827 device = SMBUS_MEM_DEVICE_START;
828 while ((byte < 0) && (device <= SMBUS_MEM_DEVICE_END)) {
829 byte = smbus_read_byte(device, 12);
830 device += SMBUS_MEM_DEVICE_INC;
833 /* We couldn't find anything we must have no memory */
837 /* Default refresh rate be conservative */
839 /* see if the ram refresh is a supported one */
841 #if HAVE_STATIC_ARRAY_SUPPORT
842 refresh_rate = refresh_rates[byte];
845 byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57);
847 byte |= refresh_rate;
848 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, byte);
851 static void spd_set_sdramc(void)
856 static void spd_set_rps(void)
859 * Effects: Uses serial presence detect to set the row size
861 * FIXME: Check for illegal/unsupported ram configurations and abort
863 /* The RPS register holds the size of a ``page'' of DRAM on each DIMM */
868 /* default all page sizes to 2KB */
871 device = SMBUS_MEM_DEVICE_START;
872 for(; device <= SMBUS_MEM_DEVICE_END; index += 4, device += SMBUS_MEM_DEVICE_INC) {
877 byte = smbus_read_byte(device, 3);
878 if (byte < 0) continue;
880 /* I now have the row page size as a power of 2 */
881 page_size = byte & 0xf;
882 /* make it in multiples of 2Kb */
885 if (page_size <= 0) continue;
887 /* FIXME: do something with page sizes greather than 8KB!! */
888 page_sizes |= (page_size << index);
891 byte = smbus_read_byte(device, 5);
892 if (byte <= 1) continue;
894 /* For now only handle the symmetrical case */
895 page_sizes |= (page_size << (index +2));
897 /* next block is for Ron's attempt to get registered to work. */
898 /* we have just verified that we have to have this code. It appears that
899 * the registered SDRAMs do indeed set the RPS wrong. sheesh.
901 /* at this point, page_sizes holds the RPS for all ram.
902 * we have verified that for registered DRAM the values are
903 * 1/2 the size they should be. So we test for registered
904 * and then double the sizes if needed.
907 dramc = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57);
911 /* BIOS makes weird page size for registered! */
912 /* what we have found is you need to set the EVEN banks to
913 * twice the size. Fortunately there is a very easy way to
914 * do this. First, read the WORD value of register 0x74.
916 page_sizes += 0x1111;
919 pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x74, page_sizes);
922 static void spd_set_pgpol(void)
925 * Effects: Uses serial presence detect to set the number of banks
927 * FIXME: Check for illegal/unsupported ram configurations and abort
929 /* The PGPOL register stores the number of logical banks per DIMM,
930 * and number of clocks the DRAM controller waits in the idle
937 /* default all bank counts 2 */
940 device = SMBUS_MEM_DEVICE_START;
941 for(; device <= SMBUS_MEM_DEVICE_END;
942 bank += 2, device += SMBUS_MEM_DEVICE_INC) {
946 byte = smbus_read_byte(device, 17);
947 if (byte < 0) continue;
948 if (byte < 4) continue;
949 bank_sizes |= (1 << bank);
952 /* Number of physical banks */
953 byte = smbus_read_byte(device, 5);
954 if (byte <= 1) continue;
955 /* for now only handle the symmetrical case */
956 bank_sizes |= (1 << (bank +1));
958 reg = bank_sizes << 8;
959 reg |= 0x7; /* 32 clocks idle time */
960 pcibios_write_config_word(I440GX_BUS, I440GX_DEVFN, 0x78, reg);
963 static void spd_set_nbxcfg(void)
966 * Effects: Uses serial presence detect to set the
967 * ECC support flags in the NBXCFG register
968 * FIXME: Check for illegal/unsupported ram configurations and abort
974 /* Say all dimms have no ECC support */
978 device = SMBUS_MEM_DEVICE_START;
979 for(; device <= SMBUS_MEM_DEVICE_END; index += 2, device += SMBUS_MEM_DEVICE_INC) {
982 byte = smbus_read_byte(device, 11);
983 if (byte < 0) continue;
985 byte = 0; /* Disable ECC */
987 /* 0 == None, 1 == Parity, 2 == ECC */
988 if (byte != 2) continue;
992 /* number of physical banks */
993 byte = smbus_read_byte(device, 5);
994 if (byte <= 1) continue;
995 /* There is only the symmetrical case */
996 reg ^= (1 << (index +1));
998 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x53, reg);
999 /* Now see if reg is 0xff. If it is we are done. If not,
1000 * we need to set 0x18 into regster 0x50.l
1001 * we will do this in two steps, first or in 0x80 to 0x50.b,
1002 * then or in 0x1 to 0x51.b
1004 #if HAVE_STRING_SUPPORT
1005 print_debug("spd_set_nbxcfg reg="); print_debug_hex8(reg); print_debug("\n");
1009 byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x50);
1011 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x50, byte);
1012 byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x51);
1014 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x51, byte);
1016 * We should be setting bit 2 in register 76 and we're not
1017 * technically we should see if CL=2 for the ram,
1018 * but registered is so screwed up that it's kind of a lost
1021 byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76);
1023 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76, byte);
1024 #if HAVE_STRING_SUPPORT
1025 print_debug("spd_set_nbxcfg 0x76.b="); print_debug_hex8(byte); print_debug("\n");
1030 void sdram_set_spd_registers(void)
1040 void sdram_first_normal_reference(void)
1045 void sdram_special_finishup(void)
1050 static void set_ram_command(unsigned command)
1054 byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76);
1056 byte |= (command << 5);
1057 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76, byte);
1058 #if HAVE_STRING_SUPPORT
1059 print_debug("set_ram_command 0x76.b="); print_debug_hex8(byte); print_debug("\n");
1063 #define RAM_COMMAND_NONE 0x0
1064 #define RAM_COMMAND_NOOP 0x1
1065 #define RAM_COMMAND_PRECHARGE 0x2
1066 #define RAM_COMMAND_MRS 0x3
1067 #define RAM_COMMAND_CBR 0x4
1069 void sdram_set_command_none(void)
1071 set_ram_command(RAM_COMMAND_NONE);
1073 void sdram_set_command_noop(void)
1075 set_ram_command(RAM_COMMAND_NOOP);
1077 void sdram_set_command_precharge(void)
1079 set_ram_command(RAM_COMMAND_PRECHARGE);
1082 static unsigned long dimm_base(int n)
1085 unsigned long result;
1090 byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x60 + (n - 1));
1096 static void dimms_read(unsigned long offset)
1099 for(i = 0; i < 8; i++) {
1100 unsigned long dummy;
1102 unsigned long next_base;
1104 next_base = dimm_base(i +1);
1105 addr = dimm_base(i);
1106 if (addr == next_base) {
1110 #if HAVE_STRING_SUPPORT
1111 print_debug("Reading ");
1112 print_debug_hex32(addr);
1115 #if HAVE_POINTER_SUPPORT
1116 #if HAVE_MACRO_ARG_SUPPORT
1117 dummy = RAM(unsigned long, addr);
1119 dummy = *((volatile unsigned long *)(addr));
1122 #if HAVE_STRING_SUPPORT
1123 print_debug("Reading ");
1124 print_debug_hex32(addr ^ 0xddf8);
1127 #if HAVE_POINTER_SUPPORT
1128 #if HAVE_MACRO_ARG_SUPPORT
1129 dummy = RAM(unsigned long, addr ^ 0xdff8);
1131 dummy = *((volatile unsigned long *)(addr ^ 0xdff8));
1134 #if HAVE_STRING_SUPPORT
1135 print_debug("Read ");
1136 print_debug_hex32(addr);
1137 print_debug_hex32(addr ^ 0xddf8);
1143 void sdram_set_command_cbr(void)
1145 set_ram_command(RAM_COMMAND_CBR);
1148 void sdram_assert_command(void)
1153 void sdram_set_mode_register(void)
1157 set_ram_command(RAM_COMMAND_MRS);
1158 byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76);
1159 cas_mode = byte & 0x4;
1164 dimms_read(cas_mode);
1167 void sdram_enable_refresh(void)
1169 spd_enable_refresh();
1173 unsigned long sdram_get_ecc_size_bytes(void)
1177 /* FIXME handle the no ram case. */
1178 /* Read the RAM SIZE */
1179 byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x67);
1180 /* Convert it to bytes */
1189 /* Dummy udelay code acting as a place holder... */
1190 void udelay(int count)
1196 void sdram_enable(void)
1198 #if HAVE_STRING_SUPPORT
1199 print_debug("Ram Enable 1\n");
1203 sdram_set_command_noop();
1205 sdram_assert_command();
1208 sdram_set_command_precharge();
1209 sdram_assert_command();
1211 /* wait until the all banks idle state... */
1212 #if HAVE_STRING_SUPPORT
1213 print_debug("Ram Enable 2\n");
1216 /* Now we need 8 AUTO REFRESH / CBR cycles to be performed */
1218 sdram_set_command_cbr();
1219 sdram_assert_command();
1220 sdram_assert_command();
1221 sdram_assert_command();
1222 sdram_assert_command();
1223 sdram_assert_command();
1224 sdram_assert_command();
1225 sdram_assert_command();
1226 sdram_assert_command();
1228 #if HAVE_STRING_SUPPORT
1229 print_debug("Ram Enable 3\n");
1232 /* mode register set */
1233 sdram_set_mode_register();
1235 * MAx[2:0 ] 010 == burst mode of 4
1236 * MAx[3:3 ] 1 == interleave wrap type
1237 * MAx[4:4 ] == CAS# latency bit
1242 #if HAVE_STRING_SUPPORT
1243 print_debug("Ram Enable 4\n");
1246 /* normal operation */
1247 sdram_set_command_none();
1249 #if HAVE_STRING_SUPPORT
1250 print_debug("Ram Enable 5\n");
1255 void sdram_initialize(void)
1257 #if HAVE_STRING_SUPPORT
1258 print_debug("Ram1\n");
1260 /* Set the registers we can set once to reasonable values */
1261 sdram_set_registers();
1263 #if HAVE_STRING_SUPPORT
1264 print_debug("Ram2\n");
1266 /* Now setup those things we can auto detect */
1267 sdram_set_spd_registers();
1269 #if HAVE_STRING_SUPPORT
1270 print_debug("Ram3\n");
1272 /* Now that everything is setup enable the SDRAM.
1273 * Some chipsets do the work for use while on others
1274 * we need to it by hand.
1278 #if HAVE_STRING_SUPPORT
1279 print_debug("Ram4\n");
1281 sdram_first_normal_reference();
1283 #if HAVE_STRING_SUPPORT
1284 print_debug("Ram5\n");
1286 sdram_enable_refresh();
1287 sdram_special_finishup();
1289 #if HAVE_STRING_SUPPORT
1290 print_debug("Ram6\n");