2 * This file is part of msrtool.
4 * Copyright (c) 2008 Peter Stuge <peter@stuge.se>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 int geodelx_probe(const struct targetdef *target) {
23 struct cpuid_t *id = cpuid();
24 return 5 == id->family && 10 == id->model;
27 const struct msrdef geodelx_msrs[] = {
28 { 0x20000018, MSRTYPE_RDWR, MSR2(0x10071007, 0x40), "MC_CF07_DATA", "Refresh and SDRAM Program", {
29 { 63, 4, "D1_SZ", "DIMM1 Size", PRESENT_BIN, {
30 { MSR1(0), "Reserved" },
35 { MSR1(5), "128 MB" },
36 { MSR1(6), "256 MB" },
37 { MSR1(7), "512 MB" },
39 { MSR1(9), "Reserved" },
40 { MSR1(10), "Reserved" },
41 { MSR1(11), "Reserved" },
42 { MSR1(12), "Reserved" },
43 { MSR1(13), "Reserved" },
44 { MSR1(14), "Reserved" },
45 { MSR1(15), "Reserved" },
49 { 56, 1, "D1_MB", "DIMM1 Module Banks", PRESENT_BIN, {
50 { MSR1(0), "1 Module bank" },
51 { MSR1(1), "2 Module banks" },
55 { 52, 1, "D1_CB", "DIMM1 Component Banks", PRESENT_BIN, {
56 { MSR1(0), "2 Component banks" },
57 { MSR1(1), "4 Component banks" },
61 { 50, 3, "D1_PSZ", "DIMM1 Page Size", PRESENT_BIN, {
68 { MSR1(6), "Reserved" },
69 { MSR1(7), "DIMM1 Not Installed" },
72 { 47, 4, "D0_SZ", "DIMM0 Size", PRESENT_BIN, {
73 { MSR1(0), "Reserved" },
78 { MSR1(5), "128 MB" },
79 { MSR1(6), "256 MB" },
80 { MSR1(7), "512 MB" },
82 { MSR1(9), "Reserved" },
83 { MSR1(10), "Reserved" },
84 { MSR1(11), "Reserved" },
85 { MSR1(12), "Reserved" },
86 { MSR1(13), "Reserved" },
87 { MSR1(14), "Reserved" },
88 { MSR1(15), "Reserved" },
92 { 40, 1, "D0_MB", "DIMM0 Module Banks", PRESENT_BIN, {
93 { MSR1(0), "1 Module bank" },
94 { MSR1(1), "2 Module banks" },
98 { 36, 1, "D0_CB", "DIMM0 Component Banks", PRESENT_BIN, {
99 { MSR1(0), "2 Component banks" },
100 { MSR1(1), "4 Component banks" },
104 { 34, 3, "D0_PSZ", "DIMM0 Page Size", PRESENT_BIN, {
109 { MSR1(4), "16 KB" },
110 { MSR1(5), "32 KB" },
111 { MSR1(6), "Reserved" },
112 { MSR1(7), "DIMM0 Not Installed" },
116 { 29, 2, "MSR_BA", "Mode Register Set Bank Address", PRESENT_BIN, {
117 { MSR1(0), "Program the DIMM Mode Register" },
118 { MSR1(1), "Program the DIMM Extended Mode Register" },
119 { MSR1(2), "Reserved" },
120 { MSR1(3), "Reserved" },
123 { 27, 1, "RST_DLL", "Mode Register Reset DLL", PRESENT_BIN, {
124 { MSR1(0), "Do not reset DLL" },
125 { MSR1(1), "Reset DLL" },
128 { 26, 1, "EMR_QFC", "Extended Mode Register FET Control", PRESENT_BIN, {
129 { MSR1(0), "Enable" },
130 { MSR1(1), "Disable" },
133 { 25, 1, "EMR_DRV", "Extended Mode Register Drive Strength Control", PRESENT_BIN, {
134 { MSR1(0), "Normal" },
135 { MSR1(1), "Reduced" },
138 { 24, 1, "EMR_DLL", "Extended Mode Register DLL", PRESENT_BIN, {
139 { MSR1(0), "Enable" },
140 { MSR1(1), "Disable" },
143 { 23, 16, "REF_INT", "Refresh Interval", PRESENT_DEC, NOBITS },
144 { 7, 4, "REF_STAG", "Refresh Staggering", PRESENT_DEC, NOBITS },
145 { 3, 1, "REF_TST", "Test Refresh", PRESENT_BIN, NOBITS },
147 { 1, 1, "SOFT_RST", "Software Reset", PRESENT_BIN, NOBITS },
148 { 0, 1, "PROG_DRAM", "Program Mode Register in SDRAM", PRESENT_BIN, NOBITS },
151 { 0x20000019, MSRTYPE_RDWR, MSR2(0x18000008, 0x287337a3), "MC_CF8F_DATA", "Timing and Mode Program", {
152 { 63, 8, "STALE_REQ", "GLIU Max Stale Request Count", PRESENT_DEC, NOBITS },
154 { 52, 2, "XOR_BIT_SEL", "XOR Bit Select", PRESENT_BIN, {
155 { MSR1(0), "ADDR[18]" },
156 { MSR1(1), "ADDR[19]" },
157 { MSR1(2), "ADDR[20]" },
158 { MSR1(3), "ADDR[21]" },
161 { 50, 1, "XOR_MB0", "XOR MB0 Enable", PRESENT_BIN, {
162 { MSR1(0), "Disabled" },
163 { MSR1(1), "Enabled" },
166 { 49, 1, "XOR_BA1", "XOR BA1 Enable", PRESENT_BIN, {
167 { MSR1(0), "Disabled" },
168 { MSR1(1), "Enabled" },
171 { 48, 1, "XOR_BA0", "XOR BA0 Enable", PRESENT_BIN, {
172 { MSR1(0), "Disabled" },
173 { MSR1(1), "Enabled" },
177 { 41, 1, "TRUNC_DIS", "Burst Truncate Disable", PRESENT_BIN, {
178 { MSR1(0), "Bursts Enabled" },
179 { MSR1(1), "Bursts Disabled" },
182 { 40, 1, "REORDER_DIS", "Reorder Disable", PRESENT_BIN, {
183 { MSR1(0), "Reordering Enabled" },
184 { MSR1(1), "Reordering Disabled" },
188 { 33, 1, "HOI_LOI", "High / Low Order Interleave Select", PRESENT_BIN, {
189 { MSR1(0), "Low Order Interleave" },
190 { MSR1(1), "High Order Interleave" },
194 { 31, 1, "THZ_DLY", "tHZ Delay", PRESENT_BIN, NOBITS },
195 { 30, 3, "CAS_LAT", "Read CAS Latency", PRESENT_BIN, {
196 { MSR1(0), "Reserved" },
197 { MSR1(1), "Reserved" },
206 { 27, 4, "ACT2ACTREF", "ACT to ACT/REF Period. tRC", PRESENT_DEC, NOBITS },
207 { 23, 4, "ACT2PRE", "ACT to PRE Period. tRAS", PRESENT_DEC, NOBITS },
209 { 18, 3, "PRE2ACT", "PRE to ACT Period. tRP", PRESENT_DEC, NOBITS },
211 { 14, 3, "ACT2CMD", "Delay Time from ACT to Read/Write. tRCD", PRESENT_DEC, NOBITS },
212 { 11, 4, "ACT2ACT", "ACT(0) to ACT(1) Period. tRRD", PRESENT_DEC, NOBITS },
213 { 7, 2, "DPLWR", "Data-in to PRE Period. tDPLW", PRESENT_DEC, {
214 { MSR1(0), "Invalid value" },
220 { 5, 2, "DPLRD", "Data-in to PRE Period. tDPLR", PRESENT_DEC, {
221 { MSR1(0), "Invalid value" },
230 { 0x2000001a, MSRTYPE_RDWR, MSR2(0, 0x11080001), "MC_CF1017_DATA", "Feature Enables", {
231 { 63, 34, RESERVED },
232 { 29, 2, "WR_TO_RD", "Write to Read Delay. tWTR", PRESENT_DEC, NOBITS },
234 { 26, 3, "RD_TMG_CTL", "Read Timing Control", PRESENT_DEC, NOBITS },
236 { 20, 5, "REF2ACT", "Refresh to Activate Delay. tRFC", PRESENT_DEC, NOBITS },
237 { 15, 8, "PM1_UP_DLY", "PMode1 Up Delay", PRESENT_DEC, NOBITS },
239 { 2, 3, "WR2DAT", "Write Command to Data Latency", PRESENT_DEC, {
240 { MSR1(0), "No delay" },
241 { MSR1(1), "1-clock delay for unbuffered DIMMs" },
242 { MSR1(2), "2-clock delay" },
243 { MSR1(3), "Invalid value" },
248 { 0x2000001b, MSRTYPE_RDONLY, MSR2(0, 0), "MC_CFPERF_CNT1", "Performance Counters", {
249 { 63, 32, "CNT0", "Counter 0", PRESENT_DEC, NOBITS },
250 { 31, 32, "CNT1", "Counter 1", PRESENT_DEC, NOBITS },
253 { 0x2000001c, MSRTYPE_RDWR, MSR2(0, 0x00ff00ff), "MC_PERFCNT2", "Counter and CAS Control", {
254 { 63, 28, RESERVED },
255 { 35, 1, "STOP_CNT1", "Stop Counter 1", PRESENT_DEC, NOBITS },
256 { 34, 1, "RST_CNT1", "Reset Counter 1", PRESENT_DEC, NOBITS },
257 { 33, 1, "STOP_CNT0", "Stop Counter 0", PRESENT_DEC, NOBITS },
258 { 32, 1, "RST_CNT0", "Reset Counter 0", PRESENT_DEC, NOBITS },
259 { 31, 32, RESERVED },
262 { 0x2000001d, MSRTYPE_RDWR, MSR2(0, 0x1300), "MC_CFCLK_DBUG", "Clocking and Debug", {
263 { 63, 29, RESERVED },
264 { 34, 1, "B2B_DIS", "Back-to-Back Command Disable", PRESENT_BIN, {
265 { MSR1(0), "Allow back-to-back commands" },
266 { MSR1(1), "Disable back-to-back commands" },
269 { 33, 1, "MTEST_RBEX_EN", "MTEST RBEX Enable", PRESENT_BIN, {
270 { MSR1(0), "Disable" },
271 { MSR1(1), "Enable" },
274 { 32, 1, "MTEST_EN", "MTEST Enable", PRESENT_BIN, {
275 { MSR1(0), "Disable" },
276 { MSR1(1), "Enable" },
279 { 31, 15, RESERVED },
280 { 16, 1, "FORCE_PRE", "Force Precharge-all", PRESENT_BIN, {
281 { MSR1(0), "Disable" },
282 { MSR1(1), "Enable" },
286 { 12, 1, "TRISTATE_DIS", "TRI-STATE Disable", PRESENT_BIN, {
287 { MSR1(0), "Tri-stating enabled" },
288 { MSR1(1), "Tri-stating disabled" },
292 { 9, 1, "MASK_CKE1", "CKE1 Mask", PRESENT_BIN, {
293 { MSR1(0), "CKE1 output enable unmasked" },
294 { MSR1(1), "CKE1 output enable masked" },
297 { 8, 1, "MASK_CKE0", "CKE0 Mask", PRESENT_BIN, {
298 { MSR1(0), "CKE0 output enable unmasked" },
299 { MSR1(1), "CKE0 output enable masked" },
302 { 7, 1, "CNTL_MSK1", "Control Mask 1", PRESENT_BIN, {
303 { MSR1(0), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable unmasked" },
304 { MSR1(1), "DIMM1 CAS1# RAS1# WE1# CS[3:2]# output enable masked" },
307 { 6, 1, "CNTL_MSK0", "Control Mask 0", PRESENT_BIN, {
308 { MSR1(0), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable unmasked" },
309 { MSR1(1), "DIMM0 CAS0# RAS0# WE0# CS[1:0]# output enable masked" },
312 { 5, 1, "ADRS_MSK", "Address Mask", PRESENT_BIN, {
313 { MSR1(0), "MA and BA output enable unmasked" },
314 { MSR1(1), "MA and BA output enable masked" },
320 { 0x4c00000f, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_DELAY_CONTROLS", "GLCP I/O Delay Controls", {
321 { 63, 1, "EN", "Enable", PRESENT_DEC, {
322 { MSR1(0), "Use default values" },
323 { MSR1(1), "Use value in bits [62:0]" },
326 { 62, 1, "B_DQ", "Buffer Control for DQ DQS DQM TLA drive", PRESENT_DEC, {
327 { MSR1(1), "Half power" },
328 { MSR1(0), "Quarter power" },
331 { 61, 1, "B_CMD", "Buffer Control for RAS CAS CKE CS WE drive", PRESENT_DEC, {
332 { MSR1(1), "Half power" },
333 { MSR1(0), "Quarter power" },
336 { 60, 1, "B_MA", "Buffer Control for MA BA drive", PRESENT_DEC, {
337 { MSR1(0), "Half power" },
338 { MSR1(1), "Full power" },
341 { 59, 1, "SDCLK_SET", "SDCLK Setup", PRESENT_DEC, {
342 { MSR1(0), "Full SDCLK setup" },
343 { MSR1(1), "Half SDCLK setup for control signals" },
346 { 58, 3, "DDR_RLE", "DDR read latch enable position", PRESENT_DEC, NOBITS },
347 { 55, 1, "SDCLK_DIS", "SDCLK disable [1,3,5]", PRESENT_DEC, {
348 { MSR1(0), "All SDCLK output" },
349 { MSR1(1), "SDCLK[0,2,4] output only" },
352 { 54, 3, "TLA1_OA", "TLA hint pin output adjust", PRESENT_DEC, NOBITS },
353 { 51, 2, "D_TLA1", "Output delay for TLA1", PRESENT_DEC, NOBITS },
354 { 49, 2, "D_TLA0", "Output delay for TLA0", PRESENT_DEC, NOBITS },
355 { 47, 2, "D_DQ_E", "Output delay for DQ DQM - even byte lanes", PRESENT_DEC, NOBITS },
356 { 45, 2, "D_DQ_O", "Output delay for DQ DQM - odd byte lanes", PRESENT_DEC, NOBITS },
358 { 41, 2, "D_SDCLK", "Output delay for SDCLK", PRESENT_DEC, NOBITS },
359 { 39, 2, "D_CMD_O", "Output delay for CKE CS RAS CAS WE - odd bits", PRESENT_DEC, NOBITS },
360 { 37, 2, "D_CMD_E", "Output delay for CKE CS RAS CAS WE - even bits", PRESENT_DEC, NOBITS },
361 { 35, 2, "D_MA_O", "Output delay for BA MA - odd bits", PRESENT_DEC, NOBITS },
362 { 33, 2, "D_MA_E", "Output delay for BA MA - even bits", PRESENT_DEC, NOBITS },
363 { 31, 2, "D_PCI_O", "Output delay for pci_ad IRQ13 SUSPA# INTA# - odd bits", PRESENT_DEC, NOBITS },
364 { 29, 2, "D_PCI_E", "Output delay for pci_ad IRQ13 SUSPA# INTA# - even bits", PRESENT_DEC, NOBITS },
365 { 27, 2, "D_DOTCLK", "Output delay for DOTCLK", PRESENT_DEC, NOBITS },
366 { 25, 2, "D_DRGB_O", "Output delay for DRGB[31:0] - odd bits", PRESENT_DEC, NOBITS },
367 { 23, 2, "D_DRGB_E", "Output delay for DRGB[31:0] HSYNC VSYNC DISPEN VDDEN LDE_MOD - even bits", PRESENT_DEC, NOBITS },
368 { 21, 2, "D_PCI_IN", "Input delay for pci_ad CBE# PAR STOP# FRAME# IRDY# TRDY# DEVSEL# REQ# GNT# CIS", PRESENT_DEC, NOBITS },
369 { 19, 2, "D_TDBGI", "Input delay for TDBGI", PRESENT_DEC, NOBITS },
370 { 17, 2, "D_VIP", "Input delay for VID[15:0] VIP_HSYNC VIP_VSYNC", PRESENT_DEC, NOBITS },
371 { 15, 2, "D_VIPCLK", "Input delay for VIPCLK", PRESENT_DEC, NOBITS },
372 { 13, 1, "H_SDCLK", "Half SDCLK hold select (for cmd addr)", PRESENT_DEC, {
373 { MSR1(1), "Half SDCLK setup for MA and BA" },
374 { MSR1(0), "Full SDCLK setup" },
377 { 12, 2, "PLL_FD_DEL", "PLL Feedback Delay", PRESENT_BIN, {
378 { MSR1(0), "No feedback delay" },
379 { MSR1(1), "~350 ps" },
380 { MSR1(2), "~700 ps" },
381 { MSR1(3), "~1100 ps (Max feedback delay)" },
385 { 5, 1, "DLL_OV", "DLL Override (to DLL)", PRESENT_DEC, NOBITS },
386 { 4, 5, "DLL_OVS/RSDA", "DLL Override Setting or Read Strobe Delay Adjust", PRESENT_DEC, NOBITS },
389 { 0x4c000014, MSRTYPE_RDWR, MSR2(0, 0), "GLCP_SYS_RSTPLL", "GLCP System Reset and PLL Control", {
390 { 63, 20, RESERVED },
391 { 43, 5, "GLIUMULT", "GLIU Multiplier", PRESENT_DEC, NOBITS },
392 { 38, 1, "GLIUDIV", "GLIU Divide", PRESENT_DEC, {
393 { MSR1(0), "Do not predivide input" },
394 { MSR1(1), "Divide by 2" },
397 { 37, 5, "COREMULT", "CPU Core Multiplier", PRESENT_DEC, NOBITS },
398 { 32, 1, "COREDIV", "CPU Core Divide", PRESENT_DEC, {
399 { MSR1(0), "Do not predivide input" },
400 { MSR1(1), "Divide by 2" },
403 { 31, 6, "SWFLAGS", "Flags", PRESENT_BIN, NOBITS },
404 { 25, 1, "GLIULOCK", "GLIU PLL Lock", PRESENT_DEC, {
405 { MSR1(1), "PLL locked" },
406 { MSR1(0), "PLL is not locked" },
409 { 24, 1, "CORELOCK", "CPU Core PLL Lock", PRESENT_DEC, {
410 { MSR1(1), "PLL locked" },
411 { MSR1(0), "PLL is not locked" },
414 { 23, 8, "HOLD_COUNT", "Hold Count, divided by 16", PRESENT_DEC, NOBITS },
416 { 14, 1, "GLIUPD", "GLIU PLL Power Down mode", PRESENT_DEC, NOBITS },
417 { 13, 1, "COREPD", "CPU Core PLL Power Down mode", PRESENT_DEC, NOBITS },
418 { 12, 1, "GLIUBYPASS", "GLIU PLL Bypass", PRESENT_DEC, {
419 { MSR1(1), "DOTREF input directly drives the GLIU clock spines" },
420 { MSR1(0), "DOTPLL drives the GLIU clock" },
423 { 11, 1, "COREBYPASS", "CPU Core PLL Bypass", PRESENT_DEC, {
424 { MSR1(1), "DOTREF input directly drives the CPU Core clock" },
425 { MSR1(0), "DOTPLL drives the CPU Core clock" },
428 { 10, 1, "LPFEN", "Loop Filter", PRESENT_DEC, {
429 { MSR1(1), "Enabled" },
430 { MSR1(0), "Disabled" },
433 { 9, 1, "VA_SEMI_SYNC_MODE", "CPU-GLIU Sync Mode", PRESENT_DEC, {
434 { MSR1(1), "CPU does not use GLIU FIFO" },
435 { MSR1(0), "The GLIU FIFO is used by the CPU" },
438 { 8, 1, "PCI_SEMI_SYNC_MODE", "PCI-GLIU Sync Mode", PRESENT_DEC, {
439 { MSR1(1), "PCI does not use mb_func_clk and pci_func_clk falling edges" },
440 { MSR1(0), "Falling edges on mb_func_clk and pci_func_clk are used by PCI" },
443 { 7, 1, "BOOTSTRAP_PW1", "PW1 bootstrap", PRESENT_DEC, {
444 { MSR1(1), "66MHz PCI clock" },
445 { MSR1(0), "33MHz PCI clock" },
448 { 6, 1, "BOOTSTRAP_IRQ13", "IRQ13 bootstrap", PRESENT_DEC, {
449 { MSR1(1), "Stall-on-reset debug feature enabled" },
450 { MSR1(0), "No stall" },
453 { 5, 5, "BOOTSTRAPS", "CPU/GLIU frequency select", PRESENT_BIN, NOBITS },
454 { 0, 1, "CHIP_RESET", "Chip Reset", PRESENT_DEC, NOBITS },
458 { 0, MSRTYPE_RDONLY, MSR2(0, 0), "TEMPLATE", "Template MSR", {
459 { 63, 64, RESERVED },