2 * inteltool - dump all registers on an Intel CPU + chipset based system.
4 * Copyright (C) 2008 by coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include "inteltool.h"
27 * Egress Port Root Complex MMIO configuration space
29 int print_epbar(struct pci_dev *nb)
31 int i, size = (4 * 1024);
32 volatile uint8_t *epbar;
35 printf("\n============= EPBAR =============\n\n");
37 switch (nb->device_id) {
38 case PCI_DEVICE_ID_INTEL_82945GM:
39 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
41 case 0x1234: // Dummy for non-existent functionality
42 printf("This northbrigde does not have EPBAR.\n");
45 printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
49 epbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
50 fd_mem, (off_t) epbar_phys);
52 if (epbar == MAP_FAILED) {
53 perror("Error mapping EPBAR");
57 printf("EPBAR = 0x%08x (MEM)\n\n", epbar_phys);
58 for (i = 0; i < size; i += 4) {
59 if (*(uint32_t *)(epbar + i))
60 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
63 munmap((void *)epbar, size);
68 * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
70 int print_dmibar(struct pci_dev *nb)
72 int i, size = (4 * 1024);
73 volatile uint8_t *dmibar;
76 printf("\n============= DMIBAR ============\n\n");
78 switch (nb->device_id) {
79 case PCI_DEVICE_ID_INTEL_82945GM:
80 dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
82 case 0x1234: // Dummy for non-existent functionality
83 printf("This northbrigde does not have DMIBAR.\n");
86 printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
90 dmibar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
91 fd_mem, (off_t) dmibar_phys);
93 if (dmibar == MAP_FAILED) {
94 perror("Error mapping DMIBAR");
98 printf("DMIBAR = 0x%08x (MEM)\n\n", dmibar_phys);
99 for (i = 0; i < size; i += 4) {
100 if (*(uint32_t *)(dmibar + i))
101 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
104 munmap((void *)dmibar, size);
109 * PCIe MMIO configuration space
111 int print_pciexbar(struct pci_dev *nb)
113 uint32_t pciexbar_reg;
114 uint32_t pciexbar_phys;
115 volatile uint8_t *pciexbar;
116 int max_busses, devbase, i;
119 printf("========= PCIEXBAR ========\n\n");
121 switch (nb->device_id) {
122 case PCI_DEVICE_ID_INTEL_82945GM:
123 pciexbar_reg = pci_read_long(nb, 0x48);
125 case 0x1234: // Dummy for non-existent functionality
126 printf("Error: This northbrigde does not have PCIEXBAR.\n");
129 printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
133 if (!(pciexbar_reg & (1 << 0))) {
134 printf("PCIEXBAR register is disabled.\n");
138 switch ((pciexbar_reg >> 1) & 3) {
140 pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
144 pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
148 pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
152 printf("Undefined address base. Bailing out.\n");
156 printf("PCIEXBAR: 0x%08x\n", pciexbar_phys);
158 pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ,
159 MAP_SHARED, fd_mem, (off_t) pciexbar_phys);
161 if (pciexbar == MAP_FAILED) {
162 perror("Error mapping PCIEXBAR");
166 for (bus = 0; bus < max_busses; bus++) {
167 for (dev = 0; dev < 32; dev++) {
168 for (fn = 0; fn < 8; fn++) {
169 devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
171 if (*(uint16_t *)(pciexbar + devbase) == 0xffff)
174 /* This is a heuristics. Anyone got a better check? */
175 if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) &&
176 (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) {
178 printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
183 printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
184 for (i = 0; i < 4096; i++) {
186 printf("\n%04x:", i);
187 printf(" %02x", *(pciexbar+devbase+i));
194 munmap((void *)pciexbar, (max_busses * 1024 * 1024));