2 * inteltool - dump all registers on an Intel CPU + chipset based system.
4 * Copyright (C) 2008-2010 by coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include "inteltool.h"
25 * Egress Port Root Complex MMIO configuration space
27 int print_epbar(struct pci_dev *nb)
29 int i, size = (4 * 1024);
30 volatile uint8_t *epbar;
33 printf("\n============= EPBAR =============\n\n");
35 switch (nb->device_id) {
36 case PCI_DEVICE_ID_INTEL_82915:
37 case PCI_DEVICE_ID_INTEL_82945GM:
38 case PCI_DEVICE_ID_INTEL_82945GSE:
39 case PCI_DEVICE_ID_INTEL_82945P:
40 case PCI_DEVICE_ID_INTEL_82975X:
41 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
43 case PCI_DEVICE_ID_INTEL_PM965:
44 case PCI_DEVICE_ID_INTEL_Q965:
45 case PCI_DEVICE_ID_INTEL_82Q35:
46 case PCI_DEVICE_ID_INTEL_82G33:
47 case PCI_DEVICE_ID_INTEL_82Q33:
48 case PCI_DEVICE_ID_INTEL_GS45:
49 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
50 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
51 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
52 epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
54 case PCI_DEVICE_ID_INTEL_82810:
55 case PCI_DEVICE_ID_INTEL_82810DC:
56 case PCI_DEVICE_ID_INTEL_82810E_MC:
57 case PCI_DEVICE_ID_INTEL_82830M:
58 printf("This northbrigde does not have EPBAR.\n");
61 printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
65 epbar = map_physical(epbar_phys, size);
68 perror("Error mapping EPBAR");
72 printf("EPBAR = 0x%08llx (MEM)\n\n", epbar_phys);
73 for (i = 0; i < size; i += 4) {
74 if (*(uint32_t *)(epbar + i))
75 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
78 unmap_physical((void *)epbar, size);
83 * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
85 int print_dmibar(struct pci_dev *nb)
87 int i, size = (4 * 1024);
88 volatile uint8_t *dmibar;
91 printf("\n============= DMIBAR ============\n\n");
93 switch (nb->device_id) {
94 case PCI_DEVICE_ID_INTEL_82915:
95 case PCI_DEVICE_ID_INTEL_82945GM:
96 case PCI_DEVICE_ID_INTEL_82945GSE:
97 case PCI_DEVICE_ID_INTEL_82945P:
98 case PCI_DEVICE_ID_INTEL_82975X:
99 dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
101 case PCI_DEVICE_ID_INTEL_PM965:
102 case PCI_DEVICE_ID_INTEL_Q965:
103 case PCI_DEVICE_ID_INTEL_82Q35:
104 case PCI_DEVICE_ID_INTEL_82G33:
105 case PCI_DEVICE_ID_INTEL_82Q33:
106 case PCI_DEVICE_ID_INTEL_GS45:
107 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
108 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
109 dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
110 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
112 case PCI_DEVICE_ID_INTEL_82810:
113 case PCI_DEVICE_ID_INTEL_82810DC:
114 case PCI_DEVICE_ID_INTEL_82810E_MC:
115 printf("This northbrigde does not have DMIBAR.\n");
118 printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
122 dmibar = map_physical(dmibar_phys, size);
124 if (dmibar == NULL) {
125 perror("Error mapping DMIBAR");
129 printf("DMIBAR = 0x%08llx (MEM)\n\n", dmibar_phys);
130 for (i = 0; i < size; i += 4) {
131 if (*(uint32_t *)(dmibar + i))
132 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
135 unmap_physical((void *)dmibar, size);
140 * PCIe MMIO configuration space
142 int print_pciexbar(struct pci_dev *nb)
144 uint64_t pciexbar_reg;
145 uint64_t pciexbar_phys;
146 volatile uint8_t *pciexbar;
147 int max_busses, devbase, i;
150 printf("========= PCIEXBAR ========\n\n");
152 switch (nb->device_id) {
153 case PCI_DEVICE_ID_INTEL_82915:
154 case PCI_DEVICE_ID_INTEL_82945GM:
155 case PCI_DEVICE_ID_INTEL_82945GSE:
156 case PCI_DEVICE_ID_INTEL_82945P:
157 case PCI_DEVICE_ID_INTEL_82975X:
158 pciexbar_reg = pci_read_long(nb, 0x48);
160 case PCI_DEVICE_ID_INTEL_PM965:
161 case PCI_DEVICE_ID_INTEL_Q965:
162 case PCI_DEVICE_ID_INTEL_82Q35:
163 case PCI_DEVICE_ID_INTEL_82G33:
164 case PCI_DEVICE_ID_INTEL_82Q33:
165 case PCI_DEVICE_ID_INTEL_GS45:
166 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
167 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
168 pciexbar_reg = pci_read_long(nb, 0x60);
169 pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
171 case PCI_DEVICE_ID_INTEL_82810:
172 case PCI_DEVICE_ID_INTEL_82810DC:
173 case PCI_DEVICE_ID_INTEL_82810E_MC:
174 printf("Error: This northbrigde does not have PCIEXBAR.\n");
177 printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
181 if (!(pciexbar_reg & (1 << 0))) {
182 printf("PCIEXBAR register is disabled.\n");
186 switch ((pciexbar_reg >> 1) & 3) {
188 pciexbar_phys = pciexbar_reg & (0xff << 28);
192 pciexbar_phys = pciexbar_reg & (0x1ff << 27);
196 pciexbar_phys = pciexbar_reg & (0x3ff << 26);
200 printf("Undefined address base. Bailing out.\n");
204 printf("PCIEXBAR: 0x%08llx\n", pciexbar_phys);
206 pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024));
208 if (pciexbar == NULL) {
209 perror("Error mapping PCIEXBAR");
213 for (bus = 0; bus < max_busses; bus++) {
214 for (dev = 0; dev < 32; dev++) {
215 for (fn = 0; fn < 8; fn++) {
216 devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
218 if (*(uint16_t *)(pciexbar + devbase) == 0xffff)
221 /* This is a heuristics. Anyone got a better check? */
222 if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) &&
223 (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) {
225 printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
230 printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
231 for (i = 0; i < 4096; i++) {
233 printf("\n%04x:", i);
234 printf(" %02x", *(pciexbar+devbase+i));
241 unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024));