2 * inteltool - dump all registers on an Intel CPU + chipset based system.
4 * Copyright (C) 2008-2010 by coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include "inteltool.h"
25 * Egress Port Root Complex MMIO configuration space
27 int print_epbar(struct pci_dev *nb)
29 int i, size = (4 * 1024);
30 volatile uint8_t *epbar;
33 printf("\n============= EPBAR =============\n\n");
35 switch (nb->device_id) {
36 case PCI_DEVICE_ID_INTEL_82915:
37 case PCI_DEVICE_ID_INTEL_82945GM:
38 case PCI_DEVICE_ID_INTEL_82945GSE:
39 case PCI_DEVICE_ID_INTEL_82945P:
40 case PCI_DEVICE_ID_INTEL_82975X:
41 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
43 case PCI_DEVICE_ID_INTEL_PM965:
44 case PCI_DEVICE_ID_INTEL_Q965:
45 case PCI_DEVICE_ID_INTEL_82Q35:
46 case PCI_DEVICE_ID_INTEL_82G33:
47 case PCI_DEVICE_ID_INTEL_82Q33:
48 case PCI_DEVICE_ID_INTEL_GS45:
49 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
50 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
51 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
52 epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
54 case PCI_DEVICE_ID_INTEL_82810:
55 case PCI_DEVICE_ID_INTEL_82810DC:
56 case PCI_DEVICE_ID_INTEL_82810E_MC:
57 case PCI_DEVICE_ID_INTEL_82830M:
58 printf("This northbrigde does not have EPBAR.\n");
61 printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
65 epbar = map_physical(epbar_phys, size);
68 perror("Error mapping EPBAR");
72 printf("EPBAR = 0x%08llx (MEM)\n\n", epbar_phys);
73 for (i = 0; i < size; i += 4) {
74 if (*(uint32_t *)(epbar + i))
75 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
78 unmap_physical((void *)epbar, size);
83 * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
85 int print_dmibar(struct pci_dev *nb)
87 int i, size = (4 * 1024);
88 volatile uint8_t *dmibar;
91 printf("\n============= DMIBAR ============\n\n");
93 switch (nb->device_id) {
94 case PCI_DEVICE_ID_INTEL_82915:
95 case PCI_DEVICE_ID_INTEL_82945GM:
96 case PCI_DEVICE_ID_INTEL_82945GSE:
97 case PCI_DEVICE_ID_INTEL_82945P:
98 case PCI_DEVICE_ID_INTEL_82975X:
99 dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
101 case PCI_DEVICE_ID_INTEL_PM965:
102 case PCI_DEVICE_ID_INTEL_Q965:
103 case PCI_DEVICE_ID_INTEL_82Q35:
104 case PCI_DEVICE_ID_INTEL_82G33:
105 case PCI_DEVICE_ID_INTEL_82Q33:
106 case PCI_DEVICE_ID_INTEL_GS45:
107 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
108 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
109 dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
110 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
112 case PCI_DEVICE_ID_INTEL_82810:
113 case PCI_DEVICE_ID_INTEL_82810DC:
114 case PCI_DEVICE_ID_INTEL_82810E_MC:
115 printf("This northbrigde does not have DMIBAR.\n");
117 case PCI_DEVICE_ID_INTEL_X58:
118 dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;
121 printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
125 dmibar = map_physical(dmibar_phys, size);
127 if (dmibar == NULL) {
128 perror("Error mapping DMIBAR");
132 printf("DMIBAR = 0x%08llx (MEM)\n\n", dmibar_phys);
133 for (i = 0; i < size; i += 4) {
134 if (*(uint32_t *)(dmibar + i))
135 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
138 unmap_physical((void *)dmibar, size);
143 * PCIe MMIO configuration space
145 int print_pciexbar(struct pci_dev *nb)
147 uint64_t pciexbar_reg;
148 uint64_t pciexbar_phys;
149 volatile uint8_t *pciexbar;
150 int max_busses, devbase, i;
153 printf("========= PCIEXBAR ========\n\n");
155 switch (nb->device_id) {
156 case PCI_DEVICE_ID_INTEL_82915:
157 case PCI_DEVICE_ID_INTEL_82945GM:
158 case PCI_DEVICE_ID_INTEL_82945GSE:
159 case PCI_DEVICE_ID_INTEL_82945P:
160 case PCI_DEVICE_ID_INTEL_82975X:
161 pciexbar_reg = pci_read_long(nb, 0x48);
163 case PCI_DEVICE_ID_INTEL_PM965:
164 case PCI_DEVICE_ID_INTEL_Q965:
165 case PCI_DEVICE_ID_INTEL_82Q35:
166 case PCI_DEVICE_ID_INTEL_82G33:
167 case PCI_DEVICE_ID_INTEL_82Q33:
168 case PCI_DEVICE_ID_INTEL_GS45:
169 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
170 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
171 pciexbar_reg = pci_read_long(nb, 0x60);
172 pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
174 case PCI_DEVICE_ID_INTEL_82810:
175 case PCI_DEVICE_ID_INTEL_82810DC:
176 case PCI_DEVICE_ID_INTEL_82810E_MC:
177 printf("Error: This northbrigde does not have PCIEXBAR.\n");
180 printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
184 if (!(pciexbar_reg & (1 << 0))) {
185 printf("PCIEXBAR register is disabled.\n");
189 switch ((pciexbar_reg >> 1) & 3) {
191 pciexbar_phys = pciexbar_reg & (0xff << 28);
195 pciexbar_phys = pciexbar_reg & (0x1ff << 27);
199 pciexbar_phys = pciexbar_reg & (0x3ff << 26);
203 printf("Undefined address base. Bailing out.\n");
207 printf("PCIEXBAR: 0x%08llx\n", pciexbar_phys);
209 pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024));
211 if (pciexbar == NULL) {
212 perror("Error mapping PCIEXBAR");
216 for (bus = 0; bus < max_busses; bus++) {
217 for (dev = 0; dev < 32; dev++) {
218 for (fn = 0; fn < 8; fn++) {
219 devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
221 if (*(uint16_t *)(pciexbar + devbase) == 0xffff)
224 /* This is a heuristics. Anyone got a better check? */
225 if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) &&
226 (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) {
228 printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
233 printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
234 for (i = 0; i < 4096; i++) {
236 printf("\n%04x:", i);
237 printf(" %02x", *(pciexbar+devbase+i));
244 unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024));