2 * inteltool - dump all registers on an Intel CPU + chipset based system.
4 * Copyright (C) 2008-2010 by coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include "inteltool.h"
25 * Egress Port Root Complex MMIO configuration space
27 int print_epbar(struct pci_dev *nb)
29 int i, size = (4 * 1024);
30 volatile uint8_t *epbar;
33 printf("\n============= EPBAR =============\n\n");
35 switch (nb->device_id) {
36 case PCI_DEVICE_ID_INTEL_82915:
37 case PCI_DEVICE_ID_INTEL_82945GM:
38 case PCI_DEVICE_ID_INTEL_82945P:
39 case PCI_DEVICE_ID_INTEL_82975X:
40 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
42 case PCI_DEVICE_ID_INTEL_PM965:
43 case PCI_DEVICE_ID_INTEL_Q965:
44 case PCI_DEVICE_ID_INTEL_82Q35:
45 case PCI_DEVICE_ID_INTEL_82G33:
46 case PCI_DEVICE_ID_INTEL_82Q33:
47 case PCI_DEVICE_ID_INTEL_GS45:
48 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
49 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
50 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
51 epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
53 case PCI_DEVICE_ID_INTEL_82810:
54 case PCI_DEVICE_ID_INTEL_82810DC:
55 case PCI_DEVICE_ID_INTEL_82810E_MC:
56 case PCI_DEVICE_ID_INTEL_82830M:
57 printf("This northbrigde does not have EPBAR.\n");
60 printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
64 epbar = map_physical(epbar_phys, size);
67 perror("Error mapping EPBAR");
71 printf("EPBAR = 0x%08llx (MEM)\n\n", epbar_phys);
72 for (i = 0; i < size; i += 4) {
73 if (*(uint32_t *)(epbar + i))
74 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
77 unmap_physical((void *)epbar, size);
82 * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
84 int print_dmibar(struct pci_dev *nb)
86 int i, size = (4 * 1024);
87 volatile uint8_t *dmibar;
90 printf("\n============= DMIBAR ============\n\n");
92 switch (nb->device_id) {
93 case PCI_DEVICE_ID_INTEL_82915:
94 case PCI_DEVICE_ID_INTEL_82945GM:
95 case PCI_DEVICE_ID_INTEL_82945P:
96 case PCI_DEVICE_ID_INTEL_82975X:
97 dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
99 case PCI_DEVICE_ID_INTEL_PM965:
100 case PCI_DEVICE_ID_INTEL_Q965:
101 case PCI_DEVICE_ID_INTEL_82Q35:
102 case PCI_DEVICE_ID_INTEL_82G33:
103 case PCI_DEVICE_ID_INTEL_82Q33:
104 case PCI_DEVICE_ID_INTEL_GS45:
105 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
106 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
107 dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
108 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
110 case PCI_DEVICE_ID_INTEL_82810:
111 case PCI_DEVICE_ID_INTEL_82810DC:
112 case PCI_DEVICE_ID_INTEL_82810E_MC:
113 printf("This northbrigde does not have DMIBAR.\n");
116 printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
120 dmibar = map_physical(dmibar_phys, size);
122 if (dmibar == NULL) {
123 perror("Error mapping DMIBAR");
127 printf("DMIBAR = 0x%08llx (MEM)\n\n", dmibar_phys);
128 for (i = 0; i < size; i += 4) {
129 if (*(uint32_t *)(dmibar + i))
130 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
133 unmap_physical((void *)dmibar, size);
138 * PCIe MMIO configuration space
140 int print_pciexbar(struct pci_dev *nb)
142 uint64_t pciexbar_reg;
143 uint64_t pciexbar_phys;
144 volatile uint8_t *pciexbar;
145 int max_busses, devbase, i;
148 printf("========= PCIEXBAR ========\n\n");
150 switch (nb->device_id) {
151 case PCI_DEVICE_ID_INTEL_82915:
152 case PCI_DEVICE_ID_INTEL_82945GM:
153 case PCI_DEVICE_ID_INTEL_82945P:
154 case PCI_DEVICE_ID_INTEL_82975X:
155 pciexbar_reg = pci_read_long(nb, 0x48);
157 case PCI_DEVICE_ID_INTEL_PM965:
158 case PCI_DEVICE_ID_INTEL_Q965:
159 case PCI_DEVICE_ID_INTEL_82Q35:
160 case PCI_DEVICE_ID_INTEL_82G33:
161 case PCI_DEVICE_ID_INTEL_82Q33:
162 case PCI_DEVICE_ID_INTEL_GS45:
163 case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
164 case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
165 pciexbar_reg = pci_read_long(nb, 0x60);
166 pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
168 case PCI_DEVICE_ID_INTEL_82810:
169 case PCI_DEVICE_ID_INTEL_82810DC:
170 case PCI_DEVICE_ID_INTEL_82810E_MC:
171 printf("Error: This northbrigde does not have PCIEXBAR.\n");
174 printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
178 if (!(pciexbar_reg & (1 << 0))) {
179 printf("PCIEXBAR register is disabled.\n");
183 switch ((pciexbar_reg >> 1) & 3) {
185 pciexbar_phys = pciexbar_reg & (0xff << 28);
189 pciexbar_phys = pciexbar_reg & (0x1ff << 27);
193 pciexbar_phys = pciexbar_reg & (0x3ff << 26);
197 printf("Undefined address base. Bailing out.\n");
201 printf("PCIEXBAR: 0x%08llx\n", pciexbar_phys);
203 pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024));
205 if (pciexbar == NULL) {
206 perror("Error mapping PCIEXBAR");
210 for (bus = 0; bus < max_busses; bus++) {
211 for (dev = 0; dev < 32; dev++) {
212 for (fn = 0; fn < 8; fn++) {
213 devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
215 if (*(uint16_t *)(pciexbar + devbase) == 0xffff)
218 /* This is a heuristics. Anyone got a better check? */
219 if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) &&
220 (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) {
222 printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
227 printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
228 for (i = 0; i < 4096; i++) {
230 printf("\n%04x:", i);
231 printf(" %02x", *(pciexbar+devbase+i));
238 unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024));