2 * inteltool - dump all registers on an Intel CPU + chipset based system.
4 * Copyright (C) 2008 by coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include "inteltool.h"
24 static const io_register_t ich0_gpio_registers[] = {
25 { 0x00, 4, "GPIO_USE_SEL" },
26 { 0x04, 4, "GP_IO_SEL" },
27 { 0x08, 4, "RESERVED" },
28 { 0x0c, 4, "GP_LVL" },
29 { 0x10, 4, "RESERVED" },
30 { 0x14, 4, "GPO_TTL" },
31 { 0x18, 4, "GPO_BLINK" },
32 { 0x1c, 4, "RESERVED" },
33 { 0x20, 4, "RESERVED" },
34 { 0x24, 4, "RESERVED" },
35 { 0x28, 4, "RESERVED" },
36 { 0x2c, 4, "GPI_INV" },
37 { 0x30, 4, "RESERVED" },
38 { 0x34, 4, "RESERVED" },
39 { 0x38, 4, "RESERVED" },
40 { 0x3C, 4, "RESERVED" }
43 static const io_register_t ich4_gpio_registers[] = {
44 { 0x00, 4, "GPIO_USE_SEL" },
45 { 0x04, 4, "GP_IO_SEL" },
46 { 0x08, 4, "RESERVED" },
47 { 0x0c, 4, "GP_LVL" },
48 { 0x10, 4, "RESERVED" },
49 { 0x14, 4, "GPO_TTL" },
50 { 0x18, 4, "GPO_BLINK" },
51 { 0x1c, 4, "RESERVED" },
52 { 0x20, 4, "RESERVED" },
53 { 0x24, 4, "RESERVED" },
54 { 0x28, 4, "RESERVED" },
55 { 0x2c, 4, "GPI_INV" },
56 { 0x30, 4, "GPIO_USE_SEL2" },
57 { 0x34, 4, "GP_IO_SEL2" },
58 { 0x38, 4, "GP_LVL2" },
59 { 0x3C, 4, "RESERVED" }
62 static const io_register_t ich7_gpio_registers[] = {
63 { 0x00, 4, "GPIO_USE_SEL" },
64 { 0x04, 4, "GP_IO_SEL" },
65 { 0x08, 4, "RESERVED" },
66 { 0x0c, 4, "GP_LVL" },
67 { 0x10, 4, "RESERVED" },
68 { 0x14, 4, "RESERVED" },
69 { 0x18, 4, "GPO_BLINK" },
70 { 0x1c, 4, "RESERVED" },
71 { 0x20, 4, "RESERVED" },
72 { 0x24, 4, "RESERVED" },
73 { 0x28, 4, "RESERVED" },
74 { 0x2c, 4, "GPI_INV" },
75 { 0x30, 4, "GPIO_USE_SEL2" },
76 { 0x34, 4, "GP_IO_SEL2" },
77 { 0x38, 4, "GP_LVL2" },
78 { 0x3C, 4, "RESERVED" }
81 int print_gpios(struct pci_dev *sb)
85 const io_register_t *gpio_registers;
87 printf("\n============= GPIOS =============\n\n");
89 switch (sb->device_id) {
90 case PCI_DEVICE_ID_INTEL_ICH7:
91 case PCI_DEVICE_ID_INTEL_ICH7M:
92 case PCI_DEVICE_ID_INTEL_ICH7DH:
93 case PCI_DEVICE_ID_INTEL_ICH7MDH:
94 gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
95 gpio_registers = ich7_gpio_registers;
96 size = ARRAY_SIZE(ich7_gpio_registers);
98 case PCI_DEVICE_ID_INTEL_ICH4:
99 case PCI_DEVICE_ID_INTEL_ICH4M:
100 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
101 gpio_registers = ich4_gpio_registers;
102 size = ARRAY_SIZE(ich4_gpio_registers);
104 case PCI_DEVICE_ID_INTEL_ICH:
105 case PCI_DEVICE_ID_INTEL_ICH0:
106 gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
107 gpio_registers = ich0_gpio_registers;
108 size = ARRAY_SIZE(ich0_gpio_registers);
110 case 0x1234: // Dummy for non-existent functionality
111 printf("This southbridge does not have GPIOBASE.\n");
114 printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
118 printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase);
120 for (i = 0; i < size; i++) {
121 switch (gpio_registers[i].size) {
123 printf("gpiobase+0x%04x: 0x%08x (%s)\n",
124 gpio_registers[i].addr,
125 inl(gpiobase+gpio_registers[i].addr),
126 gpio_registers[i].name);
129 printf("gpiobase+0x%04x: 0x%04x (%s)\n",
130 gpio_registers[i].addr,
131 inw(gpiobase+gpio_registers[i].addr),
132 gpio_registers[i].name);
135 printf("gpiobase+0x%04x: 0x%02x (%s)\n",
136 gpio_registers[i].addr,
137 inb(gpiobase+gpio_registers[i].addr),
138 gpio_registers[i].name);