2 * inteltool - dump all registers on an Intel CPU + chipset based system.
4 * Copyright (C) 2008-2010 by coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include "inteltool.h"
31 unsigned int cpuid(unsigned int op)
35 #if defined(__DARWIN__) && !defined(__LP64__)
40 : "=a" (ret) : "a" (op) : "%ecx", "%edx"
43 asm ("cpuid" : "=a" (ret) : "a" (op) : "%ebx", "%ecx", "%edx");
50 int msr_readerror = 0;
55 msr_t msr = { 0xffffffff, 0xffffffff };
57 if (lseek(fd_msr, (off_t) addr, SEEK_SET) == -1) {
58 perror("Could not lseek() to MSR");
63 if (read(fd_msr, buf, 8) == 8) {
64 msr.lo = *(uint32_t *)buf;
65 msr.hi = *(uint32_t *)(buf + 4);
71 printf(" (*)"); // Not all bits of the MSR could be read
75 perror("Could not read() MSR");
84 int print_intel_core_msrs(void)
86 unsigned int i, core, id;
89 #define IA32_PLATFORM_ID 0x0017
90 #define EBL_CR_POWERON 0x002a
91 #define FSB_CLK_STS 0x00cd
92 #define IA32_TIME_STAMP_COUNTER 0x0010
93 #define IA32_APIC_BASE 0x001b
100 static const msr_entry_t model6bx_global_msrs[] = {
101 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
102 { 0x0017, "IA32_PLATFORM_ID" },
103 { 0x001b, "IA32_APIC_BASE" },
104 { 0x002a, "EBL_CR_POWERON" },
105 { 0x0033, "TEST_CTL" },
106 { 0x003f, "THERM_DIODE_OFFSET" },
107 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
108 { 0x008b, "IA32_BIOS_SIGN_ID" },
109 { 0x00c1, "PERFCTR0" },
110 { 0x00c2, "PERFCTR1" },
111 { 0x011e, "BBL_CR_CTL3" },
112 { 0x0179, "IA32_MCG_CAP" },
113 { 0x017a, "IA32_MCG_STATUS" },
114 { 0x0198, "IA32_PERF_STATUS" },
115 { 0x0199, "IA32_PERF_CONTROL" },
116 { 0x019a, "IA32_CLOCK_MODULATION" },
117 { 0x01a0, "IA32_MISC_ENABLES" },
118 { 0x01d9, "IA32_DEBUGCTL" },
119 { 0x0200, "IA32_MTRR_PHYSBASE0" },
120 { 0x0201, "IA32_MTRR_PHYSMASK0" },
121 { 0x0202, "IA32_MTRR_PHYSBASE1" },
122 { 0x0203, "IA32_MTRR_PHYSMASK1" },
123 { 0x0204, "IA32_MTRR_PHYSBASE2" },
124 { 0x0205, "IA32_MTRR_PHYSMASK2" },
125 { 0x0206, "IA32_MTRR_PHYSBASE3" },
126 { 0x0207, "IA32_MTRR_PHYSMASK3" },
127 { 0x0208, "IA32_MTRR_PHYSBASE4" },
128 { 0x0209, "IA32_MTRR_PHYSMASK4" },
129 { 0x020a, "IA32_MTRR_PHYSBASE5" },
130 { 0x020b, "IA32_MTRR_PHYSMASK5" },
131 { 0x020c, "IA32_MTRR_PHYSBASE6" },
132 { 0x020d, "IA32_MTRR_PHYSMASK6" },
133 { 0x020e, "IA32_MTRR_PHYSBASE7" },
134 { 0x020f, "IA32_MTRR_PHYSMASK7" },
135 { 0x0250, "IA32_MTRR_FIX64K_00000" },
136 { 0x0258, "IA32_MTRR_FIX16K_80000" },
137 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
138 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
139 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
140 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
141 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
142 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
143 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
144 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
145 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
146 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
147 { 0x0400, "IA32_MC0_CTL" },
148 { 0x0401, "IA32_MC0_STATUS" },
149 { 0x0402, "IA32_MC0_ADDR" },
150 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
151 { 0x040c, "IA32_MC4_CTL" },
152 { 0x040d, "IA32_MC4_STATUS" },
153 { 0x040e, "IA32_MC4_ADDR" },
154 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
157 static const msr_entry_t model6bx_per_core_msrs[] = {
161 static const msr_entry_t model6ex_global_msrs[] = {
162 { 0x0017, "IA32_PLATFORM_ID" },
163 { 0x002a, "EBL_CR_POWERON" },
164 { 0x00cd, "FSB_CLOCK_STS" },
165 { 0x00ce, "FSB_CLOCK_VCC" },
166 { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" },
167 { 0x00e3, "PMG_IO_BASE_ADDR" },
168 { 0x00e4, "PMG_IO_CAPTURE_ADDR" },
169 { 0x00ee, "EXT_CONFIG" },
170 { 0x011e, "BBL_CR_CTL3" },
171 { 0x0194, "CLOCK_FLEX_MAX" },
172 { 0x0198, "IA32_PERF_STATUS" },
173 { 0x01a0, "IA32_MISC_ENABLES" },
174 { 0x01aa, "PIC_SENS_CFG" },
175 { 0x0400, "IA32_MC0_CTL" },
176 { 0x0401, "IA32_MC0_STATUS" },
177 { 0x0402, "IA32_MC0_ADDR" },
178 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
179 { 0x040c, "IA32_MC4_CTL" },
180 { 0x040d, "IA32_MC4_STATUS" },
181 { 0x040e, "IA32_MC4_ADDR" },
182 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
185 static const msr_entry_t model6ex_per_core_msrs[] = {
186 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
187 { 0x001b, "IA32_APIC_BASE" },
188 { 0x003a, "IA32_FEATURE_CONTROL" },
189 { 0x003f, "IA32_TEMPERATURE_OFFSET" },
190 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
191 { 0x008b, "IA32_BIOS_SIGN_ID" },
192 { 0x00e7, "IA32_MPERF" },
193 { 0x00e8, "IA32_APERF" },
194 { 0x00fe, "IA32_MTRRCAP" },
195 { 0x015f, "DTS_CAL_CTRL" },
196 { 0x0179, "IA32_MCG_CAP" },
197 { 0x017a, "IA32_MCG_STATUS" },
198 { 0x0199, "IA32_PERF_CONTROL" },
199 { 0x019a, "IA32_CLOCK_MODULATION" },
200 { 0x019b, "IA32_THERM_INTERRUPT" },
201 { 0x019c, "IA32_THERM_STATUS" },
202 { 0x019d, "GV_THERM" },
203 { 0x01d9, "IA32_DEBUGCTL" },
204 { 0x0200, "IA32_MTRR_PHYSBASE0" },
205 { 0x0201, "IA32_MTRR_PHYSMASK0" },
206 { 0x0202, "IA32_MTRR_PHYSBASE1" },
207 { 0x0203, "IA32_MTRR_PHYSMASK1" },
208 { 0x0204, "IA32_MTRR_PHYSBASE2" },
209 { 0x0205, "IA32_MTRR_PHYSMASK2" },
210 { 0x0206, "IA32_MTRR_PHYSBASE3" },
211 { 0x0207, "IA32_MTRR_PHYSMASK3" },
212 { 0x0208, "IA32_MTRR_PHYSBASE4" },
213 { 0x0209, "IA32_MTRR_PHYSMASK4" },
214 { 0x020a, "IA32_MTRR_PHYSBASE5" },
215 { 0x020b, "IA32_MTRR_PHYSMASK5" },
216 { 0x020c, "IA32_MTRR_PHYSBASE6" },
217 { 0x020d, "IA32_MTRR_PHYSMASK6" },
218 { 0x020e, "IA32_MTRR_PHYSBASE7" },
219 { 0x020f, "IA32_MTRR_PHYSMASK7" },
220 { 0x0250, "IA32_MTRR_FIX64K_00000" },
221 { 0x0258, "IA32_MTRR_FIX16K_80000" },
222 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
223 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
224 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
225 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
226 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
227 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
228 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
229 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
230 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
231 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
232 //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
235 static const msr_entry_t model6fx_global_msrs[] = {
236 { 0x0017, "IA32_PLATFORM_ID" },
237 { 0x002a, "EBL_CR_POWERON" },
238 { 0x003f, "IA32_TEMPERATURE_OFFSET" },
239 { 0x00a8, "EMTTM_CR_TABLE0" },
240 { 0x00a9, "EMTTM_CR_TABLE1" },
241 { 0x00aa, "EMTTM_CR_TABLE2" },
242 { 0x00ab, "EMTTM_CR_TABLE3" },
243 { 0x00ac, "EMTTM_CR_TABLE4" },
244 { 0x00ad, "EMTTM_CR_TABLE5" },
245 { 0x00cd, "FSB_CLOCK_STS" },
246 { 0x00e2, "PMG_CST_CONFIG_CONTROL" },
247 { 0x00e3, "PMG_IO_BASE_ADDR" },
248 { 0x00e4, "PMG_IO_CAPTURE_ADDR" },
249 { 0x00ee, "EXT_CONFIG" },
250 { 0x011e, "BBL_CR_CTL3" },
251 { 0x0194, "CLOCK_FLEX_MAX" },
252 { 0x0198, "IA32_PERF_STATUS" },
253 { 0x01a0, "IA32_MISC_ENABLES" },
254 { 0x01aa, "PIC_SENS_CFG" },
255 { 0x0400, "IA32_MC0_CTL" },
256 { 0x0401, "IA32_MC0_STATUS" },
257 { 0x0402, "IA32_MC0_ADDR" },
258 //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
259 { 0x040c, "IA32_MC4_CTL" },
260 { 0x040d, "IA32_MC4_STATUS" },
261 { 0x040e, "IA32_MC4_ADDR" },
262 //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
265 static const msr_entry_t model6fx_per_core_msrs[] = {
266 { 0x0010, "IA32_TIME_STAMP_COUNTER" },
267 { 0x001b, "IA32_APIC_BASE" },
268 { 0x003a, "IA32_FEATURE_CONTROL" },
269 //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
270 { 0x008b, "IA32_BIOS_SIGN_ID" },
271 { 0x00e1, "SMM_CST_MISC_INFO" },
272 { 0x00e7, "IA32_MPERF" },
273 { 0x00e8, "IA32_APERF" },
274 { 0x00fe, "IA32_MTRRCAP" },
275 { 0x0179, "IA32_MCG_CAP" },
276 { 0x017a, "IA32_MCG_STATUS" },
277 { 0x0199, "IA32_PERF_CONTROL" },
278 { 0x019a, "IA32_THERM_CTL" },
279 { 0x019b, "IA32_THERM_INTERRUPT" },
280 { 0x019c, "IA32_THERM_STATUS" },
281 { 0x019d, "MSR_THERM2_CTL" },
282 { 0x01d9, "IA32_DEBUGCTL" },
283 { 0x0200, "IA32_MTRR_PHYSBASE0" },
284 { 0x0201, "IA32_MTRR_PHYSMASK0" },
285 { 0x0202, "IA32_MTRR_PHYSBASE1" },
286 { 0x0203, "IA32_MTRR_PHYSMASK1" },
287 { 0x0204, "IA32_MTRR_PHYSBASE2" },
288 { 0x0205, "IA32_MTRR_PHYSMASK2" },
289 { 0x0206, "IA32_MTRR_PHYSBASE3" },
290 { 0x0207, "IA32_MTRR_PHYSMASK3" },
291 { 0x0208, "IA32_MTRR_PHYSBASE4" },
292 { 0x0209, "IA32_MTRR_PHYSMASK4" },
293 { 0x020a, "IA32_MTRR_PHYSBASE5" },
294 { 0x020b, "IA32_MTRR_PHYSMASK5" },
295 { 0x020c, "IA32_MTRR_PHYSBASE6" },
296 { 0x020d, "IA32_MTRR_PHYSMASK6" },
297 { 0x020e, "IA32_MTRR_PHYSBASE7" },
298 { 0x020f, "IA32_MTRR_PHYSMASK7" },
299 { 0x0250, "IA32_MTRR_FIX64K_00000" },
300 { 0x0258, "IA32_MTRR_FIX16K_80000" },
301 { 0x0259, "IA32_MTRR_FIX16K_A0000" },
302 { 0x0268, "IA32_MTRR_FIX4K_C0000" },
303 { 0x0269, "IA32_MTRR_FIX4K_C8000" },
304 { 0x026a, "IA32_MTRR_FIX4K_D0000" },
305 { 0x026b, "IA32_MTRR_FIX4K_D8000" },
306 { 0x026c, "IA32_MTRR_FIX4K_E0000" },
307 { 0x026d, "IA32_MTRR_FIX4K_E8000" },
308 { 0x026e, "IA32_MTRR_FIX4K_F0000" },
309 { 0x026f, "IA32_MTRR_FIX4K_F8000" },
310 { 0x02ff, "IA32_MTRR_DEF_TYPE" },
311 //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO
316 const msr_entry_t *global_msrs;
317 unsigned int num_global_msrs;
318 const msr_entry_t *per_core_msrs;
319 unsigned int num_per_core_msrs;
323 { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
324 { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
325 { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
330 /* Get CPU family and model, not the stepping
331 * (TODO: extended family/model)
333 id = cpuid(1) & 0xff0;
334 for (i = 0; i < ARRAY_SIZE(cpulist); i++) {
335 if(cpulist[i].model == id) {
342 printf("Error: Dumping MSRs on this CPU (0x%06x) is not (yet) supported.\n", id);
347 fd_msr = open("/dev/cpu/0/msr", O_RDWR);
349 perror("Error while opening /dev/cpu/0/msr");
350 printf("Did you run 'modprobe msr'?\n");
355 printf("\n===================== SHARED MSRs (All Cores) =====================\n");
357 for (i = 0; i < cpu->num_global_msrs; i++) {
358 msr = rdmsr(cpu->global_msrs[i].number);
359 printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
360 cpu->global_msrs[i].number, msr.hi, msr.lo,
361 cpu->global_msrs[i].name);
366 for (core = 0; core < 8; core++) {
368 char msrfilename[64];
369 memset(msrfilename, 0, 64);
370 sprintf(msrfilename, "/dev/cpu/%d/msr", core);
372 fd_msr = open(msrfilename, O_RDWR);
374 /* If the file is not there, we're probably through. No error,
375 * since we successfully opened /dev/cpu/0/msr before.
380 if (cpu->num_per_core_msrs)
381 printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core);
383 for (i = 0; i < cpu->num_per_core_msrs; i++) {
384 msr = rdmsr(cpu->per_core_msrs[i].number);
385 printf(" MSR 0x%08X = 0x%08X:0x%08X (%s)\n",
386 cpu->per_core_msrs[i].number, msr.hi, msr.lo,
387 cpu->per_core_msrs[i].name);
396 printf("\n(*) Some MSRs could not be read. The marked values are unreliable.\n");