2 * This file is part of the flashrom project.
4 * Copyright (C) 2008 Peter Stuge <peter@stuge.se>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 #define WBSIO_PORT1 0x2e
28 #define WBSIO_PORT2 0x4e
30 static uint16_t wbsio_spibase = 0;
32 static uint16_t wbsio_get_spibase(uint16_t port)
35 uint16_t flashport = 0;
37 w836xx_ext_enter(port);
38 id = wbsio_read(port, 0x20);
40 fprintf(stderr, "\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id);
44 if (0 == (wbsio_read(port, 0x24) & 2)) {
45 fprintf(stderr, "\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port);
49 wbsio_write(port, 0x07, 0x06);
50 if (0 == (wbsio_read(port, 0x30) & 1)) {
51 fprintf(stderr, "\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port);
55 flashport = (wbsio_read(port, 0x62) << 8) | wbsio_read(port, 0x63);
58 w836xx_ext_leave(port);
62 int wbsio_check_for_spi(const char *name)
64 if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1)))
65 if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2)))
68 printf_debug("\nwbsio_spibase = 0x%x\n", wbsio_spibase);
69 flashbus = BUS_TYPE_WBSIO_SPI;
73 /* W83627DHG has 11 command modes:
75 * 2=1 command+1 data write
76 * 3=1 command+2 data read
77 * 4=1 command+3 address
78 * 5=1 command+3 address+1 data write
79 * 6=1 command+3 address+4 data write
80 * 7=1 command+3 address+1 dummy address inserted by wbsio+4 data read
81 * 8=1 command+3 address+1 data read
82 * 9=1 command+3 address+2 data read
83 * a=1 command+3 address+3 data read
84 * b=1 command+3 address+4 data read
86 * mode[7:4] holds the command mode
87 * mode[3:0] holds SPI address bits [19:16]
89 * The Winbond SPI master only supports 20 bit addresses on the SPI bus. :\
90 * Would one more byte of RAM in the chip (to get all 24 bits) really make
91 * such a big difference?
93 int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt,
94 const unsigned char *writearr, unsigned char *readarr)
99 printf_debug("%s:", __func__);
101 if (1 == writecnt && 0 == readcnt) {
103 } else if (2 == writecnt && 0 == readcnt) {
104 OUTB(writearr[1], wbsio_spibase + 4);
105 printf_debug(" data=0x%02x", writearr[1]);
107 } else if (1 == writecnt && 2 == readcnt) {
109 } else if (4 == writecnt && 0 == readcnt) {
110 printf_debug(" addr=0x%02x", (writearr[1] & 0x0f));
111 for (i = 2; i < writecnt; i++) {
112 OUTB(writearr[i], wbsio_spibase + i);
113 printf_debug("%02x", writearr[i]);
115 mode = 0x40 | (writearr[1] & 0x0f);
116 } else if (5 == writecnt && 0 == readcnt) {
117 printf_debug(" addr=0x%02x", (writearr[1] & 0x0f));
118 for (i = 2; i < 4; i++) {
119 OUTB(writearr[i], wbsio_spibase + i);
120 printf_debug("%02x", writearr[i]);
122 OUTB(writearr[i], wbsio_spibase + i);
123 printf_debug(" data=0x%02x", writearr[i]);
124 mode = 0x50 | (writearr[1] & 0x0f);
125 } else if (8 == writecnt && 0 == readcnt) {
126 printf_debug(" addr=0x%02x", (writearr[1] & 0x0f));
127 for (i = 2; i < 4; i++) {
128 OUTB(writearr[i], wbsio_spibase + i);
129 printf_debug("%02x", writearr[i]);
131 printf_debug(" data=0x");
132 for (; i < writecnt; i++) {
133 OUTB(writearr[i], wbsio_spibase + i);
134 printf_debug("%02x", writearr[i]);
136 mode = 0x60 | (writearr[1] & 0x0f);
137 } else if (5 == writecnt && 4 == readcnt) {
138 /* XXX: TODO not supported by flashrom infrastructure!
139 * This mode, 7, discards the fifth byte in writecnt,
140 * but since we can not express that in flashrom, fail
141 * the operation for now.
144 } else if (4 == writecnt && readcnt >= 1 && readcnt <= 4) {
145 printf_debug(" addr=0x%02x", (writearr[1] & 0x0f));
146 for (i = 2; i < writecnt; i++) {
147 OUTB(writearr[i], wbsio_spibase + i);
148 printf_debug("%02x", writearr[i]);
150 mode = ((7 + readcnt) << 4) | (writearr[1] & 0x0f);
152 printf_debug(" cmd=%02x mode=%02x\n", writearr[0], mode);
155 fprintf(stderr, "%s: unsupported command type wr=%d rd=%d\n",
156 __func__, writecnt, readcnt);
160 OUTB(writearr[0], wbsio_spibase);
161 OUTB(mode, wbsio_spibase + 1);
167 printf_debug("%s: returning data =", __func__);
168 for (i = 0; i < readcnt; i++) {
169 readarr[i] = INB(wbsio_spibase + 4 + i);
170 printf_debug(" 0x%02x", readarr[i]);
176 int wbsio_spi_read(struct flashchip *flash, uint8_t *buf)
178 int size = flash->total_size * 1024;
180 if (flash->total_size > 1024) {
181 fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__);
185 memcpy(buf, (const char *)flash->virtual_memory, size);
189 int wbsio_spi_write(struct flashchip *flash, uint8_t *buf)
191 int pos, size = flash->total_size * 1024;
193 if (flash->total_size > 1024) {
194 fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__);
200 for (pos = 0; pos < size; pos++) {
201 spi_byte_program(pos, buf[pos]);
202 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)