2 * This file is part of the flashrom project.
4 * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 * Contains the generic SPI headers
27 /* Read Electronic ID */
28 #define JEDEC_RDID 0x9f
29 #define JEDEC_RDID_OUTSIZE 0x01
30 #define JEDEC_RDID_INSIZE 0x03
32 /* Read Electronic Signature */
33 #define JEDEC_RES 0xab
34 #define JEDEC_RES_OUTSIZE 0x04
35 #define JEDEC_RES_INSIZE 0x01
38 #define JEDEC_WREN 0x06
39 #define JEDEC_WREN_OUTSIZE 0x01
40 #define JEDEC_WREN_INSIZE 0x00
43 #define JEDEC_WRDI 0x04
44 #define JEDEC_WRDI_OUTSIZE 0x01
45 #define JEDEC_WRDI_INSIZE 0x00
47 /* Chip Erase 0x60 is supported by Macronix/SST chips. */
48 #define JEDEC_CE_60 0x60
49 #define JEDEC_CE_60_OUTSIZE 0x01
50 #define JEDEC_CE_60_INSIZE 0x00
52 /* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */
53 #define JEDEC_CE_C7 0xc7
54 #define JEDEC_CE_C7_OUTSIZE 0x01
55 #define JEDEC_CE_C7_INSIZE 0x00
57 /* Block Erase 0x52 is supported by SST chips. */
58 #define JEDEC_BE_52 0x52
59 #define JEDEC_BE_52_OUTSIZE 0x04
60 #define JEDEC_BE_52_INSIZE 0x00
62 /* Block Erase 0xd8 is supported by EON/Macronix chips. */
63 #define JEDEC_BE_D8 0xd8
64 #define JEDEC_BE_D8_OUTSIZE 0x04
65 #define JEDEC_BE_D8_INSIZE 0x00
67 /* Sector Erase 0x20 is supported by Macronix/SST chips. */
69 #define JEDEC_SE_OUTSIZE 0x04
70 #define JEDEC_SE_INSIZE 0x00
72 /* Read Status Register */
73 #define JEDEC_RDSR 0x05
74 #define JEDEC_RDSR_OUTSIZE 0x01
75 #define JEDEC_RDSR_INSIZE 0x01
76 #define JEDEC_RDSR_BIT_WIP (0x01 << 0)
78 /* Write Status Register */
79 #define JEDEC_WRSR 0x01
80 #define JEDEC_WRSR_OUTSIZE 0x02
81 #define JEDEC_WRSR_INSIZE 0x00
84 #define JEDEC_READ 0x03
85 #define JEDEC_READ_OUTSIZE 0x04
86 /* JEDEC_READ_INSIZE : any length */
88 /* Write memory byte */
89 #define JEDEC_BYTE_PROGRAM 0x02
90 #define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
91 #define JEDEC_BYTE_PROGRAM_INSIZE 0x00
93 #endif /* !__SPI_H__ */