2 * This file is part of the flashrom project.
4 * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 * Contains the generic SPI headers
27 /* Read Electronic ID */
28 #define JEDEC_RDID 0x9f
29 #define JEDEC_RDID_OUTSIZE 0x01
30 #define JEDEC_RDID_INSIZE 0x03
32 /* AT25F512A has bit 3 as don't care bit in commands */
33 #define AT25F512A_RDID 0x15
34 #define AT25F512A_RDID_OUTSIZE 0x01
35 #define AT25F512A_RDID_INSIZE 0x02
37 /* Read Electronic Manufacturer Signature */
38 #define JEDEC_REMS 0x90
39 #define JEDEC_REMS_OUTSIZE 0x04
40 #define JEDEC_REMS_INSIZE 0x02
42 /* Read Electronic Signature */
43 #define JEDEC_RES 0xab
44 #define JEDEC_RES_OUTSIZE 0x04
45 #define JEDEC_RES_INSIZE 0x01
48 #define JEDEC_WREN 0x06
49 #define JEDEC_WREN_OUTSIZE 0x01
50 #define JEDEC_WREN_INSIZE 0x00
53 #define JEDEC_WRDI 0x04
54 #define JEDEC_WRDI_OUTSIZE 0x01
55 #define JEDEC_WRDI_INSIZE 0x00
57 /* Chip Erase 0x60 is supported by Macronix/SST chips. */
58 #define JEDEC_CE_60 0x60
59 #define JEDEC_CE_60_OUTSIZE 0x01
60 #define JEDEC_CE_60_INSIZE 0x00
62 /* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */
63 #define JEDEC_CE_C7 0xc7
64 #define JEDEC_CE_C7_OUTSIZE 0x01
65 #define JEDEC_CE_C7_INSIZE 0x00
67 /* Block Erase 0x52 is supported by SST and old Atmel chips. */
68 #define JEDEC_BE_52 0x52
69 #define JEDEC_BE_52_OUTSIZE 0x04
70 #define JEDEC_BE_52_INSIZE 0x00
72 /* Block Erase 0xd8 is supported by EON/Macronix chips. */
73 #define JEDEC_BE_D8 0xd8
74 #define JEDEC_BE_D8_OUTSIZE 0x04
75 #define JEDEC_BE_D8_INSIZE 0x00
77 /* Sector Erase 0x20 is supported by Macronix/SST chips. */
79 #define JEDEC_SE_OUTSIZE 0x04
80 #define JEDEC_SE_INSIZE 0x00
82 /* Read Status Register */
83 #define JEDEC_RDSR 0x05
84 #define JEDEC_RDSR_OUTSIZE 0x01
85 #define JEDEC_RDSR_INSIZE 0x01
86 #define JEDEC_RDSR_BIT_WIP (0x01 << 0)
88 /* Write Status Enable */
89 #define JEDEC_EWSR 0x50
90 #define JEDEC_EWSR_OUTSIZE 0x01
91 #define JEDEC_EWSR_INSIZE 0x00
93 /* Write Status Register */
94 #define JEDEC_WRSR 0x01
95 #define JEDEC_WRSR_OUTSIZE 0x02
96 #define JEDEC_WRSR_INSIZE 0x00
99 #define JEDEC_READ 0x03
100 #define JEDEC_READ_OUTSIZE 0x04
101 /* JEDEC_READ_INSIZE : any length */
103 /* Write memory byte */
104 #define JEDEC_BYTE_PROGRAM 0x02
105 #define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
106 #define JEDEC_BYTE_PROGRAM_INSIZE 0x00
108 #endif /* !__SPI_H__ */