2 * This file is part of the flashrom project.
4 * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
5 * Copyright (C) 2008 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * Contains the generic SPI framework
33 void spi_prettyprint_status_register(struct flashchip *flash);
35 int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
37 if (it8716f_flashport)
38 return it8716f_spi_command(writecnt, readcnt, writearr, readarr);
39 else if ((ich7_detected) || (viaspi_detected))
40 return ich_spi_command(writecnt, readcnt, writearr, readarr);
41 else if (ich9_detected)
42 return ich_spi_command(writecnt, readcnt, writearr, readarr);
43 printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
47 static int spi_rdid(unsigned char *readarr, int bytes)
49 const unsigned char cmd[JEDEC_RDID_OUTSIZE] = {JEDEC_RDID};
51 if (spi_command(JEDEC_RDID_OUTSIZE, bytes, cmd, readarr))
53 printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], readarr[2]);
57 static int spi_res(unsigned char *readarr)
59 const unsigned char cmd[JEDEC_RES_OUTSIZE] = {JEDEC_RES, 0, 0, 0};
61 if (spi_command(JEDEC_RES_OUTSIZE, JEDEC_RES_INSIZE, cmd, readarr))
63 printf_debug("RES returned %02x.\n", readarr[0]);
67 void spi_write_enable()
69 const unsigned char cmd[JEDEC_WREN_OUTSIZE] = {JEDEC_WREN};
71 /* Send WREN (Write Enable) */
72 spi_command(JEDEC_WREN_OUTSIZE, JEDEC_WREN_INSIZE, cmd, NULL);
75 void spi_write_disable()
77 const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = {JEDEC_WRDI};
79 /* Send WRDI (Write Disable) */
80 spi_command(JEDEC_WRDI_OUTSIZE, JEDEC_WRDI_INSIZE, cmd, NULL);
83 static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
85 unsigned char readarr[4];
89 if (spi_rdid(readarr, bytes))
92 if (!oddparity(readarr[0]))
93 printf_debug("RDID byte 0 parity violation.\n");
95 /* Check if this is a continuation vendor ID */
96 if (readarr[0] == 0x7f) {
97 if (!oddparity(readarr[1]))
98 printf_debug("RDID byte 1 parity violation.\n");
99 manuf_id = (readarr[0] << 8) | readarr[1];
100 model_id = readarr[2];
103 model_id |= readarr[3];
106 manuf_id = readarr[0];
107 model_id = (readarr[1] << 8) | readarr[2];
110 printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id);
112 if (manuf_id == flash->manufacture_id &&
113 model_id == flash->model_id) {
114 /* Print the status register to tell the
115 * user about possible write protection.
117 spi_prettyprint_status_register(flash);
122 /* Test if this is a pure vendor match. */
123 if (manuf_id == flash->manufacture_id &&
124 GENERIC_DEVICE_ID == flash->model_id)
130 int probe_spi_rdid(struct flashchip *flash) {
131 return probe_spi_rdid_generic(flash, 3);
134 /* support 4 bytes flash ID */
135 int probe_spi_rdid4(struct flashchip *flash) {
137 /* only some SPI chipsets support 4 bytes commands */
138 if (!((ich7_detected) || (ich9_detected) || (viaspi_detected)))
140 return probe_spi_rdid_generic(flash, 4);
143 int probe_spi_res(struct flashchip *flash)
145 unsigned char readarr[3];
148 if (spi_rdid(readarr, 3))
149 /* We couldn't issue RDID, it's pointless to try RES. */
152 /* Check if RDID returns 0xff 0xff 0xff, then we use RES. */
153 if ((readarr[0] != 0xff) || (readarr[1] != 0xff) ||
154 (readarr[2] != 0xff))
157 if (spi_res(readarr))
160 model_id = readarr[0];
161 printf_debug("%s: id 0x%x\n", __FUNCTION__, model_id);
162 if (model_id != flash->model_id)
165 /* Print the status register to tell the
166 * user about possible write protection.
168 spi_prettyprint_status_register(flash);
172 uint8_t spi_read_status_register()
174 const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = {JEDEC_RDSR};
175 unsigned char readarr[1];
177 /* Read Status Register */
178 spi_command(JEDEC_RDSR_OUTSIZE, JEDEC_RDSR_INSIZE, cmd, readarr);
182 /* Prettyprint the status register. Common definitions.
184 void spi_prettyprint_status_register_common(uint8_t status)
186 printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
187 "%sset\n", (status & (1 << 5)) ? "" : "not ");
188 printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is "
189 "%sset\n", (status & (1 << 4)) ? "" : "not ");
190 printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
191 "%sset\n", (status & (1 << 3)) ? "" : "not ");
192 printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
193 "%sset\n", (status & (1 << 2)) ? "" : "not ");
194 printf_debug("Chip status register: Write Enable Latch (WEL) is "
195 "%sset\n", (status & (1 << 1)) ? "" : "not ");
196 printf_debug("Chip status register: Write In Progress (WIP/BUSY) is "
197 "%sset\n", (status & (1 << 0)) ? "" : "not ");
200 /* Prettyprint the status register. Works for
204 void spi_prettyprint_status_register_st_m25p(uint8_t status)
206 printf_debug("Chip status register: Status Register Write Disable "
207 "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
208 printf_debug("Chip status register: Bit 6 is "
209 "%sset\n", (status & (1 << 6)) ? "" : "not ");
210 spi_prettyprint_status_register_common(status);
213 /* Prettyprint the status register. Works for
216 void spi_prettyprint_status_register_sst25vf016(uint8_t status)
218 const char *bpt[] = {
227 printf_debug("Chip status register: Block Protect Write Disable "
228 "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
229 printf_debug("Chip status register: Auto Address Increment Programming "
230 "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
231 spi_prettyprint_status_register_common(status);
232 printf_debug("Resulting block protection : %s\n",
233 bpt[(status & 0x1c) >> 2]);
236 void spi_prettyprint_status_register(struct flashchip *flash)
240 status = spi_read_status_register();
241 printf_debug("Chip status register is %02x\n", status);
242 switch (flash->manufacture_id) {
244 if (((flash->model_id & 0xff00) == 0x2000) ||
245 ((flash->model_id & 0xff00) == 0x2500))
246 spi_prettyprint_status_register_st_m25p(status);
249 if ((flash->model_id & 0xff00) == 0x2000)
250 spi_prettyprint_status_register_st_m25p(status);
253 if (flash->model_id == SST_25VF016B)
254 spi_prettyprint_status_register_sst25vf016(status);
259 int spi_chip_erase_c7(struct flashchip *flash)
261 const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = {JEDEC_CE_C7};
263 spi_disable_blockprotect();
265 /* Send CE (Chip Erase) */
266 spi_command(JEDEC_CE_C7_OUTSIZE, JEDEC_CE_C7_INSIZE, cmd, NULL);
267 /* Wait until the Write-In-Progress bit is cleared.
268 * This usually takes 1-85 s, so wait in 1 s steps.
270 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
275 /* Block size is usually
278 * 4-32k non-uniform for EON
280 int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr)
282 unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = {JEDEC_BE_D8};
284 cmd[1] = (addr & 0x00ff0000) >> 16;
285 cmd[2] = (addr & 0x0000ff00) >> 8;
286 cmd[3] = (addr & 0x000000ff);
288 /* Send BE (Block Erase) */
289 spi_command(JEDEC_BE_D8_OUTSIZE, JEDEC_BE_D8_INSIZE, cmd, NULL);
290 /* Wait until the Write-In-Progress bit is cleared.
291 * This usually takes 100-4000 ms, so wait in 100 ms steps.
293 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
298 /* Sector size is usually 4k, though Macronix eliteflash has 64k */
299 int spi_sector_erase(const struct flashchip *flash, unsigned long addr)
301 unsigned char cmd[JEDEC_SE_OUTSIZE] = {JEDEC_SE};
302 cmd[1] = (addr & 0x00ff0000) >> 16;
303 cmd[2] = (addr & 0x0000ff00) >> 8;
304 cmd[3] = (addr & 0x000000ff);
307 /* Send SE (Sector Erase) */
308 spi_command(JEDEC_SE_OUTSIZE, JEDEC_SE_INSIZE, cmd, NULL);
309 /* Wait until the Write-In-Progress bit is cleared.
310 * This usually takes 15-800 ms, so wait in 10 ms steps.
312 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
317 void spi_page_program(int block, uint8_t *buf, uint8_t *bios)
319 if (it8716f_flashport) {
320 it8716f_spi_page_program(block, buf, bios);
323 printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
327 * This is according the SST25VF016 datasheet, who knows it is more
328 * generic that this...
330 void spi_write_status_register(int status)
332 const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = {JEDEC_WRSR, (unsigned char)status};
334 /* Send WRSR (Write Status Register) */
335 spi_command(JEDEC_WRSR_OUTSIZE, JEDEC_WRSR_INSIZE, cmd, NULL);
338 void spi_byte_program(int address, uint8_t byte)
340 const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = {JEDEC_BYTE_PROGRAM,
347 /* Send Byte-Program */
348 spi_command(JEDEC_BYTE_PROGRAM_OUTSIZE, JEDEC_BYTE_PROGRAM_INSIZE, cmd, NULL);
351 void spi_disable_blockprotect(void)
355 status = spi_read_status_register();
356 /* If there is block protection in effect, unprotect it first. */
357 if ((status & 0x3c) != 0) {
358 printf_debug("Some block protection in effect, disabling\n");
360 spi_write_status_register(status & ~0x3c);
364 void spi_nbyte_read(int address, uint8_t *bytes, int len)
366 const unsigned char cmd[JEDEC_READ_OUTSIZE] = {JEDEC_READ,
367 (address >> 16) & 0xff,
368 (address >> 8) & 0xff,
369 (address >> 0) & 0xff,
373 spi_command(JEDEC_READ_OUTSIZE, len, cmd, bytes);
376 int spi_chip_read(struct flashchip *flash, uint8_t *buf)
378 if (it8716f_flashport)
379 return it8716f_spi_chip_read(flash, buf);
380 else if ((ich7_detected) || (viaspi_detected))
381 return ich_spi_read(flash, buf);
382 else if (ich9_detected)
383 return ich_spi_read(flash, buf);
384 printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
388 int spi_chip_write(struct flashchip *flash, uint8_t *buf)
390 if (it8716f_flashport)
391 return it8716f_spi_chip_write(flash, buf);
392 else if ((ich7_detected) || (viaspi_detected))
393 return ich_spi_write(flash, buf);
394 else if (ich9_detected)
395 return ich_spi_write(flash, buf);
396 printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);