2 * This file is part of the flashrom project.
4 * Copyright (C) 2007, 2008 Carl-Daniel Hailfinger
5 * Copyright (C) 2008 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * Contains the generic SPI framework
33 void spi_prettyprint_status_register(struct flashchip *flash);
35 int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
38 case BUS_TYPE_IT87XX_SPI:
39 return it8716f_spi_command(writecnt, readcnt, writearr, readarr);
40 case BUS_TYPE_ICH7_SPI:
41 case BUS_TYPE_ICH9_SPI:
42 case BUS_TYPE_VIA_SPI:
43 return ich_spi_command(writecnt, readcnt, writearr, readarr);
45 printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
50 static int spi_rdid(unsigned char *readarr, int bytes)
52 const unsigned char cmd[JEDEC_RDID_OUTSIZE] = {JEDEC_RDID};
54 if (spi_command(sizeof(cmd), bytes, cmd, readarr))
56 printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], readarr[2]);
60 static int spi_res(unsigned char *readarr)
62 const unsigned char cmd[JEDEC_RES_OUTSIZE] = {JEDEC_RES, 0, 0, 0};
64 if (spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr))
66 printf_debug("RES returned %02x.\n", readarr[0]);
70 void spi_write_enable()
72 const unsigned char cmd[JEDEC_WREN_OUTSIZE] = {JEDEC_WREN};
74 /* Send WREN (Write Enable) */
75 spi_command(sizeof(cmd), 0, cmd, NULL);
78 void spi_write_disable()
80 const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = {JEDEC_WRDI};
82 /* Send WRDI (Write Disable) */
83 spi_command(sizeof(cmd), 0, cmd, NULL);
86 static int probe_spi_rdid_generic(struct flashchip *flash, int bytes)
88 unsigned char readarr[4];
92 if (spi_rdid(readarr, bytes))
95 if (!oddparity(readarr[0]))
96 printf_debug("RDID byte 0 parity violation.\n");
98 /* Check if this is a continuation vendor ID */
99 if (readarr[0] == 0x7f) {
100 if (!oddparity(readarr[1]))
101 printf_debug("RDID byte 1 parity violation.\n");
102 manuf_id = (readarr[0] << 8) | readarr[1];
103 model_id = readarr[2];
106 model_id |= readarr[3];
109 manuf_id = readarr[0];
110 model_id = (readarr[1] << 8) | readarr[2];
113 printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id);
115 if (manuf_id == flash->manufacture_id &&
116 model_id == flash->model_id) {
117 /* Print the status register to tell the
118 * user about possible write protection.
120 spi_prettyprint_status_register(flash);
125 /* Test if this is a pure vendor match. */
126 if (manuf_id == flash->manufacture_id &&
127 GENERIC_DEVICE_ID == flash->model_id)
133 int probe_spi_rdid(struct flashchip *flash) {
134 return probe_spi_rdid_generic(flash, 3);
137 /* support 4 bytes flash ID */
138 int probe_spi_rdid4(struct flashchip *flash) {
140 /* only some SPI chipsets support 4 bytes commands */
142 case BUS_TYPE_ICH7_SPI:
143 case BUS_TYPE_ICH9_SPI:
144 case BUS_TYPE_VIA_SPI:
145 return probe_spi_rdid_generic(flash, 4);
147 printf_debug("4b ID not supported on this SPI controller\n");
153 int probe_spi_res(struct flashchip *flash)
155 unsigned char readarr[3];
158 if (spi_rdid(readarr, 3))
159 /* We couldn't issue RDID, it's pointless to try RES. */
162 /* Check if RDID returns 0xff 0xff 0xff, then we use RES. */
163 if ((readarr[0] != 0xff) || (readarr[1] != 0xff) ||
164 (readarr[2] != 0xff))
167 if (spi_res(readarr))
170 model_id = readarr[0];
171 printf_debug("%s: id 0x%x\n", __FUNCTION__, model_id);
172 if (model_id != flash->model_id)
175 /* Print the status register to tell the
176 * user about possible write protection.
178 spi_prettyprint_status_register(flash);
182 uint8_t spi_read_status_register()
184 const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = {JEDEC_RDSR};
185 unsigned char readarr[JEDEC_RDSR_INSIZE];
187 /* Read Status Register */
188 spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr);
192 /* Prettyprint the status register. Common definitions.
194 void spi_prettyprint_status_register_common(uint8_t status)
196 printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
197 "%sset\n", (status & (1 << 5)) ? "" : "not ");
198 printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is "
199 "%sset\n", (status & (1 << 4)) ? "" : "not ");
200 printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
201 "%sset\n", (status & (1 << 3)) ? "" : "not ");
202 printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
203 "%sset\n", (status & (1 << 2)) ? "" : "not ");
204 printf_debug("Chip status register: Write Enable Latch (WEL) is "
205 "%sset\n", (status & (1 << 1)) ? "" : "not ");
206 printf_debug("Chip status register: Write In Progress (WIP/BUSY) is "
207 "%sset\n", (status & (1 << 0)) ? "" : "not ");
210 /* Prettyprint the status register. Works for
214 void spi_prettyprint_status_register_st_m25p(uint8_t status)
216 printf_debug("Chip status register: Status Register Write Disable "
217 "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
218 printf_debug("Chip status register: Bit 6 is "
219 "%sset\n", (status & (1 << 6)) ? "" : "not ");
220 spi_prettyprint_status_register_common(status);
223 /* Prettyprint the status register. Works for
226 void spi_prettyprint_status_register_sst25vf016(uint8_t status)
228 const char *bpt[] = {
237 printf_debug("Chip status register: Block Protect Write Disable "
238 "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
239 printf_debug("Chip status register: Auto Address Increment Programming "
240 "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
241 spi_prettyprint_status_register_common(status);
242 printf_debug("Resulting block protection : %s\n",
243 bpt[(status & 0x1c) >> 2]);
246 void spi_prettyprint_status_register(struct flashchip *flash)
250 status = spi_read_status_register();
251 printf_debug("Chip status register is %02x\n", status);
252 switch (flash->manufacture_id) {
254 if (((flash->model_id & 0xff00) == 0x2000) ||
255 ((flash->model_id & 0xff00) == 0x2500))
256 spi_prettyprint_status_register_st_m25p(status);
259 if ((flash->model_id & 0xff00) == 0x2000)
260 spi_prettyprint_status_register_st_m25p(status);
263 if (flash->model_id == SST_25VF016B)
264 spi_prettyprint_status_register_sst25vf016(status);
269 int spi_chip_erase_c7(struct flashchip *flash)
271 const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = {JEDEC_CE_C7};
273 spi_disable_blockprotect();
275 /* Send CE (Chip Erase) */
276 spi_command(sizeof(cmd), 0, cmd, NULL);
277 /* Wait until the Write-In-Progress bit is cleared.
278 * This usually takes 1-85 s, so wait in 1 s steps.
280 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
285 /* Block size is usually
288 * 4-32k non-uniform for EON
290 int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr)
292 unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = {JEDEC_BE_D8};
294 cmd[1] = (addr & 0x00ff0000) >> 16;
295 cmd[2] = (addr & 0x0000ff00) >> 8;
296 cmd[3] = (addr & 0x000000ff);
298 /* Send BE (Block Erase) */
299 spi_command(sizeof(cmd), 0, cmd, NULL);
300 /* Wait until the Write-In-Progress bit is cleared.
301 * This usually takes 100-4000 ms, so wait in 100 ms steps.
303 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
308 /* Sector size is usually 4k, though Macronix eliteflash has 64k */
309 int spi_sector_erase(const struct flashchip *flash, unsigned long addr)
311 unsigned char cmd[JEDEC_SE_OUTSIZE] = {JEDEC_SE};
312 cmd[1] = (addr & 0x00ff0000) >> 16;
313 cmd[2] = (addr & 0x0000ff00) >> 8;
314 cmd[3] = (addr & 0x000000ff);
317 /* Send SE (Sector Erase) */
318 spi_command(sizeof(cmd), 0, cmd, NULL);
319 /* Wait until the Write-In-Progress bit is cleared.
320 * This usually takes 15-800 ms, so wait in 10 ms steps.
322 while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
328 * This is according the SST25VF016 datasheet, who knows it is more
329 * generic that this...
331 void spi_write_status_register(int status)
333 const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = {JEDEC_WRSR, (unsigned char)status};
335 /* Send WRSR (Write Status Register) */
336 spi_command(sizeof(cmd), 0, cmd, NULL);
339 void spi_byte_program(int address, uint8_t byte)
341 const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = {JEDEC_BYTE_PROGRAM,
348 /* Send Byte-Program */
349 spi_command(sizeof(cmd), 0, cmd, NULL);
352 void spi_disable_blockprotect(void)
356 status = spi_read_status_register();
357 /* If there is block protection in effect, unprotect it first. */
358 if ((status & 0x3c) != 0) {
359 printf_debug("Some block protection in effect, disabling\n");
361 spi_write_status_register(status & ~0x3c);
365 void spi_nbyte_read(int address, uint8_t *bytes, int len)
367 const unsigned char cmd[JEDEC_READ_OUTSIZE] = {JEDEC_READ,
368 (address >> 16) & 0xff,
369 (address >> 8) & 0xff,
370 (address >> 0) & 0xff,
374 spi_command(sizeof(cmd), len, cmd, bytes);
377 int spi_chip_read(struct flashchip *flash, uint8_t *buf)
381 case BUS_TYPE_IT87XX_SPI:
382 return it8716f_spi_chip_read(flash, buf);
383 case BUS_TYPE_ICH7_SPI:
384 case BUS_TYPE_ICH9_SPI:
385 case BUS_TYPE_VIA_SPI:
386 return ich_spi_read(flash, buf);
388 printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
394 int spi_chip_write(struct flashchip *flash, uint8_t *buf)
397 case BUS_TYPE_IT87XX_SPI:
398 return it8716f_spi_chip_write(flash, buf);
399 case BUS_TYPE_ICH7_SPI:
400 case BUS_TYPE_ICH9_SPI:
401 case BUS_TYPE_VIA_SPI:
402 return ich_spi_write(flash, buf);
404 printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);