2 * This file is part of the flashrom project.
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
7 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 * This module is designed for supporting the devices
30 * ST M25P32 already tested
32 * AT 25DF321 already tested
44 /* ICH9 controller register definition */
45 #define ICH9_REG_FADDR 0x08 /* 32 Bits */
46 #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
48 #define ICH9_REG_SSFS 0x90 /* 08 Bits */
49 #define SSFS_SCIP 0x00000001
50 #define SSFS_CDS 0x00000004
51 #define SSFS_FCERR 0x00000008
52 #define SSFS_AEL 0x00000010
54 #define ICH9_REG_SSFC 0x91 /* 24 Bits */
55 #define SSFC_SCGO 0x00000200
56 #define SSFC_ACS 0x00000400
57 #define SSFC_SPOP 0x00000800
58 #define SSFC_COP 0x00001000
59 #define SSFC_DBC 0x00010000
60 #define SSFC_DS 0x00400000
61 #define SSFC_SME 0x00800000
62 #define SSFC_SCF 0x01000000
63 #define SSFC_SCF_20MHZ 0x00000000
64 #define SSFC_SCF_33MHZ 0x01000000
66 #define ICH9_REG_PREOP 0x94 /* 16 Bits */
67 #define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
68 #define ICH9_REG_OPMENU 0x98 /* 64 Bits */
71 #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
72 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
73 #define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
74 #define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
77 #define ICH7_REG_SPIS 0x00 /* 16 Bits */
78 #define SPIS_SCIP 0x00000001
79 #define SPIS_CDS 0x00000004
80 #define SPIS_FCERR 0x00000008
82 /* VIA SPI is compatible with ICH7, but maxdata
83 to transfer is 16 bytes.
85 DATA byte count on ICH7 is 8:13, on VIA 8:11
87 bit 12 is port select CS0 CS1
88 bit 13 is FAST READ enable
89 bit 7 is used with fast read and one shot controls CS de-assert?
92 #define ICH7_REG_SPIC 0x02 /* 16 Bits */
93 #define SPIC_SCGO 0x0002
94 #define SPIC_ACS 0x0004
95 #define SPIC_SPOP 0x0008
96 #define SPIC_DS 0x4000
98 #define ICH7_REG_SPIA 0x04 /* 32 Bits */
99 #define ICH7_REG_SPID0 0x08 /* 64 Bytes */
100 #define ICH7_REG_PREOP 0x54 /* 16 Bits */
101 #define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
102 #define ICH7_REG_OPMENU 0x58 /* 64 Bits */
104 /* ICH SPI configuration lock-down. May be set during chipset enabling. */
107 typedef struct _OPCODE {
108 uint8_t opcode; //This commands spi opcode
109 uint8_t spi_type; //This commands spi type
110 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
113 /* Opcode definition:
114 * Preop 1: Write Enable
115 * Preop 2: Write Status register enable
117 * OP 0: Write address
120 * OP 3: Read Status register
122 * OP 5: Write Status register
123 * OP 6: chip private (read JDEC id)
126 typedef struct _OPCODES {
131 static OPCODES *curopcodes = NULL;
133 /* HW access functions */
134 static inline uint32_t REGREAD32(int X)
136 volatile uint32_t regval;
137 regval = *(volatile uint32_t *)((uint8_t *) spibar + X);
141 static inline uint16_t REGREAD16(int X)
143 volatile uint16_t regval;
144 regval = *(volatile uint16_t *)((uint8_t *) spibar + X);
148 #define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)spibar+X)=Y)
149 #define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)spibar+X)=Y)
150 #define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)spibar+X)=Y)
152 /* Common SPI functions */
153 static inline int find_opcode(OPCODES *op, uint8_t opcode);
154 static inline int find_preop(OPCODES *op, uint8_t preop);
155 static int generate_opcodes(OPCODES * op);
156 static int program_opcodes(OPCODES * op);
157 static int run_opcode(OPCODE op, uint32_t offset,
158 uint8_t datalength, uint8_t * data);
159 static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf,
160 int offset, int maxdata);
161 static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
162 int offset, int maxdata);
164 /* for pairing opcodes with their required preop */
165 struct preop_opcode_pair {
170 struct preop_opcode_pair pops[] = {
171 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
172 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
173 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
174 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
175 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
176 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
177 {JEDEC_EWSR, JEDEC_WRSR},
181 OPCODES O_ST_M25P = {
186 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Write Byte
187 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
188 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Erase Sector
189 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
190 {JEDEC_RES, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Resume Deep Power-Down
191 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Write Status Register
192 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
193 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Bulk erase
197 OPCODES O_EXISTING = {};
199 static inline int find_opcode(OPCODES *op, uint8_t opcode)
203 for (a = 0; a < 8; a++) {
204 if (op->opcode[a].opcode == opcode)
211 static inline int find_preop(OPCODES *op, uint8_t preop)
215 for (a = 0; a < 2; a++) {
216 if (op->preop[a] == preop)
223 static int generate_opcodes(OPCODES * op)
226 uint16_t preop, optype;
230 printf_debug("\n%s: null OPCODES pointer!\n", __FUNCTION__);
235 case BUS_TYPE_ICH7_SPI:
236 case BUS_TYPE_VIA_SPI:
237 preop = REGREAD16(ICH7_REG_PREOP);
238 optype = REGREAD16(ICH7_REG_OPTYPE);
239 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
240 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
242 case BUS_TYPE_ICH9_SPI:
243 preop = REGREAD16(ICH9_REG_PREOP);
244 optype = REGREAD16(ICH9_REG_OPTYPE);
245 opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
246 opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
249 printf_debug("%s: unsupported chipset\n", __FUNCTION__);
253 op->preop[0] = (uint8_t) preop;
254 op->preop[1] = (uint8_t) (preop >> 8);
256 for (a = 0; a < 8; a++) {
257 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
261 for (a = 0; a < 4; a++) {
262 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
266 for (a = 4; a < 8; a++) {
267 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
271 /* atomic (link opcode with required pre-op) */
272 for (a = 4; a < 8; a++)
273 op->opcode[a].atomic = 0;
275 for (i = 0; pops[i].opcode; i++) {
276 a = find_opcode(op, pops[i].opcode);
277 b = find_preop(op, pops[i].preop);
278 if ((a != -1) && (b != -1))
279 op->opcode[a].atomic = (uint8_t) ++b;
285 int program_opcodes(OPCODES * op)
288 uint16_t preop, optype;
291 /* Program Prefix Opcodes */
293 /* 0:7 Prefix Opcode 1 */
294 preop = (op->preop[0]);
295 /* 8:16 Prefix Opcode 2 */
296 preop |= ((uint16_t) op->preop[1]) << 8;
298 /* Program Opcode Types 0 - 7 */
300 for (a = 0; a < 8; a++) {
301 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
304 /* Program Allowable Opcodes 0 - 3 */
306 for (a = 0; a < 4; a++) {
307 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
310 /*Program Allowable Opcodes 4 - 7 */
312 for (a = 4; a < 8; a++) {
313 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
317 case BUS_TYPE_ICH7_SPI:
318 case BUS_TYPE_VIA_SPI:
319 REGWRITE16(ICH7_REG_PREOP, preop);
320 REGWRITE16(ICH7_REG_OPTYPE, optype);
321 REGWRITE32(ICH7_REG_OPMENU, opmenu[0]);
322 REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]);
324 case BUS_TYPE_ICH9_SPI:
325 REGWRITE16(ICH9_REG_PREOP, preop);
326 REGWRITE16(ICH9_REG_OPTYPE, optype);
327 REGWRITE32(ICH9_REG_OPMENU, opmenu[0]);
328 REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]);
331 printf_debug("%s: unsupported chipset\n", __FUNCTION__);
338 /* This function generates OPCODES from or programs OPCODES to ICH according to
339 * the chipset's SPI configuration lock.
341 * It should be called before ICH sends any spi command.
343 int ich_init_opcodes()
346 OPCODES *curopcodes_done;
352 printf_debug("Generating OPCODES... ");
353 curopcodes_done = &O_EXISTING;
354 rc = generate_opcodes(curopcodes_done);
356 printf_debug("Programming OPCODES... ");
357 curopcodes_done = &O_ST_M25P;
358 rc = program_opcodes(curopcodes_done);
363 printf_debug("failed\n");
366 curopcodes = curopcodes_done;
367 printf_debug("done\n");
372 static int ich7_run_opcode(OPCODE op, uint32_t offset,
373 uint8_t datalength, uint8_t * data, int maxdata)
383 /* Is it a write command? */
384 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
385 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
389 /* Programm Offset in Flash into FADDR */
390 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
392 /* Program data into FDATA0 to N */
393 if (write_cmd && (datalength != 0)) {
395 for (a = 0; a < datalength; a++) {
400 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
403 REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)),
407 if (((a - 1) % 4) != 3) {
408 REGWRITE32(ICH7_REG_SPID0 +
409 ((a - 1) - ((a - 1) % 4)), temp32);
416 /* clear error status registers */
417 temp16 |= (SPIS_CDS + SPIS_FCERR);
418 REGWRITE16(ICH7_REG_SPIS, temp16);
423 if (datalength != 0) {
425 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
429 opmenu = REGREAD32(ICH7_REG_OPMENU);
430 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
432 for (opcode_index=0; opcode_index<8; opcode_index++) {
433 if((opmenu & 0xff) == op.opcode) {
438 if (opcode_index == 8) {
439 printf_debug("Opcode %x not found.\n", op.opcode);
442 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
445 if (op.atomic != 0) {
446 /* Select atomic command */
448 /* Select prefix opcode */
449 if ((op.atomic - 1) == 1) {
450 /*Select prefix opcode 2 */
459 REGWRITE16(ICH7_REG_SPIC, temp16);
461 /* wait for cycle complete */
462 timeout = 1000 * 60; // 60s is a looong timeout.
463 while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
467 printf_debug("timeout\n");
470 if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) {
471 printf_debug("Transaction error!\n");
475 if ((!write_cmd) && (datalength != 0)) {
476 for (a = 0; a < datalength; a++) {
478 temp32 = REGREAD32(ICH7_REG_SPID0 + (a));
482 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
490 static int ich9_run_opcode(OPCODE op, uint32_t offset,
491 uint8_t datalength, uint8_t * data)
500 /* Is it a write command? */
501 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
502 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
506 /* Programm Offset in Flash into FADDR */
507 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
509 /* Program data into FDATA0 to N */
510 if (write_cmd && (datalength != 0)) {
512 for (a = 0; a < datalength; a++) {
517 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
520 REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)),
524 if (((a - 1) % 4) != 3) {
525 REGWRITE32(ICH9_REG_FDATA0 +
526 ((a - 1) - ((a - 1) % 4)), temp32);
531 /* Assemble SSFS + SSFC */
534 /* clear error status registers */
535 temp32 |= (SSFS_CDS + SSFS_FCERR);
537 temp32 |= SSFC_SCF_20MHZ;
539 if (datalength != 0) {
542 datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8);
547 opmenu = REGREAD32(ICH9_REG_OPMENU);
548 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
550 for (opcode_index=0; opcode_index<8; opcode_index++) {
551 if((opmenu & 0xff) == op.opcode) {
556 if (opcode_index == 8) {
557 printf_debug("Opcode %x not found.\n", op.opcode);
560 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
563 if (op.atomic != 0) {
564 /* Select atomic command */
566 /* Selct prefix opcode */
567 if ((op.atomic - 1) == 1) {
568 /*Select prefix opcode 2 */
577 REGWRITE32(ICH9_REG_SSFS, temp32);
579 /*wait for cycle complete */
580 timeout = 1000 * 60; // 60s is a looong timeout.
581 while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
585 printf_debug("timeout\n");
588 if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) {
589 printf_debug("Transaction error!\n");
593 if ((!write_cmd) && (datalength != 0)) {
594 for (a = 0; a < datalength; a++) {
596 temp32 = REGREAD32(ICH9_REG_FDATA0 + (a));
600 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
608 static int run_opcode(OPCODE op, uint32_t offset,
609 uint8_t datalength, uint8_t * data)
612 case BUS_TYPE_VIA_SPI:
613 return ich7_run_opcode(op, offset, datalength, data, 16);
614 case BUS_TYPE_ICH7_SPI:
615 return ich7_run_opcode(op, offset, datalength, data, 64);
616 case BUS_TYPE_ICH9_SPI:
617 return ich9_run_opcode(op, offset, datalength, data);
619 printf_debug("%s: unsupported chipset\n", __FUNCTION__);
622 /* If we ever get here, something really weird happened */
626 static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset,
629 int page_size = flash->page_size;
630 uint32_t remaining = flash->page_size;
633 printf_debug("ich_spi_read_page: offset=%d, number=%d, buf=%p\n",
634 offset, page_size, buf);
636 for (a = 0; a < page_size; a += maxdata) {
637 if (remaining < maxdata) {
639 if (spi_nbyte_read(offset + (page_size - remaining),
640 &buf[page_size - remaining], remaining)) {
641 printf_debug("Error reading");
646 if (spi_nbyte_read(offset + (page_size - remaining),
647 &buf[page_size - remaining], maxdata)) {
648 printf_debug("Error reading");
651 remaining -= maxdata;
658 static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
659 int offset, int maxdata)
661 int page_size = flash->page_size;
662 uint32_t remaining = page_size;
665 printf_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n",
666 offset, page_size, bytes);
668 for (a = 0; a < page_size; a += maxdata) {
669 if (remaining < maxdata) {
671 (curopcodes->opcode[0],
672 offset + (page_size - remaining), remaining,
673 &bytes[page_size - remaining]) != 0) {
674 printf_debug("Error writing");
680 (curopcodes->opcode[0],
681 offset + (page_size - remaining), maxdata,
682 &bytes[page_size - remaining]) != 0) {
683 printf_debug("Error writing");
686 remaining -= maxdata;
693 int ich_spi_read(struct flashchip *flash, uint8_t * buf)
696 int total_size = flash->total_size * 1024;
697 int page_size = flash->page_size;
700 if (flashbus == BUS_TYPE_VIA_SPI) {
704 for (i = 0; (i < total_size / page_size) && (rc == 0); i++) {
705 rc = ich_spi_read_page(flash, (void *)(buf + i * page_size),
706 i * page_size, maxdata);
712 int ich_spi_write(struct flashchip *flash, uint8_t * buf)
715 int total_size = flash->total_size * 1024;
716 int page_size = flash->page_size;
717 int erase_size = 64 * 1024;
720 spi_disable_blockprotect();
722 printf("Programming page: \n");
724 for (i = 0; i < total_size / erase_size; i++) {
725 /* FIMXE: call the chip-specific spi_block_erase_XX instead.
726 * For this, we need to add a block erase function to
729 rc = spi_block_erase_d8(flash, i * erase_size);
731 printf("Error erasing block at 0x%x\n", i);
735 if (flashbus == BUS_TYPE_VIA_SPI)
738 for (j = 0; j < erase_size / page_size; j++) {
739 ich_spi_write_page(flash,
740 (void *)(buf + (i * erase_size) + (j * page_size)),
741 (i * erase_size) + (j * page_size), maxdata);
750 int ich_spi_command(unsigned int writecnt, unsigned int readcnt,
751 const unsigned char *writearr, unsigned char *readarr)
754 int opcode_index = -1;
755 const unsigned char cmd = *writearr;
761 /* find cmd in opcodes-table */
762 for (a = 0; a < 8; a++) {
763 if ((curopcodes->opcode[a]).opcode == cmd) {
769 /* unknown / not programmed command */
770 if (opcode_index == -1) {
771 printf_debug("Invalid OPCODE 0x%02x\n", cmd);
775 opcode = &(curopcodes->opcode[opcode_index]);
777 /* if opcode-type requires an address */
778 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
779 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
780 addr = (writearr[1] << 16) |
781 (writearr[2] << 8) | (writearr[3] << 0);
784 /* translate read/write array/count */
785 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
786 data = (uint8_t *) (writearr + 1);
787 count = writecnt - 1;
788 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
789 data = (uint8_t *) (writearr + 4);
790 count = writecnt - 4;
792 data = (uint8_t *) readarr;
796 if (run_opcode(*opcode, addr, count, data) != 0) {
797 printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode);