2 * This file is part of the flashrom project.
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
7 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 * This module is designed for supporting the devices
30 * ST M25P32 already tested
32 * AT 25DF321 already tested
44 /* ICH9 controller register definition */
45 #define ICH9_REG_FADDR 0x08 /* 32 Bits */
46 #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
48 #define ICH9_REG_SSFS 0x90 /* 08 Bits */
49 #define SSFS_SCIP 0x00000001
50 #define SSFS_CDS 0x00000004
51 #define SSFS_FCERR 0x00000008
52 #define SSFS_AEL 0x00000010
54 #define ICH9_REG_SSFC 0x91 /* 24 Bits */
55 #define SSFC_SCGO 0x00000200
56 #define SSFC_ACS 0x00000400
57 #define SSFC_SPOP 0x00000800
58 #define SSFC_COP 0x00001000
59 #define SSFC_DBC 0x00010000
60 #define SSFC_DS 0x00400000
61 #define SSFC_SME 0x00800000
62 #define SSFC_SCF 0x01000000
63 #define SSFC_SCF_20MHZ 0x00000000
64 #define SSFC_SCF_33MHZ 0x01000000
66 #define ICH9_REG_PREOP 0x94 /* 16 Bits */
67 #define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
68 #define ICH9_REG_OPMENU 0x98 /* 64 Bits */
71 #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
72 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
73 #define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
74 #define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
77 #define ICH7_REG_SPIS 0x00 /* 16 Bits */
78 #define SPIS_SCIP 0x00000001
79 #define SPIS_CDS 0x00000004
80 #define SPIS_FCERR 0x00000008
82 /* VIA SPI is compatible with ICH7, but maxdata
83 to transfer is 16 bytes.
85 DATA byte count on ICH7 is 8:13, on VIA 8:11
87 bit 12 is port select CS0 CS1
88 bit 13 is FAST READ enable
89 bit 7 is used with fast read and one shot controls CS de-assert?
92 #define ICH7_REG_SPIC 0x02 /* 16 Bits */
93 #define SPIC_SCGO 0x0002
94 #define SPIC_ACS 0x0004
95 #define SPIC_SPOP 0x0008
96 #define SPIC_DS 0x4000
98 #define ICH7_REG_SPIA 0x04 /* 32 Bits */
99 #define ICH7_REG_SPID0 0x08 /* 64 Bytes */
100 #define ICH7_REG_PREOP 0x54 /* 16 Bits */
101 #define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
102 #define ICH7_REG_OPMENU 0x58 /* 64 Bits */
104 typedef struct _OPCODE {
105 uint8_t opcode; //This commands spi opcode
106 uint8_t spi_type; //This commands spi type
107 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
110 /* Opcode definition:
111 * Preop 1: Write Enable
112 * Preop 2: Write Status register enable
114 * OP 0: Write address
117 * OP 3: Read Status register
119 * OP 5: Write Status register
120 * OP 6: chip private (read JDEC id)
123 typedef struct _OPCODES {
128 static OPCODES *curopcodes = NULL;
130 /* HW access functions */
131 static inline uint32_t REGREAD32(int X)
133 volatile uint32_t regval;
134 regval = *(volatile uint32_t *) ((uint8_t *) spibar + X);
138 static inline uint16_t REGREAD16(int X)
140 volatile uint16_t regval;
141 regval = *(volatile uint16_t *) ((uint8_t *) spibar + X);
145 #define REGWRITE32(X,Y) (*(uint32_t *)((uint8_t *)spibar+X)=Y)
146 #define REGWRITE16(X,Y) (*(uint16_t *)((uint8_t *)spibar+X)=Y)
147 #define REGWRITE8(X,Y) (*(uint8_t *)((uint8_t *)spibar+X)=Y)
149 /* Common SPI functions */
150 static int program_opcodes(OPCODES * op);
151 static int run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
152 uint8_t datalength, uint8_t * data);
153 static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf,
154 int offset, int maxdata);
155 static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
156 int offset, int maxdata);
157 static int ich_spi_erase_block(struct flashchip *flash, int offset);
159 OPCODES O_ST_M25P = {
164 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Write Byte
165 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
166 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 1}, // Erase Sector
167 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
168 {JEDEC_RES, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Resume Deep Power-Down
169 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Write Status Register
170 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
171 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 1}, // Bulk erase
175 int program_opcodes(OPCODES * op)
178 uint16_t preop, optype;
181 /* Program Prefix Opcodes */
183 /* 0:7 Prefix Opcode 1 */
184 preop = (op->preop[0]);
185 /* 8:16 Prefix Opcode 2 */
186 preop |= ((uint16_t) op->preop[1]) << 8;
188 /* Program Opcode Types 0 - 7 */
190 for (a = 0; a < 8; a++) {
191 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
194 /* Program Allowable Opcodes 0 - 3 */
196 for (a = 0; a < 4; a++) {
197 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
200 /*Program Allowable Opcodes 4 - 7 */
202 for (a = 4; a < 8; a++) {
203 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
207 case BUS_TYPE_ICH7_SPI:
208 case BUS_TYPE_VIA_SPI:
209 REGWRITE16(ICH7_REG_PREOP, preop);
210 REGWRITE16(ICH7_REG_OPTYPE, optype);
211 REGWRITE32(ICH7_REG_OPMENU, opmenu[0]);
212 REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]);
214 case BUS_TYPE_ICH9_SPI:
215 REGWRITE16(ICH9_REG_PREOP, preop);
216 REGWRITE16(ICH9_REG_OPTYPE, optype);
217 REGWRITE32(ICH9_REG_OPMENU, opmenu[0]);
218 REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]);
221 printf_debug("%s: unsupported chipset\n", __FUNCTION__);
228 static int ich7_run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
229 uint8_t datalength, uint8_t * data, int maxdata)
237 /* Is it a write command? */
238 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
239 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
243 /* Programm Offset in Flash into FADDR */
244 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
246 /* Program data into FDATA0 to N */
247 if (write_cmd && (datalength != 0)) {
249 for (a = 0; a < datalength; a++) {
254 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
257 REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)),
261 if (((a - 1) % 4) != 3) {
262 REGWRITE32(ICH7_REG_SPID0 +
263 ((a - 1) - ((a - 1) % 4)), temp32);
270 /* clear error status registers */
271 temp16 |= (SPIS_CDS + SPIS_FCERR);
272 REGWRITE16(ICH7_REG_SPIS, temp16);
277 if (datalength != 0) {
279 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
283 temp16 |= ((uint16_t) (nr & 0x07)) << 4;
286 if (op.atomic != 0) {
287 /* Select atomic command */
289 /* Selct prefix opcode */
290 if ((op.atomic - 1) == 1) {
291 /*Select prefix opcode 2 */
300 REGWRITE16(ICH7_REG_SPIC, temp16);
302 /* wait for cycle complete */
303 timeout = 1000 * 60; // 60s is a looong timeout.
304 while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
308 printf_debug("timeout\n");
311 if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) {
312 printf_debug("Transaction error!\n");
316 if ((!write_cmd) && (datalength != 0)) {
317 for (a = 0; a < datalength; a++) {
319 temp32 = REGREAD32(ICH7_REG_SPID0 + (a));
323 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
332 static int ich9_run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
333 uint8_t datalength, uint8_t * data)
340 /* Is it a write command? */
341 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
342 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
346 /* Programm Offset in Flash into FADDR */
347 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */
349 /* Program data into FDATA0 to N */
350 if (write_cmd && (datalength != 0)) {
352 for (a = 0; a < datalength; a++) {
357 temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8);
360 REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)),
364 if (((a - 1) % 4) != 3) {
365 REGWRITE32(ICH9_REG_FDATA0 +
366 ((a - 1) - ((a - 1) % 4)), temp32);
371 /* Assemble SSFS + SSFC */
374 /* clear error status registers */
375 temp32 |= (SSFS_CDS + SSFS_FCERR);
377 temp32 |= SSFC_SCF_20MHZ;
379 if (datalength != 0) {
382 datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8);
387 temp32 |= ((uint32_t) (nr & 0x07)) << (8 + 4);
390 if (op.atomic != 0) {
391 /* Select atomic command */
393 /* Selct prefix opcode */
394 if ((op.atomic - 1) == 1) {
395 /*Select prefix opcode 2 */
404 REGWRITE32(ICH9_REG_SSFS, temp32);
406 /*wait for cycle complete */
407 timeout = 1000 * 60; // 60s is a looong timeout.
408 while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
412 printf_debug("timeout\n");
415 if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) {
416 printf_debug("Transaction error!\n");
420 if ((!write_cmd) && (datalength != 0)) {
421 for (a = 0; a < datalength; a++) {
423 temp32 = REGREAD32(ICH9_REG_FDATA0 + (a));
427 (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8)))
435 static int run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
436 uint8_t datalength, uint8_t * data)
439 case BUS_TYPE_VIA_SPI:
440 return ich7_run_opcode(nr, op, offset, datalength, data, 16);
441 case BUS_TYPE_ICH7_SPI:
442 return ich7_run_opcode(nr, op, offset, datalength, data, 64);
443 case BUS_TYPE_ICH9_SPI:
444 return ich9_run_opcode(nr, op, offset, datalength, data);
446 printf_debug("%s: unsupported chipset\n", __FUNCTION__);
449 /* If we ever get here, something really weird happened */
453 static int ich_spi_erase_block(struct flashchip *flash, int offset)
455 printf_debug("ich_spi_erase_block: offset=%d, sectors=%d\n",
458 if (run_opcode(2, curopcodes->opcode[2], offset, 0, NULL) != 0) {
459 printf_debug("Error erasing sector at 0x%x", offset);
463 printf("DONE BLOCK 0x%x\n", offset);
468 static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset, int maxdata)
470 int page_size = flash->page_size;
471 uint32_t remaining = flash->page_size;
474 printf_debug("ich_spi_read_page: offset=%d, number=%d, buf=%p\n",
475 offset, page_size, buf);
477 for (a = 0; a < page_size; a += maxdata) {
478 if (remaining < maxdata) {
481 (1, curopcodes->opcode[1],
482 offset + (page_size - remaining), remaining,
483 &buf[page_size - remaining]) != 0) {
484 printf_debug("Error reading");
490 (1, curopcodes->opcode[1],
491 offset + (page_size - remaining), maxdata,
492 &buf[page_size - remaining]) != 0) {
493 printf_debug("Error reading");
496 remaining -= maxdata;
503 static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
504 int offset, int maxdata)
506 int page_size = flash->page_size;
507 uint32_t remaining = page_size;
510 printf_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n",
511 offset, page_size, bytes);
513 for (a = 0; a < page_size; a += maxdata) {
514 if (remaining < maxdata) {
516 (0, curopcodes->opcode[0],
517 offset + (page_size - remaining), remaining,
518 &bytes[page_size - remaining]) != 0) {
519 printf_debug("Error writing");
525 (0, curopcodes->opcode[0],
526 offset + (page_size - remaining), maxdata,
527 &bytes[page_size - remaining]) != 0) {
528 printf_debug("Error writing");
531 remaining -= maxdata;
538 int ich_spi_read(struct flashchip *flash, uint8_t * buf)
541 int total_size = flash->total_size * 1024;
542 int page_size = flash->page_size;
545 if (flashbus == BUS_TYPE_VIA_SPI) {
549 for (i = 0; (i < total_size / page_size) && (rc == 0); i++) {
550 rc = ich_spi_read_page(flash, (void *)(buf + i * page_size),
551 i * page_size, maxdata);
557 int ich_spi_write(struct flashchip *flash, uint8_t * buf)
560 int total_size = flash->total_size * 1024;
561 int page_size = flash->page_size;
562 int erase_size = 64 * 1024;
565 spi_disable_blockprotect();
567 printf("Programming page: \n");
569 for (i = 0; i < total_size / erase_size; i++) {
570 rc = ich_spi_erase_block(flash, i * erase_size);
572 printf("Error erasing block at 0x%x\n", i);
576 if (flashbus == BUS_TYPE_VIA_SPI)
579 for (j = 0; j < erase_size / page_size; j++) {
580 ich_spi_write_page(flash, (void *)(buf + (i * erase_size) + (j * page_size)),
581 (i * erase_size) + (j * page_size), maxdata);
590 int ich_spi_command(unsigned int writecnt, unsigned int readcnt,
591 const unsigned char *writearr, unsigned char *readarr)
594 int opcode_index = -1;
595 const unsigned char cmd = *writearr;
601 /* program opcodes if not already done */
602 if (curopcodes == NULL) {
603 printf_debug("Programming OPCODES... ");
604 curopcodes = &O_ST_M25P;
605 program_opcodes(curopcodes);
606 printf_debug("done\n");
609 /* find cmd in opcodes-table */
610 for (a = 0; a < 8; a++) {
611 if ((curopcodes->opcode[a]).opcode == cmd) {
617 /* unknown / not programmed command */
618 if (opcode_index == -1) {
619 printf_debug("Invalid OPCODE 0x%02x\n", cmd);
623 opcode = &(curopcodes->opcode[opcode_index]);
625 /* if opcode-type requires an address */
626 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
627 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
628 addr = (writearr[1] << 16) |
629 (writearr[2] << 8) | (writearr[3] << 0);
632 /* translate read/write array/count */
633 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
634 data = (uint8_t *) (writearr + 1);
635 count = writecnt - 1;
636 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
637 data = (uint8_t *) (writearr + 4);
638 count = writecnt - 4;
640 data = (uint8_t *) readarr;
644 if (run_opcode(opcode_index, *opcode, addr, count, data) != 0) {
645 printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode);