2 * flash rom utility: enable flash writes
4 * Copyright (C) 2000-2004 ???
5 * Copyright (C) 2005 coresystems GmbH <stepan@openbios.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
22 // We keep this for the others.
23 static struct pci_access *pacc;
25 static int enable_flash_sis630(struct pci_dev *dev, char *name)
29 /* get io privilege access PCI configuration space */
31 perror("Can not set io priviliage");
35 /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630 */
36 outl(0x80000840, 0x0cf8);
37 b = inb(0x0cfc) | 0x0b;
39 /* Flash write enable on SiS 540/630 */
40 outl(0x80000845, 0x0cf8);
41 b = inb(0x0cfd) | 0x40;
44 /* The same thing on SiS 950 SuperIO side */
50 if (inb(0x2f) != 0x87) {
55 if (inb(0x4f) != 0x87) {
56 printf("Can not access SiS 950\n");
68 printf("2f is %#x\n", inb(0x2f));
79 static int enable_flash_e7500(struct pci_dev *dev, char *name)
81 /* register 4e.b gets or'ed with one */
83 /* if it fails, it fails. There are so many variations of broken mobos
84 * that it is hard to argue that we should quit at this point.
87 old = pci_read_byte(dev, 0x4e);
94 pci_write_byte(dev, 0x4e, new);
96 if (pci_read_byte(dev, 0x4e) != new) {
97 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
105 ICH4_BIOS_CNTL = 0x4e,
106 /* see page 375 of "Intel ICH7 External Design Specification"
107 * http://download.intel.com/design/chipsets/datashts/30701302.pdf */
108 ICH7_BIOS_CNTL = 0xdc,
110 static int enable_flash_ich(struct pci_dev *dev, char *name, int bios_cntl)
112 /* register 4e.b gets or'ed with one */
114 /* if it fails, it fails. There are so many variations of broken mobos
115 * that it is hard to argue that we should quit at this point.
118 old = pci_read_byte(dev, bios_cntl);
125 pci_write_byte(dev, bios_cntl, new);
127 if (pci_read_byte(dev, bios_cntl) != new) {
128 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
129 bios_cntl, new, name);
135 static int enable_flash_ich4(struct pci_dev *dev, char *name)
137 return enable_flash_ich(dev, name, ICH4_BIOS_CNTL);
140 static int enable_flash_ich7(struct pci_dev *dev, char *name)
142 return enable_flash_ich(dev, name, ICH7_BIOS_CNTL);
145 static int enable_flash_vt8235(struct pci_dev *dev, char *name)
147 uint8_t old, new, val;
151 /* get io privilege access PCI configuration space */
153 perror("Can not set io priviliage");
157 old = pci_read_byte(dev, 0x40);
164 ok = pci_write_byte(dev, 0x40, new);
166 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
170 /* enable GPIO15 which is connected to write protect. */
171 base = ((pci_read_byte(dev, 0x88) & 0x80) | pci_read_byte(dev, 0x89) << 8);
172 val = inb(base + 0x4d);
174 outb(val, base + 0x4d);
183 static int enable_flash_vt8231(struct pci_dev *dev, char *name)
187 val = pci_read_byte(dev, 0x40);
189 pci_write_byte(dev, 0x40, val);
191 if (pci_read_byte(dev, 0x40) != val) {
192 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
199 static int enable_flash_cs5530(struct pci_dev *dev, char *name)
203 pci_write_byte(dev, 0x52, 0xee);
205 new = pci_read_byte(dev, 0x52);
208 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
213 new = pci_read_byte(dev, 0x5b) | 0x20;
214 pci_write_byte(dev, 0x5b, new);
220 static int enable_flash_sc1100(struct pci_dev *dev, char *name)
224 pci_write_byte(dev, 0x52, 0xee);
226 new = pci_read_byte(dev, 0x52);
229 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
236 static int enable_flash_sis5595(struct pci_dev *dev, char *name)
240 new = pci_read_byte(dev, 0x45);
247 pci_write_byte(dev, 0x45, new);
249 newer = pci_read_byte(dev, 0x45);
251 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
253 printf("Stuck at 0x%x\n", newer);
259 static int enable_flash_amd8111(struct pci_dev *dev, char *name)
261 /* register 4e.b gets or'ed with one */
263 /* if it fails, it fails. There are so many variations of broken mobos
264 * that it is hard to argue that we should quit at this point.
267 /* enable decoding at 0xffb00000 to 0xffffffff */
268 old = pci_read_byte(dev, 0x43);
271 pci_write_byte(dev, 0x43, new);
272 if (pci_read_byte(dev, 0x43) != new) {
273 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
278 old = pci_read_byte(dev, 0x40);
282 pci_write_byte(dev, 0x40, new);
284 if (pci_read_byte(dev, 0x40) != new) {
285 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
293 static int enable_flash_ck804(struct pci_dev *dev, char *name)
295 /* register 4e.b gets or'ed with one */
297 /* if it fails, it fails. There are so many variations of broken mobos
298 * that it is hard to argue that we should quit at this point.
301 //dump_pci_device(dev);
303 old = pci_read_byte(dev, 0x88);
306 pci_write_byte(dev, 0x88, new);
307 if (pci_read_byte(dev, 0x88) != new) {
308 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
313 old = pci_read_byte(dev, 0x6d);
317 pci_write_byte(dev, 0x6d, new);
319 if (pci_read_byte(dev, 0x6d) != new) {
320 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
327 static int enable_flash_sb400(struct pci_dev *dev, char *name)
332 struct pci_dev *smbusdev;
334 /* get io privilege access */
336 perror("Can not set io priviliage");
340 /* then look for the smbus device */
341 pci_filter_init((struct pci_access *) 0, &f);
345 for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
346 if (pci_filter_match(&f, smbusdev)) {
352 perror("smbus device not found. aborting\n");
356 // enable some smbus stuff
357 tmp=pci_read_byte(smbusdev, 0x79);
359 pci_write_byte(smbusdev, 0x79, tmp);
361 // change southbridge
362 tmp=pci_read_byte(dev, 0x48);
364 pci_write_byte(dev, 0x48, tmp);
366 // now become a bit silly.
378 typedef struct penable {
379 unsigned short vendor, device;
381 int (*doit) (struct pci_dev * dev, char *name);
384 static FLASH_ENABLE enables[] = {
385 {0x1039, 0x0630, "sis630", enable_flash_sis630},
386 {0x8086, 0x2480, "E7500", enable_flash_e7500},
387 {0x8086, 0x24c0, "ICH4", enable_flash_ich4},
388 {0x8086, 0x24cc, "ICH4-M", enable_flash_ich4},
389 {0x8086, 0x24d0, "ICH5", enable_flash_ich4},
390 {0x8086, 0x27b8, "ICH7", enable_flash_ich7},
391 {0x1106, 0x8231, "VT8231", enable_flash_vt8231},
392 {0x1106, 0x3177, "VT8235", enable_flash_vt8235},
393 {0x1078, 0x0100, "CS5530", enable_flash_cs5530},
394 {0x100b, 0x0510, "SC1100", enable_flash_sc1100},
395 {0x1039, 0x0008, "SIS5595", enable_flash_sis5595},
396 {0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
397 // this fallthrough looks broken.
398 {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, // LPC
399 {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, // Pro
400 {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, // Slave, should not be here, to fix known bug for A01.
401 {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, // ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80)
404 static int mbenable_island_aruma(void)
406 #define EFIR 0x2e /* Extended function index register, either 0x2e or 0x4e */
407 #define EFDR EFIR + 1 /* Extended function data register, one plus the index reg. */
410 /* Disable the flash write protect. The flash write protect is
411 * connected to the WinBond w83627hf GPIO 24.
414 /* get io privilege access winbond config space */
416 perror("Can not set io priviliage");
420 printf("Disabling mainboard flash write protection.\n");
422 outb(0x87, EFIR); // sequence to unlock extended functions
425 outb(0x20, EFIR); // SIO device ID register
427 printf_debug("W83627HF device ID = 0x%x\n",b);
430 perror("Incorrect device ID, aborting write protect disable\n");
434 outb(0x2b, EFIR); // GPIO multiplexed pin reg.
435 b = inb(EFDR) | 0x10;
437 outb(b, EFDR); // select GPIO 24 instead of WDTO
439 outb(0x7, EFIR); // logical device select
440 outb(0x8, EFDR); // point to device 8, GPIO port 2
442 outb(0x30, EFIR); // logic device activation control
443 outb(0x1, EFDR); // activate
445 outb(0xf0, EFIR); // GPIO 20-27 I/O selection register
446 b = inb(EFDR) & ~0x10;
448 outb(b, EFDR); // set GPIO 24 as an output
450 outb(0xf1, EFIR); // GPIO 20-27 data register
451 b = inb(EFDR) | 0x10;
453 outb(b, EFDR); // set GPIO 24
455 outb(0xaa, EFIR); // command to exit extended functions
460 typedef struct mbenable {
465 static MAINBOARD_ENABLE mbenables[] = {
466 { "ISLAND", "ARUMA", mbenable_island_aruma },
469 int enable_flash_write()
472 struct pci_dev *dev = 0;
473 FLASH_ENABLE *enable = 0;
475 pacc = pci_alloc(); /* Get the pci_access structure */
476 /* Set all options you want -- here we stick with the defaults */
477 pci_init(pacc); /* Initialize the PCI library */
478 pci_scan_bus(pacc); /* We want to get the list of devices */
481 /* First look whether we have to do something for this
484 for (i = 0; i < sizeof(mbenables) / sizeof(mbenables[0]); i++) {
485 if(lb_vendor && !strcmp(mbenables[i].vendor, lb_vendor) &&
486 lb_part && !strcmp(mbenables[i].part, lb_part)) {
492 /* now let's try to find the chipset we have ... */
493 for (i = 0; i < sizeof(enables) / sizeof(enables[0]) && (!dev);
497 /* the first param is unused. */
498 pci_filter_init((struct pci_access *) 0, &f);
499 f.vendor = enables[i].vendor;
500 f.device = enables[i].device;
501 for (z = pacc->devices; z; z = z->next)
502 if (pci_filter_match(&f, z)) {
503 enable = &enables[i];
508 /* now do the deed. */
510 printf("Enabling flash write on %s...", enable->name);
511 if (enable->doit(dev, enable->name) == 0)