2 * flash rom utility: enable flash writes
4 * Copyright (C) 2000-2004 ???
5 * Copyright (C) 2005 coresystems GmbH <stepan@openbios.org>
6 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
19 #if defined (__sun) && (defined(__i386) || defined(__amd64))
21 #include <sys/sysi86.h>
23 #include <asm/sunddi.h>
29 // We keep this for the others.
30 static struct pci_access *pacc;
32 static int enable_flash_sis630(struct pci_dev *dev, char *name)
36 /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630 */
37 outl(0x80000840, 0x0cf8);
38 b = inb(0x0cfc) | 0x0b;
40 /* Flash write enable on SiS 540/630 */
41 outl(0x80000845, 0x0cf8);
42 b = inb(0x0cfd) | 0x40;
45 /* The same thing on SiS 950 SuperIO side */
51 if (inb(0x2f) != 0x87) {
56 if (inb(0x4f) != 0x87) {
57 printf("Can not access SiS 950\n");
69 printf("2f is %#x\n", inb(0x2f));
81 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
82 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
83 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
84 * - Order Number: 290562-001
86 static int enable_flash_piix4(struct pci_dev *dev, char *name)
89 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
91 old = pci_read_word(dev, xbcs);
93 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
94 FFF00000-FFF7FFFF are forwarded to ISA).
95 Set bit 7: Extended BIOS Enable (PCI master accesses to
96 FFF80000-FFFDFFFF are forwarded to ISA).
97 Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
98 the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
99 of 1 Mbyte, or the aliases at the top of 4 Gbyte
100 (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
101 Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
102 Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). */
108 pci_write_word(dev, xbcs, new);
110 if (pci_read_word(dev, xbcs) != new) {
111 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
117 static int enable_flash_ich(struct pci_dev *dev, char *name, int bios_cntl)
119 /* register 4e.b gets or'ed with one */
122 /* if it fails, it fails. There are so many variations of broken mobos
123 * that it is hard to argue that we should quit at this point.
126 /* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
127 * just treating it as 8 bit wide seems to work fine in practice.
130 /* see ie. page 375 of "Intel ICH7 External Design Specification"
131 * http://download.intel.com/design/chipsets/datashts/30701302.pdf
134 old = pci_read_byte(dev, bios_cntl);
141 pci_write_byte(dev, bios_cntl, new);
143 if (pci_read_byte(dev, bios_cntl) != new) {
144 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
145 bios_cntl, new, name);
151 static int enable_flash_ich_4e(struct pci_dev *dev, char *name)
153 return enable_flash_ich(dev, name, 0x4e);
156 static int enable_flash_ich_dc(struct pci_dev *dev, char *name)
158 return enable_flash_ich(dev, name, 0xdc);
161 static int enable_flash_vt823x(struct pci_dev *dev, char *name)
166 /* ROM Write enable */
167 val = pci_read_byte(dev, 0x40);
169 pci_write_byte(dev, 0x40, val);
171 if (pci_read_byte(dev, 0x40) != val) {
172 printf("Warning: Failed to enable ROM Write on %s\n", name);
176 if (dev->device_id == 0x3177) { /* VT8235 */
177 if (!iopl(3)) { /* enable full IO access */
180 /* GPIO12-15 -> output */
181 val = pci_read_byte(dev, 0xE4);
183 pci_write_byte(dev, 0xE4, val);
185 /* Get Power Management IO address. */
186 base = pci_read_word(dev, 0x88) & 0xFF80;
188 /* enable GPIO15 which is connected to write protect. */
189 val = inb(base + 0x4d);
191 outb(val, base + 0x4d);
193 val = inb(base + 0x4E);
195 outb(val, base + 0x4E);
197 printf("Warning; Failed to disable Write Protect"
198 " on %s (iopl failed)\n", name);
206 static int enable_flash_cs5530(struct pci_dev *dev, char *name)
210 pci_write_byte(dev, 0x52, 0xee);
212 new = pci_read_byte(dev, 0x52);
215 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
220 new = pci_read_byte(dev, 0x5b) | 0x20;
221 pci_write_byte(dev, 0x5b, new);
227 static int enable_flash_sc1100(struct pci_dev *dev, char *name)
231 pci_write_byte(dev, 0x52, 0xee);
233 new = pci_read_byte(dev, 0x52);
236 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
243 static int enable_flash_sis5595(struct pci_dev *dev, char *name)
247 new = pci_read_byte(dev, 0x45);
254 pci_write_byte(dev, 0x45, new);
256 newer = pci_read_byte(dev, 0x45);
258 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
260 printf("Stuck at 0x%x\n", newer);
266 static int enable_flash_amd8111(struct pci_dev *dev, char *name)
268 /* register 4e.b gets or'ed with one */
270 /* if it fails, it fails. There are so many variations of broken mobos
271 * that it is hard to argue that we should quit at this point.
274 /* enable decoding at 0xffb00000 to 0xffffffff */
275 old = pci_read_byte(dev, 0x43);
278 pci_write_byte(dev, 0x43, new);
279 if (pci_read_byte(dev, 0x43) != new) {
280 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
285 old = pci_read_byte(dev, 0x40);
289 pci_write_byte(dev, 0x40, new);
291 if (pci_read_byte(dev, 0x40) != new) {
292 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
300 static int enable_flash_ck804(struct pci_dev *dev, char *name)
302 /* register 4e.b gets or'ed with one */
304 /* if it fails, it fails. There are so many variations of broken mobos
305 * that it is hard to argue that we should quit at this point.
308 //dump_pci_device(dev);
310 old = pci_read_byte(dev, 0x88);
313 pci_write_byte(dev, 0x88, new);
314 if (pci_read_byte(dev, 0x88) != new) {
315 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
320 old = pci_read_byte(dev, 0x6d);
324 pci_write_byte(dev, 0x6d, new);
326 if (pci_read_byte(dev, 0x6d) != new) {
327 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
334 static int enable_flash_sb400(struct pci_dev *dev, char *name)
339 struct pci_dev *smbusdev;
341 /* then look for the smbus device */
342 pci_filter_init((struct pci_access *) 0, &f);
346 for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
347 if (pci_filter_match(&f, smbusdev)) {
353 perror("smbus device not found. aborting\n");
357 // enable some smbus stuff
358 tmp=pci_read_byte(smbusdev, 0x79);
360 pci_write_byte(smbusdev, 0x79, tmp);
362 // change southbridge
363 tmp=pci_read_byte(dev, 0x48);
365 pci_write_byte(dev, 0x48, tmp);
367 // now become a bit silly.
380 static int enable_flash_mcp55(struct pci_dev *dev, char *name)
382 /* register 4e.b gets or'ed with one */
383 unsigned char old, new, byte;
386 /* if it fails, it fails. There are so many variations of broken mobos
387 * that it is hard to argue that we should quit at this point.
390 //dump_pci_device(dev);
392 /* Set the 4MB enable bit bit */
393 byte = pci_read_byte(dev, 0x88);
395 pci_write_byte(dev, 0x88, byte);
396 byte = pci_read_byte(dev, 0x8c);
398 pci_write_byte(dev, 0x8c, byte);
399 word = pci_read_word(dev, 0x90);
400 word |= 0x7fff; //15M
401 pci_write_word(dev, 0x90, word);
403 old = pci_read_byte(dev, 0x6d);
407 pci_write_byte(dev, 0x6d, new);
409 if (pci_read_byte(dev, 0x6d) != new) {
410 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
419 typedef struct penable {
420 unsigned short vendor, device;
422 int (*doit) (struct pci_dev * dev, char *name);
425 static FLASH_ENABLE enables[] = {
426 {0x1039, 0x0630, "SIS630", enable_flash_sis630},
427 {0x8086, 0x7110, "PIIX4/PIIX4E/PIIX4M", enable_flash_piix4},
428 {0x8086, 0x2410, "ICH", enable_flash_ich_4e},
429 {0x8086, 0x2420, "ICH0", enable_flash_ich_4e},
430 {0x8086, 0x2440, "ICH2", enable_flash_ich_4e},
431 {0x8086, 0x244c, "ICH2-M", enable_flash_ich_4e},
432 {0x8086, 0x2480, "ICH3-S", enable_flash_ich_4e},
433 {0x8086, 0x248c, "ICH3-M", enable_flash_ich_4e},
434 {0x8086, 0x24c0, "ICH4/ICH4-L", enable_flash_ich_4e},
435 {0x8086, 0x24cc, "ICH4-M", enable_flash_ich_4e},
436 {0x8086, 0x24d0, "ICH5/ICH5R", enable_flash_ich_4e},
437 {0x8086, 0x2640, "ICH6/ICH6R", enable_flash_ich_dc},
438 {0x8086, 0x2641, "ICH6-M", enable_flash_ich_dc},
439 {0x8086, 0x27b8, "ICH7/ICH7R", enable_flash_ich_dc},
440 {0x8086, 0x27b9, "ICH7M", enable_flash_ich_dc},
441 {0x8086, 0x27bd, "ICH7MDH", enable_flash_ich_dc},
442 {0x8086, 0x2810, "ICH8/ICH8R", enable_flash_ich_dc},
443 {0x8086, 0x2812, "ICH8DH", enable_flash_ich_dc},
444 {0x8086, 0x2814, "ICH8DO", enable_flash_ich_dc},
445 {0x1106, 0x8231, "VT8231", enable_flash_vt823x},
446 {0x1106, 0x3177, "VT8235", enable_flash_vt823x},
447 {0x1106, 0x3227, "VT8237", enable_flash_vt823x},
448 {0x1106, 0x0686, "VT82C686", enable_flash_amd8111},
449 {0x1078, 0x0100, "CS5530", enable_flash_cs5530},
450 {0x100b, 0x0510, "SC1100", enable_flash_sc1100},
451 {0x1039, 0x0008, "SIS5595", enable_flash_sis5595},
452 {0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
453 // this fallthrough looks broken.
454 {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, // LPC
455 {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, // Pro
456 {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, // Slave, should not be here, to fix known bug for A01.
458 {0x10de, 0x0260, "NVidia MCP51", enable_flash_ck804},
459 {0x10de, 0x0261, "NVidia MCP51", enable_flash_ck804},
460 {0x10de, 0x0262, "NVidia MCP51", enable_flash_ck804},
461 {0x10de, 0x0263, "NVidia MCP51", enable_flash_ck804},
463 {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, // Gigabyte m57sli-s4
464 {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, // LPC
465 {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, // Pro
467 {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, // ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80)
470 static int mbenable_island_aruma(void)
472 #define EFIR 0x2e /* Extended function index register, either 0x2e or 0x4e */
473 #define EFDR EFIR + 1 /* Extended function data register, one plus the index reg. */
476 /* Disable the flash write protect. The flash write protect is
477 * connected to the WinBond w83627hf GPIO 24.
480 printf("Disabling mainboard flash write protection.\n");
482 outb(0x87, EFIR); // sequence to unlock extended functions
485 outb(0x20, EFIR); // SIO device ID register
487 printf_debug("W83627HF device ID = 0x%x\n",b);
490 perror("Incorrect device ID, aborting write protect disable\n");
494 outb(0x2b, EFIR); // GPIO multiplexed pin reg.
495 b = inb(EFDR) | 0x10;
497 outb(b, EFDR); // select GPIO 24 instead of WDTO
499 outb(0x7, EFIR); // logical device select
500 outb(0x8, EFDR); // point to device 8, GPIO port 2
502 outb(0x30, EFIR); // logic device activation control
503 outb(0x1, EFDR); // activate
505 outb(0xf0, EFIR); // GPIO 20-27 I/O selection register
506 b = inb(EFDR) & ~0x10;
508 outb(b, EFDR); // set GPIO 24 as an output
510 outb(0xf1, EFIR); // GPIO 20-27 data register
511 b = inb(EFDR) | 0x10;
513 outb(b, EFDR); // set GPIO 24
515 outb(0xaa, EFIR); // command to exit extended functions
520 typedef struct mbenable {
525 static MAINBOARD_ENABLE mbenables[] = {
526 { "ISLAND", "ARUMA", mbenable_island_aruma },
529 int enable_flash_write()
532 struct pci_dev *dev = 0;
533 FLASH_ENABLE *enable = 0;
535 /* get io privilege access PCI configuration space */
536 #if defined (__sun) && (defined(__i386) || defined(__amd64))
537 if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0){
541 perror("Can not set io privilege");
546 /* Initialize PCI access */
547 pacc = pci_alloc(); /* Get the pci_access structure */
548 /* Set all options you want -- here we stick with the defaults */
549 pci_init(pacc); /* Initialize the PCI library */
550 pci_scan_bus(pacc); /* We want to get the list of devices */
553 /* First look whether we have to do something for this
556 for (i = 0; i < sizeof(mbenables) / sizeof(mbenables[0]); i++) {
557 if(lb_vendor && !strcmp(mbenables[i].vendor, lb_vendor) &&
558 lb_part && !strcmp(mbenables[i].part, lb_part)) {
564 /* now let's try to find the chipset we have ... */
565 for (i = 0; i < sizeof(enables) / sizeof(enables[0]) && (!dev);
569 /* the first param is unused. */
570 pci_filter_init((struct pci_access *) 0, &f);
571 f.vendor = enables[i].vendor;
572 f.device = enables[i].device;
573 for (z = pacc->devices; z; z = z->next)
574 if (pci_filter_match(&f, z)) {
575 enable = &enables[i];
581 printf("Warning: Unknown system. Flash detection "
582 "will most likely fail.\n");
586 /* now do the deed. */
587 printf("Enabling flash write on %s...", enable->name);
588 if (enable->doit(dev, enable->name) == 0)