2 * This file is part of the flashrom project.
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 #if defined(__GLIBC__)
33 #if (defined(__MACH__) && defined(__APPLE__))
37 #if defined(__FreeBSD__)
38 #include <machine/cpufunc.h>
41 #define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0)
42 #define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0)
43 #define OUTL(x, y) do { u_int tmp = (y); outl(tmp, (x)); } while (0)
44 #define INB(x) __extension__ ({ u_int tmp = (x); inb(tmp); })
45 #define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); })
46 #define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); })
48 #if defined(__DARWIN__)
49 #include <DirectIO/darwinio.h>
61 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
67 * With 32bit manufacture_id and model_id we can cover IDs up to
68 * (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's
69 * Identification code.
71 uint32_t manufacture_id;
78 * Indicate if flashrom has been tested with this flash chip and if
79 * everything worked correctly.
83 int (*probe) (struct flashchip *flash);
84 int (*erase) (struct flashchip *flash);
85 int (*write) (struct flashchip *flash, uint8_t *buf);
86 int (*read) (struct flashchip *flash, uint8_t *buf);
88 /* Some flash devices have an additional register space. */
89 volatile uint8_t *virtual_memory;
90 volatile uint8_t *virtual_registers;
93 #define TEST_UNTESTED 0
95 #define TEST_OK_PROBE (1<<0)
96 #define TEST_OK_READ (1<<1)
97 #define TEST_OK_ERASE (1<<2)
98 #define TEST_OK_WRITE (1<<3)
99 #define TEST_OK_PR (TEST_OK_PROBE|TEST_OK_READ)
100 #define TEST_OK_PREW (TEST_OK_PROBE|TEST_OK_READ|TEST_OK_ERASE|TEST_OK_WRITE)
101 #define TEST_OK_MASK 0x0f
103 #define TEST_BAD_PROBE (1<<4)
104 #define TEST_BAD_READ (1<<5)
105 #define TEST_BAD_ERASE (1<<6)
106 #define TEST_BAD_WRITE (1<<7)
107 #define TEST_BAD_PREW (TEST_BAD_PROBE|TEST_BAD_READ|TEST_BAD_ERASE|TEST_BAD_WRITE)
108 #define TEST_BAD_MASK 0xf0
110 extern struct flashchip flashchips[];
113 * Please keep this list sorted alphabetically by manufacturer. The first
114 * entry of each section should be the manufacturer ID, followed by the
115 * list of devices from that manufacturer (sorted by device IDs).
117 * All LPC/FWH parts (parallel flash) have 8-bit device IDs if there is no
119 * SPI parts have 16-bit device IDs if they support RDID.
122 #define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */
124 #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */
126 #define AMD_ID 0x01 /* AMD */
127 #define AM_29F002BT 0xB0
128 #define AM_29F002BB 0x34
129 #define AM_29F040B 0xA4
130 #define AM_29LV040B 0x4F
131 #define AM_29F016D 0xAD
133 #define AMIC_ID 0x7F37 /* AMIC */
134 #define AMIC_ID_NOPREFIX 0x37 /* AMIC */
135 #define AMIC_A25L40P 0x2013
136 #define AMIC_A29002B 0x0d
137 #define AMIC_A29002T 0x8c
138 #define AMIC_A29040B 0x86
139 #define AMIC_A49LF040A 0x9d
141 #define ASD_ID 0x25 /* ASD, not listed in JEP106W */
142 #define ASD_AE49F2008 0x52
144 #define ATMEL_ID 0x1F /* Atmel */
145 #define AT_25DF021 0x4300
146 #define AT_25DF041A 0x4401
147 #define AT_25DF081 0x4502
148 #define AT_25DF161 0x4602
149 #define AT_25DF321 0x4700 /* also 26DF321 */
150 #define AT_25DF321A 0x4701
151 #define AT_25DF641 0x4800
152 #define AT_25F512A 0x65 /* Needs special RDID. AT25F512A_RDID 15 1d */
153 #define AT_25F512B 0x6500
154 #define AT_25FS010 0x6601
155 #define AT_25FS040 0x6604
156 #define AT_26DF041 0x4400
157 #define AT_26DF081 0x4500 /* guessed, no datasheet available */
158 #define AT_26DF081A 0x4501
159 #define AT_26DF161 0x4600
160 #define AT_26DF161A 0x4601
161 #define AT_26DF321 0x4700 /* also 25DF321 */
162 #define AT_26F004 0x0400
163 #define AT_29C040A 0xA4
164 #define AT_29C020 0xDA
165 #define AT_45BR3214B /* No ID available */
166 #define AT_45CS1282 0x2920
167 #define AT_45D011 /* No ID available */
168 #define AT_45D021A /* No ID available */
169 #define AT_45D041A /* No ID available */
170 #define AT_45D081A /* No ID available */
171 #define AT_45D161 /* No ID available */
172 #define AT_45DB011 /* No ID available */
173 #define AT_45DB011B /* No ID available */
174 #define AT_45DB011D 0x2200
175 #define AT_45DB021A /* No ID available */
176 #define AT_45DB021B /* No ID available */
177 #define AT_45DB021D 0x2300
178 #define AT_45DB041A /* No ID available */
179 #define AT_45DB041D 0x2400
180 #define AT_45DB081A /* No ID available */
181 #define AT_45DB081D 0x2500
182 #define AT_45DB161 /* No ID available */
183 #define AT_45DB161B /* No ID available */
184 #define AT_45DB161D 0x2600
185 #define AT_45DB321 /* No ID available */
186 #define AT_45DB321B /* No ID available */
187 #define AT_45DB321C 0x2700
188 #define AT_45DB321D 0x2701 /* Buggy data sheet */
189 #define AT_45DB642 /* No ID available */
190 #define AT_45DB642D 0x2800
191 #define AT_49F002N 0x07 /* for AT49F002(N) */
192 #define AT_49F002NT 0x08 /* for AT49F002(N)T */
194 #define CATALYST_ID 0x31 /* Catalyst */
196 #define EMST_ID 0x8C /* EMST / EFST Elite Flash Storage */
197 #define EMST_F49B002UA 0x00
200 * EN25 chips are SPI, first byte of device ID is memory type,
201 * second byte of device ID is log(bitsize)-9.
202 * Vendor and device ID of EN29 series are both prefixed with 0x7F, which
203 * is the continuation code for IDs in bank 2.
204 * Vendor ID of EN25 series is NOT prefixed with 0x7F, this results in
205 * a collision with Mitsubishi. Mitsubishi once manufactured flash chips.
206 * Let's hope they are not manufacturing SPI flash chips as well.
208 #define EON_ID 0x7F1C /* EON Silicon Devices */
209 #define EON_ID_NOPREFIX 0x1C /* EON, missing 0x7F prefix */
210 #define EN_25B05 0x2010 /* 2^19 kbit or 2^16 kByte */
211 #define EN_25B10 0x2011
212 #define EN_25B20 0x2012
213 #define EN_25B40 0x2013
214 #define EN_25B80 0x2014
215 #define EN_25B16 0x2015
216 #define EN_25B32 0x2016
217 #define EN_29F512 0x7F21
218 #define EN_29F010 0x7F20
219 #define EN_29F040A 0x7F04
220 #define EN_29LV010 0x7F6E
221 #define EN_29LV040A 0x7F4F /* EN_29LV040(A) */
222 #define EN_29F002T 0x7F92
223 #define EN_29F002B 0x7F97
225 #define FUJITSU_ID 0x04 /* Fujitsu */
226 #define MBM29F400BC 0xAB
227 #define MBM29F400TC 0x23
228 #define MBM29F004BC 0x7B
229 #define MBM29F004TC 0x77
231 #define HYUNDAI_ID 0xAD /* Hyundai */
233 #define IMT_ID 0x7F1F /* Integrated Memory Technologies */
234 #define IM_29F004B 0xAE
235 #define IM_29F004T 0xAF
237 #define INTEL_ID 0x89 /* Intel */
239 #define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */
242 * MX25 chips are SPI, first byte of device ID is memory type,
243 * second byte of device ID is log(bitsize)-9.
244 * Generalplus SPI chips seem to be compatible with Macronix
245 * and use the same set of IDs.
247 #define MX_ID 0xC2 /* Macronix (MX) */
248 #define MX_25L512 0x2010 /* 2^19 kbit or 2^16 kByte */
249 #define MX_25L1005 0x2011
250 #define MX_25L2005 0x2012
251 #define MX_25L4005 0x2013 /* MX25L4005{,A} */
252 #define MX_25L8005 0x2014
253 #define MX_25L1605 0x2015 /* MX25L1605{,A,D} */
254 #define MX_25L3205 0x2016 /* MX25L3205{,A} */
255 #define MX_25L6405 0x2017 /* MX25L3205{,D} */
256 #define MX_25L1635D 0x2415
257 #define MX_25L3235D 0x2416
258 #define MX_29F002B 0x34
259 #define MX_29F002T 0xB0
260 #define MX_29LV002CB 0x5A
261 #define MX_29LV002CT 0x59
262 #define MX_29LV004CB 0xB6
263 #define MX_29LV004CT 0xB5
264 #define MX_29LV008CB 0x37
265 #define MX_29LV008CT 0x3E
266 #define MX_29F040C 0xA4
267 #define MX_29F200CB 0x57
268 #define MX_29F200CT 0x51
269 #define MX_29F400CB 0xAB
270 #define MX_29F400CT 0x23
271 #define MX_29LV040C 0x4F
272 #define MX_29LV128DB 0x7A
273 #define MX_29LV128DT 0x7E
274 #define MX_29LV160DB 0x49 /* Same as MX29LV161DB/MX29LV160CB */
275 #define MX_29LV160DT 0xC4 /* Same as MX29LV161DT/MX29LV160CT */
276 #define MX_29LV320DB 0xA8 /* Same as MX29LV321DB */
277 #define MX_29LV320DT 0xA7 /* Same as MX29LV321DT */
278 #define MX_29LV400CB 0xBA
279 #define MX_29LV400CT 0xB9
280 #define MX_29LV800CB 0x5B
281 #define MX_29LV800CT 0xDA
282 #define MX_29LV640DB 0xCB /* Same as MX29LV640EB */
283 #define MX_29LV640DT 0xC9 /* Same as MX29LV640ET */
284 #define MX_29SL402CB 0xF1
285 #define MX_29SL402CT 0x70
286 #define MX_29SL800CB 0x6B /* Same as MX29SL802CB */
287 #define MX_29SL800CT 0xEA /* Same as MX29SL802CT */
290 * Programmable Micro Corp is listed in JEP106W in bank 2, so it should
291 * have a 0x7F continuation code prefix.
293 #define PMC_ID 0x7F9D /* PMC */
294 #define PMC_ID_NOPREFIX 0x9D /* PMC, missing 0x7F prefix */
295 #define PMC_25LV512 0x7B
296 #define PMC_25LV010 0x7C
297 #define PMC_25LV020 0x7D
298 #define PMC_25LV040 0x7E
299 #define PMC_25LV080B 0x13
300 #define PMC_25LV016B 0x14
301 #define PMC_39LV512 0x1B
302 #define PMC_39F010 0x1C /* also Pm39LV010 */
303 #define PMC_39LV020 0x3D
304 #define PMC_39LV040 0x3E
305 #define PMC_39F020 0x4D
306 #define PMC_39F040 0x4E
307 #define PMC_49FL002 0x6D
308 #define PMC_49FL004 0x6E
310 #define SHARP_ID 0xB0 /* Sharp */
311 #define SHARP_LHF00L04 0xCF
314 * Spansion was previously a joint venture of AMD and Fujitsu.
315 * S25 chips are SPI. The first device ID byte is memory type and
316 * the second device ID byte is memory capacity.
318 #define SPANSION_ID 0x01 /* Spansion */
319 #define SPANSION_S25FL016A 0x0214
322 * SST25 chips are SPI, first byte of device ID is memory type, second
323 * byte of device ID is related to log(bitsize) at least for some chips.
325 #define SST_ID 0xBF /* SST */
326 #define SST_25WF512 0x2501
327 #define SST_25WF010 0x2502
328 #define SST_25WF020 0x2503
329 #define SST_25WF040 0x2504
330 #define SST_25VF512A_REMS 0x48 /* REMS or RES opcode */
331 #define SST_25VF010_REMS 0x49 /* REMS or RES opcode */
332 #define SST_25VF020_REMS 0x43 /* REMS or RES opcode */
333 #define SST_25VF040_REMS 0x44 /* REMS or RES opcode */
334 #define SST_25VF040B 0x258D
335 #define SST_25VF040B_REMS 0x8D /* REMS or RES opcode */
336 #define SST_25VF080_REMS 0x80 /* REMS or RES opcode */
337 #define SST_25VF080B 0x258E
338 #define SST_25VF080B_REMS 0x8E /* REMS or RES opcode */
339 #define SST_25VF016B 0x2541
340 #define SST_25VF032B 0x254A
341 #define SST_25VF032B_REMS 0x4A /* REMS or RES opcode */
342 #define SST_26VF016 0x2601
343 #define SST_26VF032 0x2602
344 #define SST_27SF512 0xA4
345 #define SST_27SF010 0xA5
346 #define SST_27SF020 0xA6
347 #define SST_27VF010 0xA9
348 #define SST_27VF020 0xAA
349 #define SST_28SF040 0x04
350 #define SST_29EE512 0x5D
351 #define SST_29EE010 0x07
352 #define SST_29LE010 0x08 /* also SST29VE010 */
353 #define SST_29EE020A 0x10
354 #define SST_29LE020 0x12 /* also SST29VE020 */
355 #define SST_29SF020 0x24
356 #define SST_29VF020 0x25
357 #define SST_29SF040 0x13
358 #define SST_29VF040 0x14
359 #define SST_39SF010 0xB5
360 #define SST_39SF020 0xB6
361 #define SST_39SF040 0xB7
362 #define SST_39VF512 0xD4
363 #define SST_39VF010 0xD5
364 #define SST_39VF020 0xD6
365 #define SST_39VF040 0xD7
366 #define SST_49LF040B 0x50
367 #define SST_49LF040 0x51
368 #define SST_49LF020 0x61
369 #define SST_49LF020A 0x52
370 #define SST_49LF080A 0x5B
371 #define SST_49LF002A 0x57
372 #define SST_49LF003A 0x1B
373 #define SST_49LF004A 0x60
374 #define SST_49LF008A 0x5A
375 #define SST_49LF004C 0x54
376 #define SST_49LF008C 0x59
377 #define SST_49LF016C 0x5C
378 #define SST_49LF160C 0x4C
381 * ST25P chips are SPI, first byte of device ID is memory type, second
382 * byte of device ID is related to log(bitsize) at least for some chips.
384 #define ST_ID 0x20 /* ST / SGS/Thomson */
385 #define ST_M25P05A 0x2010
386 #define ST_M25P10A 0x2011
387 #define ST_M25P20 0x2012
388 #define ST_M25P40 0x2013
389 #define ST_M25P40_RES 0x12
390 #define ST_M25P80 0x2014
391 #define ST_M25P16 0x2015
392 #define ST_M25P32 0x2016
393 #define ST_M25P64 0x2017
394 #define ST_M25P128 0x2018
395 #define ST_M50FLW040A 0x08
396 #define ST_M50FLW040B 0x28
397 #define ST_M50FLW080A 0x80
398 #define ST_M50FLW080B 0x81
399 #define ST_M50FW002 0x29
400 #define ST_M50FW040 0x2C
401 #define ST_M50FW080 0x2D
402 #define ST_M50FW016 0x2E
403 #define ST_M50LPW116 0x30
404 #define ST_M29F002B 0x34
405 #define ST_M29F002T 0xB0 /* M29F002T / M29F002NT */
406 #define ST_M29F400BT 0xD5
407 #define ST_M29F040B 0xE2
408 #define ST_M29W010B 0x23
409 #define ST_M29W040B 0xE3
411 #define SYNCMOS_ID 0x40 /* SyncMOS and Mosel Vitelic */
412 #define S29C51001T 0x01
413 #define S29C51002T 0x02
414 #define S29C51004T 0x03
415 #define S29C31004T 0x63
417 #define TI_ID 0x97 /* Texas Instruments */
420 * W25X chips are SPI, first byte of device ID is memory type, second
421 * byte of device ID is related to log(bitsize).
423 #define WINBOND_ID 0xDA /* Winbond */
424 #define WINBOND_NEX_ID 0xEF /* Winbond (ex Nexcom) serial flash devices */
425 #define W_25X10 0x3011
426 #define W_25X20 0x3012
427 #define W_25X40 0x3013
428 #define W_25X80 0x3014
429 #define W_25X16 0x3015
430 #define W_25X32 0x3016
431 #define W_25X64 0x3017
432 #define W_29C011 0xC1
433 #define W_29C020C 0x45
434 #define W_29C040P 0x46
435 #define W_29EE011 0xC1
436 #define W_39V040FA 0x34
437 #define W_39V040A 0x3D
438 #define W_39V040B 0x54
439 #define W_39V080A 0xD0
440 #define W_39V080FA 0xD3
441 #define W_39V080FA_DM 0x93
442 #define W_49F002U 0x0B
443 #define W_49V002A 0xB0
444 #define W_49V002FA 0x32
447 void myusec_delay(int time);
448 void myusec_calibrate_delay();
450 /* PCI handling for board/chipset_enable */
451 struct pci_access *pacc;
452 struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
453 struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
454 uint16_t card_vendor, uint16_t card_device);
457 int board_flash_enable(const char *vendor, const char *part);
458 void print_supported_boards(void);
460 /* chipset_enable.c */
461 int chipset_flash_enable(void);
462 void print_supported_chipsets(void);
464 extern unsigned long flashbase;
475 extern flashbus_t flashbus;
480 #define printf_debug(x...) { if (verbose) printf(x); }
483 void *physmap(const char *descr, unsigned long phys_addr, size_t len);
484 void physunmap(void *virt_addr, size_t len);
487 void map_flash_registers(struct flashchip *flash);
490 int show_id(uint8_t *bios, int size, int force);
491 int read_romlayout(char *name);
492 int find_romentry(char *name);
493 int handle_romentries(uint8_t *buffer, uint8_t *content);
496 int coreboot_init(void);
497 extern char *lb_part, *lb_vendor;
500 int probe_spi_rdid(struct flashchip *flash);
501 int probe_spi_rdid4(struct flashchip *flash);
502 int probe_spi_rems(struct flashchip *flash);
503 int probe_spi_res(struct flashchip *flash);
504 int spi_command(unsigned int writecnt, unsigned int readcnt,
505 const unsigned char *writearr, unsigned char *readarr);
506 int spi_write_enable();
507 int spi_write_disable();
508 int spi_chip_erase_60(struct flashchip *flash);
509 int spi_chip_erase_c7(struct flashchip *flash);
510 int spi_chip_erase_60_c7(struct flashchip *flash);
511 int spi_chip_erase_d8(struct flashchip *flash);
512 int spi_block_erase_52(const struct flashchip *flash, unsigned long addr);
513 int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr);
514 int spi_chip_write(struct flashchip *flash, uint8_t *buf);
515 int spi_chip_read(struct flashchip *flash, uint8_t *buf);
516 uint8_t spi_read_status_register();
517 int spi_disable_blockprotect(void);
518 void spi_byte_program(int address, uint8_t byte);
519 int spi_nbyte_read(int address, uint8_t *bytes, int len);
522 int probe_82802ab(struct flashchip *flash);
523 int erase_82802ab(struct flashchip *flash);
524 int write_82802ab(struct flashchip *flash, uint8_t *buf);
527 int probe_29f040b(struct flashchip *flash);
528 int erase_29f040b(struct flashchip *flash);
529 int write_29f040b(struct flashchip *flash, uint8_t *buf);
532 int probe_en29f002a(struct flashchip *flash);
533 int erase_en29f002a(struct flashchip *flash);
534 int write_en29f002a(struct flashchip *flash, uint8_t *buf);
537 int ich_init_opcodes();
538 int ich_spi_command(unsigned int writecnt, unsigned int readcnt,
539 const unsigned char *writearr, unsigned char *readarr);
540 int ich_spi_read(struct flashchip *flash, uint8_t * buf);
541 int ich_spi_write(struct flashchip *flash, uint8_t * buf);
544 extern uint16_t it8716f_flashport;
545 int it87xx_probe_spi_flash(const char *name);
546 int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt,
547 const unsigned char *writearr, unsigned char *readarr);
548 int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf);
549 int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf);
552 int sb600_spi_command(unsigned int writecnt, unsigned int readcnt,
553 const unsigned char *writearr, unsigned char *readarr);
554 int sb600_spi_read(struct flashchip *flash, uint8_t *buf);
555 int sb600_spi_write(struct flashchip *flash, uint8_t *buf);
556 uint8_t sb600_read_status_register(void);
557 extern uint8_t volatile *sb600_spibar;
560 uint8_t oddparity(uint8_t val);
561 void toggle_ready_jedec(volatile uint8_t *dst);
562 void data_polling_jedec(volatile uint8_t *dst, uint8_t data);
563 void unprotect_jedec(volatile uint8_t *bios);
564 void protect_jedec(volatile uint8_t *bios);
565 int write_byte_program_jedec(volatile uint8_t *bios, uint8_t *src,
566 volatile uint8_t *dst);
567 int probe_jedec(struct flashchip *flash);
568 int erase_chip_jedec(struct flashchip *flash);
569 int write_jedec(struct flashchip *flash, uint8_t *buf);
570 int erase_sector_jedec(volatile uint8_t *bios, unsigned int page);
571 int erase_block_jedec(volatile uint8_t *bios, unsigned int page);
572 int write_sector_jedec(volatile uint8_t *bios, uint8_t *src,
573 volatile uint8_t *dst, unsigned int page_size);
576 int probe_m29f400bt(struct flashchip *flash);
577 int erase_m29f400bt(struct flashchip *flash);
578 int block_erase_m29f400bt(volatile uint8_t *bios,
579 volatile uint8_t *dst);
580 int write_m29f400bt(struct flashchip *flash, uint8_t *buf);
581 int write_coreboot_m29f400bt(struct flashchip *flash, uint8_t *buf);
582 void toggle_ready_m29f400bt(volatile uint8_t *dst);
583 void data_polling_m29f400bt(volatile uint8_t *dst, uint8_t data);
584 void protect_m29f400bt(volatile uint8_t *bios);
585 void write_page_m29f400bt(volatile uint8_t *bios, uint8_t *src,
586 volatile uint8_t *dst, int page_size);
589 int probe_29f002(struct flashchip *flash);
590 int erase_29f002(struct flashchip *flash);
591 int write_29f002(struct flashchip *flash, uint8_t *buf);
594 int probe_49fl00x(struct flashchip *flash);
595 int erase_49fl00x(struct flashchip *flash);
596 int write_49fl00x(struct flashchip *flash, uint8_t *buf);
598 /* sharplhf00l04.c */
599 int probe_lhf00l04(struct flashchip *flash);
600 int erase_lhf00l04(struct flashchip *flash);
601 int write_lhf00l04(struct flashchip *flash, uint8_t *buf);
602 void toggle_ready_lhf00l04(volatile uint8_t *dst);
603 void data_polling_lhf00l04(volatile uint8_t *dst, uint8_t data);
604 void protect_lhf00l04(volatile uint8_t *bios);
607 int probe_28sf040(struct flashchip *flash);
608 int erase_28sf040(struct flashchip *flash);
609 int write_28sf040(struct flashchip *flash, uint8_t *buf);
612 int probe_39sf020(struct flashchip *flash);
613 int write_39sf020(struct flashchip *flash, uint8_t *buf);
616 int erase_49lf040(struct flashchip *flash);
617 int write_49lf040(struct flashchip *flash, uint8_t *buf);
620 int probe_49lfxxxc(struct flashchip *flash);
621 int erase_49lfxxxc(struct flashchip *flash);
622 int write_49lfxxxc(struct flashchip *flash, uint8_t *buf);
625 int probe_sst_fwhub(struct flashchip *flash);
626 int erase_sst_fwhub(struct flashchip *flash);
627 int write_sst_fwhub(struct flashchip *flash, uint8_t *buf);
630 int probe_w39v040c(struct flashchip *flash);
631 int erase_w39v040c(struct flashchip *flash);
632 int write_w39v040c(struct flashchip *flash, uint8_t *buf);
635 int probe_winbond_fwhub(struct flashchip *flash);
636 int erase_winbond_fwhub(struct flashchip *flash);
637 int write_winbond_fwhub(struct flashchip *flash, uint8_t *buf);
640 int probe_w29ee011(struct flashchip *flash);
643 int write_49f002(struct flashchip *flash, uint8_t *buf);
646 int probe_stm50flw0x0x(struct flashchip *flash);
647 int erase_stm50flw0x0x(struct flashchip *flash);
648 int write_stm50flw0x0x(struct flashchip *flash, uint8_t *buf);
650 #endif /* !__FLASH_H__ */