2 * flash rom utility: enable flash writes
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
6 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
21 static int enable_flash_ali_m1533(struct pci_dev *dev, char *name)
25 /* ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
26 0xFFFE0000-0xFFFFFFFF ROM select enable. */
27 tmp = pci_read_byte(dev, 0x47);
29 pci_write_byte(dev, 0x47, tmp);
34 static int enable_flash_sis630(struct pci_dev *dev, char *name)
38 /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630 */
39 outl(0x80000840, 0x0cf8);
40 b = inb(0x0cfc) | 0x0b;
42 /* Flash write enable on SiS 540/630 */
43 outl(0x80000845, 0x0cf8);
44 b = inb(0x0cfd) | 0x40;
47 /* The same thing on SiS 950 SuperIO side */
53 if (inb(0x2f) != 0x87) {
58 if (inb(0x4f) != 0x87) {
59 printf("Can not access SiS 950\n");
71 printf("2f is %#x\n", inb(0x2f));
83 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
84 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
85 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
86 * - Order Number: 290562-001
88 static int enable_flash_piix4(struct pci_dev *dev, char *name)
91 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
93 old = pci_read_word(dev, xbcs);
95 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
96 * FFF00000-FFF7FFFF are forwarded to ISA).
97 * Set bit 7: Extended BIOS Enable (PCI master accesses to
98 * FFF80000-FFFDFFFF are forwarded to ISA).
99 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
100 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
101 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
102 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
103 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
104 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
111 pci_write_word(dev, xbcs, new);
113 if (pci_read_word(dev, xbcs) != new) {
114 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
120 static int enable_flash_ich(struct pci_dev *dev, char *name, int bios_cntl)
122 /* register 4e.b gets or'ed with one */
125 /* if it fails, it fails. There are so many variations of broken mobos
126 * that it is hard to argue that we should quit at this point.
129 /* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
130 * just treating it as 8 bit wide seems to work fine in practice.
133 /* see ie. page 375 of "Intel ICH7 External Design Specification"
134 * http://download.intel.com/design/chipsets/datashts/30701302.pdf
137 old = pci_read_byte(dev, bios_cntl);
144 pci_write_byte(dev, bios_cntl, new);
146 if (pci_read_byte(dev, bios_cntl) != new) {
147 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
153 static int enable_flash_ich_4e(struct pci_dev *dev, char *name)
155 return enable_flash_ich(dev, name, 0x4e);
158 static int enable_flash_ich_dc(struct pci_dev *dev, char *name)
160 return enable_flash_ich(dev, name, 0xdc);
166 static int enable_flash_vt823x(struct pci_dev *dev, char *name)
170 /* ROM Write enable */
171 val = pci_read_byte(dev, 0x40);
173 pci_write_byte(dev, 0x40, val);
175 if (pci_read_byte(dev, 0x40) != val) {
176 printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n",
184 static int enable_flash_cs5530(struct pci_dev *dev, char *name)
188 #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
189 #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
191 #define LOWER_ROM_ADDRESS_RANGE (1 << 0)
192 #define ROM_WRITE_ENABLE (1 << 1)
193 #define UPPER_ROM_ADDRESS_RANGE (1 << 2)
194 #define BIOS_ROM_POSITIVE_DECODE (1 << 5)
196 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
197 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
198 * Make the configured ROM areas writable.
200 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
201 reg8 |= LOWER_ROM_ADDRESS_RANGE;
202 reg8 |= UPPER_ROM_ADDRESS_RANGE;
203 reg8 |= ROM_WRITE_ENABLE;
204 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
206 /* Set positive decode on ROM. */
207 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
208 reg8 |= BIOS_ROM_POSITIVE_DECODE;
209 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
214 static int enable_flash_sc1100(struct pci_dev *dev, char *name)
218 pci_write_byte(dev, 0x52, 0xee);
220 new = pci_read_byte(dev, 0x52);
223 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
229 static int enable_flash_sis5595(struct pci_dev *dev, char *name)
233 new = pci_read_byte(dev, 0x45);
240 pci_write_byte(dev, 0x45, new);
242 newer = pci_read_byte(dev, 0x45);
244 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
245 printf("Stuck at 0x%x\n", newer);
251 static int enable_flash_amd8111(struct pci_dev *dev, char *name)
253 /* register 4e.b gets or'ed with one */
256 /* if it fails, it fails. There are so many variations of broken mobos
257 * that it is hard to argue that we should quit at this point.
260 /* enable decoding at 0xffb00000 to 0xffffffff */
261 old = pci_read_byte(dev, 0x43);
264 pci_write_byte(dev, 0x43, new);
265 if (pci_read_byte(dev, 0x43) != new) {
266 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
270 old = pci_read_byte(dev, 0x40);
274 pci_write_byte(dev, 0x40, new);
276 if (pci_read_byte(dev, 0x40) != new) {
277 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
283 static int enable_flash_ck804(struct pci_dev *dev, char *name)
285 /* register 4e.b gets or'ed with one */
288 /* if it fails, it fails. There are so many variations of broken mobos
289 * that it is hard to argue that we should quit at this point.
292 /* dump_pci_device(dev); */
294 old = pci_read_byte(dev, 0x88);
297 pci_write_byte(dev, 0x88, new);
298 if (pci_read_byte(dev, 0x88) != new) {
299 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
303 old = pci_read_byte(dev, 0x6d);
307 pci_write_byte(dev, 0x6d, new);
309 if (pci_read_byte(dev, 0x6d) != new) {
310 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
316 static int enable_flash_sb400(struct pci_dev *dev, char *name)
321 struct pci_dev *smbusdev;
323 /* then look for the smbus device */
324 pci_filter_init((struct pci_access *)0, &f);
328 for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
329 if (pci_filter_match(&f, smbusdev)) {
335 fprintf(stderr, "ERROR: SMBus device not found. aborting\n");
339 /* enable some smbus stuff */
340 tmp = pci_read_byte(smbusdev, 0x79);
342 pci_write_byte(smbusdev, 0x79, tmp);
344 /* change southbridge */
345 tmp = pci_read_byte(dev, 0x48);
347 pci_write_byte(dev, 0x48, tmp);
349 /* now become a bit silly. */
361 static int enable_flash_mcp55(struct pci_dev *dev, char *name)
363 /* register 4e.b gets or'ed with one */
364 unsigned char old, new, byte;
367 /* if it fails, it fails. There are so many variations of broken mobos
368 * that it is hard to argue that we should quit at this point.
371 /* dump_pci_device(dev); */
373 /* Set the 4MB enable bit bit */
374 byte = pci_read_byte(dev, 0x88);
375 byte |= 0xff; /* 256K */
376 pci_write_byte(dev, 0x88, byte);
377 byte = pci_read_byte(dev, 0x8c);
378 byte |= 0xff; /* 1M */
379 pci_write_byte(dev, 0x8c, byte);
380 word = pci_read_word(dev, 0x90);
381 word |= 0x7fff; /* 15M */
382 pci_write_word(dev, 0x90, word);
384 old = pci_read_byte(dev, 0x6d);
388 pci_write_byte(dev, 0x6d, new);
390 if (pci_read_byte(dev, 0x6d) != new) {
392 ("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
401 static int enable_flash_ht1000(struct pci_dev *dev, char *name)
405 /* Set the 4MB enable bit. */
406 byte = pci_read_byte(dev, 0x41);
408 pci_write_byte(dev, 0x41, byte);
410 byte = pci_read_byte(dev, 0x43);
412 pci_write_byte(dev, 0x43, byte);
417 typedef struct penable {
418 unsigned short vendor, device;
420 int (*doit) (struct pci_dev * dev, char *name);
423 static FLASH_ENABLE enables[] = {
424 {0x1039, 0x0630, "SIS630", enable_flash_sis630},
425 {0x8086, 0x7110, "PIIX4/PIIX4E/PIIX4M", enable_flash_piix4},
426 {0x8086, 0x2410, "ICH", enable_flash_ich_4e},
427 {0x8086, 0x2420, "ICH0", enable_flash_ich_4e},
428 {0x8086, 0x2440, "ICH2", enable_flash_ich_4e},
429 {0x8086, 0x244c, "ICH2-M", enable_flash_ich_4e},
430 {0x8086, 0x2480, "ICH3-S", enable_flash_ich_4e},
431 {0x8086, 0x248c, "ICH3-M", enable_flash_ich_4e},
432 {0x8086, 0x24c0, "ICH4/ICH4-L", enable_flash_ich_4e},
433 {0x8086, 0x24cc, "ICH4-M", enable_flash_ich_4e},
434 {0x8086, 0x24d0, "ICH5/ICH5R", enable_flash_ich_4e},
435 {0x8086, 0x2640, "ICH6/ICH6R", enable_flash_ich_dc},
436 {0x8086, 0x2641, "ICH6-M", enable_flash_ich_dc},
437 {0x8086, 0x27b0, "ICH7DH", enable_flash_ich_dc},
438 {0x8086, 0x27b8, "ICH7/ICH7R", enable_flash_ich_dc},
439 {0x8086, 0x27b9, "ICH7M", enable_flash_ich_dc},
440 {0x8086, 0x27bd, "ICH7MDH", enable_flash_ich_dc},
441 {0x8086, 0x2810, "ICH8/ICH8R", enable_flash_ich_dc},
442 {0x8086, 0x2812, "ICH8DH", enable_flash_ich_dc},
443 {0x8086, 0x2814, "ICH8DO", enable_flash_ich_dc},
444 {0x1106, 0x8231, "VT8231", enable_flash_vt823x},
445 {0x1106, 0x3177, "VT8235", enable_flash_vt823x},
446 {0x1106, 0x3227, "VT8237", enable_flash_vt823x},
447 {0x1106, 0x8324, "CX700", enable_flash_vt823x},
448 {0x1106, 0x0686, "VT82C686", enable_flash_amd8111},
449 {0x1078, 0x0100, "CS5530/CS5530A", enable_flash_cs5530},
450 {0x100b, 0x0510, "SC1100", enable_flash_sc1100},
451 {0x1039, 0x0008, "SIS5595", enable_flash_sis5595},
452 {0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
453 {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533},
454 /* this fallthrough looks broken. */
455 {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */
456 {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */
457 {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, /* Slave, should not be here, to fix known bug for A01. */
459 {0x10de, 0x0260, "NVidia MCP51", enable_flash_ck804},
460 {0x10de, 0x0261, "NVidia MCP51", enable_flash_ck804},
461 {0x10de, 0x0262, "NVidia MCP51", enable_flash_ck804},
462 {0x10de, 0x0263, "NVidia MCP51", enable_flash_ck804},
464 {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* Gigabyte m57sli-s4 */
465 {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
466 {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
467 {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
468 {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
469 {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
470 {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
471 {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
473 {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
475 {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000},
481 int chipset_flash_enable(void)
483 struct pci_dev *dev = 0;
484 int ret = -2; /* nothing! */
487 /* now let's try to find the chipset we have ... */
488 for (i = 0; i < sizeof(enables) / sizeof(enables[0]); i++) {
489 dev = pci_dev_find(enables[i].vendor, enables[i].device);
495 printf("Found chipset \"%s\": Enabling flash write... ",
498 ret = enables[i].doit(dev, enables[i].name);