2 * flash rom utility: enable flash writes
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
6 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
19 static int enable_flash_ali_m1533(struct pci_dev *dev, char *name)
23 /* ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
24 0xFFFE0000-0xFFFFFFFF ROM select enable. */
25 tmp = pci_read_byte(dev, 0x47);
27 pci_write_byte(dev, 0x47, tmp);
32 static int enable_flash_sis630(struct pci_dev *dev, char *name)
36 /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630 */
37 outl(0x80000840, 0x0cf8);
38 b = inb(0x0cfc) | 0x0b;
40 /* Flash write enable on SiS 540/630 */
41 outl(0x80000845, 0x0cf8);
42 b = inb(0x0cfd) | 0x40;
45 /* The same thing on SiS 950 SuperIO side */
51 if (inb(0x2f) != 0x87) {
56 if (inb(0x4f) != 0x87) {
57 printf("Can not access SiS 950\n");
69 printf("2f is %#x\n", inb(0x2f));
81 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
82 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
83 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
84 * - Order Number: 290562-001
86 static int enable_flash_piix4(struct pci_dev *dev, char *name)
89 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
91 old = pci_read_word(dev, xbcs);
93 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
94 * FFF00000-FFF7FFFF are forwarded to ISA).
95 * Set bit 7: Extended BIOS Enable (PCI master accesses to
96 * FFF80000-FFFDFFFF are forwarded to ISA).
97 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
98 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
99 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
100 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
101 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
102 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
109 pci_write_word(dev, xbcs, new);
111 if (pci_read_word(dev, xbcs) != new) {
112 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
118 static int enable_flash_ich(struct pci_dev *dev, char *name, int bios_cntl)
120 /* register 4e.b gets or'ed with one */
123 /* if it fails, it fails. There are so many variations of broken mobos
124 * that it is hard to argue that we should quit at this point.
127 /* Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
128 * just treating it as 8 bit wide seems to work fine in practice.
131 /* see ie. page 375 of "Intel ICH7 External Design Specification"
132 * http://download.intel.com/design/chipsets/datashts/30701302.pdf
135 old = pci_read_byte(dev, bios_cntl);
142 pci_write_byte(dev, bios_cntl, new);
144 if (pci_read_byte(dev, bios_cntl) != new) {
145 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
151 static int enable_flash_ich_4e(struct pci_dev *dev, char *name)
153 return enable_flash_ich(dev, name, 0x4e);
156 static int enable_flash_ich_dc(struct pci_dev *dev, char *name)
158 return enable_flash_ich(dev, name, 0xdc);
164 static int enable_flash_vt823x(struct pci_dev *dev, char *name)
168 /* ROM Write enable */
169 val = pci_read_byte(dev, 0x40);
171 pci_write_byte(dev, 0x40, val);
173 if (pci_read_byte(dev, 0x40) != val) {
174 printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n",
182 static int enable_flash_cs5530(struct pci_dev *dev, char *name)
186 #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
187 #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
189 #define LOWER_ROM_ADDRESS_RANGE (1 << 0)
190 #define ROM_WRITE_ENABLE (1 << 1)
191 #define UPPER_ROM_ADDRESS_RANGE (1 << 2)
192 #define BIOS_ROM_POSITIVE_DECODE (1 << 5)
194 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
195 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
196 * Make the configured ROM areas writable.
198 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
199 reg8 |= LOWER_ROM_ADDRESS_RANGE;
200 reg8 |= UPPER_ROM_ADDRESS_RANGE;
201 reg8 |= ROM_WRITE_ENABLE;
202 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
204 /* Set positive decode on ROM. */
205 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
206 reg8 |= BIOS_ROM_POSITIVE_DECODE;
207 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
212 static int enable_flash_sc1100(struct pci_dev *dev, char *name)
216 pci_write_byte(dev, 0x52, 0xee);
218 new = pci_read_byte(dev, 0x52);
221 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
227 static int enable_flash_sis5595(struct pci_dev *dev, char *name)
231 new = pci_read_byte(dev, 0x45);
238 pci_write_byte(dev, 0x45, new);
240 newer = pci_read_byte(dev, 0x45);
242 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
243 printf("Stuck at 0x%x\n", newer);
249 static int enable_flash_amd8111(struct pci_dev *dev, char *name)
251 /* register 4e.b gets or'ed with one */
254 /* if it fails, it fails. There are so many variations of broken mobos
255 * that it is hard to argue that we should quit at this point.
258 /* enable decoding at 0xffb00000 to 0xffffffff */
259 old = pci_read_byte(dev, 0x43);
262 pci_write_byte(dev, 0x43, new);
263 if (pci_read_byte(dev, 0x43) != new) {
264 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
268 old = pci_read_byte(dev, 0x40);
272 pci_write_byte(dev, 0x40, new);
274 if (pci_read_byte(dev, 0x40) != new) {
275 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
281 static int enable_flash_ck804(struct pci_dev *dev, char *name)
283 /* register 4e.b gets or'ed with one */
286 /* if it fails, it fails. There are so many variations of broken mobos
287 * that it is hard to argue that we should quit at this point.
290 /* dump_pci_device(dev); */
292 old = pci_read_byte(dev, 0x88);
295 pci_write_byte(dev, 0x88, new);
296 if (pci_read_byte(dev, 0x88) != new) {
297 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
301 old = pci_read_byte(dev, 0x6d);
305 pci_write_byte(dev, 0x6d, new);
307 if (pci_read_byte(dev, 0x6d) != new) {
308 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
314 static int enable_flash_sb400(struct pci_dev *dev, char *name)
319 struct pci_dev *smbusdev;
321 /* then look for the smbus device */
322 pci_filter_init((struct pci_access *)0, &f);
326 for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
327 if (pci_filter_match(&f, smbusdev)) {
333 fprintf(stderr, "ERROR: SMBus device not found. aborting\n");
337 /* enable some smbus stuff */
338 tmp = pci_read_byte(smbusdev, 0x79);
340 pci_write_byte(smbusdev, 0x79, tmp);
342 /* change southbridge */
343 tmp = pci_read_byte(dev, 0x48);
345 pci_write_byte(dev, 0x48, tmp);
347 /* now become a bit silly. */
359 static int enable_flash_mcp55(struct pci_dev *dev, char *name)
361 /* register 4e.b gets or'ed with one */
362 unsigned char old, new, byte;
365 /* if it fails, it fails. There are so many variations of broken mobos
366 * that it is hard to argue that we should quit at this point.
369 /* dump_pci_device(dev); */
371 /* Set the 4MB enable bit bit */
372 byte = pci_read_byte(dev, 0x88);
373 byte |= 0xff; /* 256K */
374 pci_write_byte(dev, 0x88, byte);
375 byte = pci_read_byte(dev, 0x8c);
376 byte |= 0xff; /* 1M */
377 pci_write_byte(dev, 0x8c, byte);
378 word = pci_read_word(dev, 0x90);
379 word |= 0x7fff; /* 15M */
380 pci_write_word(dev, 0x90, word);
382 old = pci_read_byte(dev, 0x6d);
386 pci_write_byte(dev, 0x6d, new);
388 if (pci_read_byte(dev, 0x6d) != new) {
390 ("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
399 static int enable_flash_ht1000(struct pci_dev *dev, char *name)
403 /* Set the 4MB enable bit. */
404 byte = pci_read_byte(dev, 0x41);
406 pci_write_byte(dev, 0x41, byte);
408 byte = pci_read_byte(dev, 0x43);
410 pci_write_byte(dev, 0x43, byte);
415 typedef struct penable {
416 unsigned short vendor, device;
418 int (*doit) (struct pci_dev * dev, char *name);
421 static FLASH_ENABLE enables[] = {
422 {0x1039, 0x0630, "SIS630", enable_flash_sis630},
423 {0x8086, 0x7110, "PIIX4/PIIX4E/PIIX4M", enable_flash_piix4},
424 {0x8086, 0x2410, "ICH", enable_flash_ich_4e},
425 {0x8086, 0x2420, "ICH0", enable_flash_ich_4e},
426 {0x8086, 0x2440, "ICH2", enable_flash_ich_4e},
427 {0x8086, 0x244c, "ICH2-M", enable_flash_ich_4e},
428 {0x8086, 0x2480, "ICH3-S", enable_flash_ich_4e},
429 {0x8086, 0x248c, "ICH3-M", enable_flash_ich_4e},
430 {0x8086, 0x24c0, "ICH4/ICH4-L", enable_flash_ich_4e},
431 {0x8086, 0x24cc, "ICH4-M", enable_flash_ich_4e},
432 {0x8086, 0x24d0, "ICH5/ICH5R", enable_flash_ich_4e},
433 {0x8086, 0x2640, "ICH6/ICH6R", enable_flash_ich_dc},
434 {0x8086, 0x2641, "ICH6-M", enable_flash_ich_dc},
435 {0x8086, 0x27b0, "ICH7DH", enable_flash_ich_dc},
436 {0x8086, 0x27b8, "ICH7/ICH7R", enable_flash_ich_dc},
437 {0x8086, 0x27b9, "ICH7M", enable_flash_ich_dc},
438 {0x8086, 0x27bd, "ICH7MDH", enable_flash_ich_dc},
439 {0x8086, 0x2810, "ICH8/ICH8R", enable_flash_ich_dc},
440 {0x8086, 0x2812, "ICH8DH", enable_flash_ich_dc},
441 {0x8086, 0x2814, "ICH8DO", enable_flash_ich_dc},
442 {0x1106, 0x8231, "VT8231", enable_flash_vt823x},
443 {0x1106, 0x3177, "VT8235", enable_flash_vt823x},
444 {0x1106, 0x3227, "VT8237", enable_flash_vt823x},
445 {0x1106, 0x8324, "CX700", enable_flash_vt823x},
446 {0x1106, 0x0686, "VT82C686", enable_flash_amd8111},
447 {0x1078, 0x0100, "CS5530/CS5530A", enable_flash_cs5530},
448 {0x100b, 0x0510, "SC1100", enable_flash_sc1100},
449 {0x1039, 0x0008, "SIS5595", enable_flash_sis5595},
450 {0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
451 {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533},
452 /* this fallthrough looks broken. */
453 {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */
454 {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */
455 {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804}, /* Slave, should not be here, to fix known bug for A01. */
457 {0x10de, 0x0260, "NVidia MCP51", enable_flash_ck804},
458 {0x10de, 0x0261, "NVidia MCP51", enable_flash_ck804},
459 {0x10de, 0x0262, "NVidia MCP51", enable_flash_ck804},
460 {0x10de, 0x0263, "NVidia MCP51", enable_flash_ck804},
462 {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* Gigabyte m57sli-s4 */
463 {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
464 {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
465 {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
466 {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
467 {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
468 {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
469 {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
471 {0x1002, 0x4377, "ATI SB400", enable_flash_sb400}, /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
473 {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000},
479 int chipset_flash_enable(void)
481 struct pci_dev *dev = 0;
482 int ret = -2; /* nothing! */
485 /* now let's try to find the chipset we have ... */
486 for (i = 0; i < sizeof(enables) / sizeof(enables[0]); i++) {
487 dev = pci_dev_find(enables[i].vendor, enables[i].device);
493 printf("Found chipset \"%s\": Enabling flash write... ",
496 ret = enables[i].doit(dev, enables[i].name);