2 * This file is part of the flashrom project.
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
6 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 * Contains the chipset specific flash enables.
26 #define _LARGEFILE64_SOURCE
31 #include <sys/types.h>
37 static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
42 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
43 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
45 tmp = pci_read_byte(dev, 0x47);
47 pci_write_byte(dev, 0x47, tmp);
52 static int enable_flash_sis630(struct pci_dev *dev, const char *name)
56 /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
57 b = pci_read_byte(dev, 0x40);
58 pci_write_byte(dev, 0x40, b | 0xb);
60 /* Flash write enable on SiS 540/630. */
61 b = pci_read_byte(dev, 0x45);
62 pci_write_byte(dev, 0x45, b | 0x40);
64 /* The same thing on SiS 950 Super I/O side... */
66 /* First probe for Super I/O on config port 0x2e. */
72 if (inb(0x2f) != 0x87) {
73 /* If that failed, try config port 0x4e. */
78 if (inb(0x4f) != 0x87) {
79 printf("Can not access SiS 950\n");
91 printf("2f is %#x\n", inb(0x2f));
103 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
104 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
105 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
106 * - Order Number: 290562-001
108 static int enable_flash_piix4(struct pci_dev *dev, const char *name)
111 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
113 old = pci_read_word(dev, xbcs);
115 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
116 * FFF00000-FFF7FFFF are forwarded to ISA).
117 * Set bit 7: Extended BIOS Enable (PCI master accesses to
118 * FFF80000-FFFDFFFF are forwarded to ISA).
119 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
120 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
121 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
122 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
123 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
124 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
131 pci_write_word(dev, xbcs, new);
133 if (pci_read_word(dev, xbcs) != new) {
134 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
142 * See ie. page 375 of "Intel ICH7 External Design Specification"
143 * http://download.intel.com/design/chipsets/datashts/30701302.pdf
145 static int enable_flash_ich(struct pci_dev *dev, const char *name,
151 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
152 * just treating it as 8 bit wide seems to work fine in practice.
154 old = pci_read_byte(dev, bios_cntl);
161 pci_write_byte(dev, bios_cntl, new);
163 if (pci_read_byte(dev, bios_cntl) != new) {
164 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
171 static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
173 return enable_flash_ich(dev, name, 0x4e);
176 static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
178 return enable_flash_ich(dev, name, 0xdc);
181 static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
185 /* ROM write enable */
186 val = pci_read_byte(dev, 0x40);
188 pci_write_byte(dev, 0x40, val);
190 if (pci_read_byte(dev, 0x40) != val) {
191 printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n",
199 static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
203 #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
204 #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
206 #define LOWER_ROM_ADDRESS_RANGE (1 << 0)
207 #define ROM_WRITE_ENABLE (1 << 1)
208 #define UPPER_ROM_ADDRESS_RANGE (1 << 2)
209 #define BIOS_ROM_POSITIVE_DECODE (1 << 5)
211 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
212 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
213 * Make the configured ROM areas writable.
215 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
216 reg8 |= LOWER_ROM_ADDRESS_RANGE;
217 reg8 |= UPPER_ROM_ADDRESS_RANGE;
218 reg8 |= ROM_WRITE_ENABLE;
219 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
221 /* Set positive decode on ROM. */
222 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
223 reg8 |= BIOS_ROM_POSITIVE_DECODE;
224 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
230 * Geode systems write protect the BIOS via RCONFs (cache settings similar
231 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and
232 * writing to MSRs, however requires instructions rdmsr/wrmsr, which are
233 * ring0 privileged instructions so only the kernel can do the read/write.
234 * This function, therefore, requires that the msr kernel module be loaded
235 * to access these instructions from user space using device /dev/cpu/0/msr.
237 * This hard-coded location could have potential problems on SMP machines
238 * since it assumes cpu0, but it is safe on the Geode which is not SMP.
240 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
241 * To enable write to NOR Boot flash for the benefit of systems that have such
242 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
244 * This is probably not portable beyond Linux.
246 static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
248 #define MSR_RCONF_DEFAULT 0x1808
249 #define MSR_NORF_CTL 0x51400018
252 unsigned char buf[8];
254 fd_msr = open("/dev/cpu/0/msr", O_RDWR);
260 if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
262 printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n");
267 if (read(fd_msr, buf, 8) != 8) {
273 if (buf[7] != 0x22) {
275 if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
281 if (write(fd_msr, buf, 8) < 0) {
288 if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
294 if (read(fd_msr, buf, 8) != 8) {
300 /* Raise WE_CS3 bit. */
303 if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
308 if (write(fd_msr, buf, 8) < 0) {
316 #undef MSR_RCONF_DEFAULT
321 static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
325 pci_write_byte(dev, 0x52, 0xee);
327 new = pci_read_byte(dev, 0x52);
330 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
337 static int enable_flash_sis5595(struct pci_dev *dev, const char *name)
341 new = pci_read_byte(dev, 0x45);
343 new &= (~0x20); /* Clear bit 5. */
344 new |= 0x4; /* Set bit 2. */
346 pci_write_byte(dev, 0x45, new);
348 newer = pci_read_byte(dev, 0x45);
350 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
351 printf("Stuck at 0x%x\n", newer);
358 static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
362 /* Enable decoding at 0xffb00000 to 0xffffffff. */
363 old = pci_read_byte(dev, 0x43);
366 pci_write_byte(dev, 0x43, new);
367 if (pci_read_byte(dev, 0x43) != new) {
368 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
372 old = pci_read_byte(dev, 0x40);
376 pci_write_byte(dev, 0x40, new);
378 if (pci_read_byte(dev, 0x40) != new) {
379 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
386 static int enable_flash_ck804(struct pci_dev *dev, const char *name)
390 old = pci_read_byte(dev, 0x88);
393 pci_write_byte(dev, 0x88, new);
394 if (pci_read_byte(dev, 0x88) != new) {
395 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
399 old = pci_read_byte(dev, 0x6d);
403 pci_write_byte(dev, 0x6d, new);
405 if (pci_read_byte(dev, 0x6d) != new) {
406 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
413 /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
414 static int enable_flash_sb400(struct pci_dev *dev, const char *name)
418 struct pci_dev *smbusdev;
420 /* Look for the SMBus device. */
421 pci_filter_init((struct pci_access *)0, &f);
425 for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
426 if (pci_filter_match(&f, smbusdev)) {
432 fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
436 /* Enable some SMBus stuff. */
437 tmp = pci_read_byte(smbusdev, 0x79);
439 pci_write_byte(smbusdev, 0x79, tmp);
441 /* Change southbridge. */
442 tmp = pci_read_byte(dev, 0x48);
444 pci_write_byte(dev, 0x48, tmp);
446 /* Now become a bit silly. */
458 static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
460 uint8_t old, new, byte;
463 /* Set the 0-16 MB enable bits. */
464 byte = pci_read_byte(dev, 0x88);
465 byte |= 0xff; /* 256K */
466 pci_write_byte(dev, 0x88, byte);
467 byte = pci_read_byte(dev, 0x8c);
468 byte |= 0xff; /* 1M */
469 pci_write_byte(dev, 0x8c, byte);
470 word = pci_read_word(dev, 0x90);
471 word |= 0x7fff; /* 16M */
472 pci_write_word(dev, 0x90, word);
474 old = pci_read_byte(dev, 0x6d);
478 pci_write_byte(dev, 0x6d, new);
480 if (pci_read_byte(dev, 0x6d) != new) {
482 ("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
490 static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
494 /* Set the 4MB enable bit. */
495 byte = pci_read_byte(dev, 0x41);
497 pci_write_byte(dev, 0x41, byte);
499 byte = pci_read_byte(dev, 0x43);
501 pci_write_byte(dev, 0x43, byte);
506 typedef struct penable {
507 uint16_t vendor, device;
509 int (*doit) (struct pci_dev *dev, const char *name);
512 static const FLASH_ENABLE enables[] = {
513 {0x1039, 0x0630, "SiS630", enable_flash_sis630},
514 {0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4},
515 {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4},
516 {0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e},
517 {0x8086, 0x2420, "Intel ICH0", enable_flash_ich_4e},
518 {0x8086, 0x2440, "Intel ICH2", enable_flash_ich_4e},
519 {0x8086, 0x244c, "Intel ICH2-M", enable_flash_ich_4e},
520 {0x8086, 0x2480, "Intel ICH3-S", enable_flash_ich_4e},
521 {0x8086, 0x248c, "Intel ICH3-M", enable_flash_ich_4e},
522 {0x8086, 0x24c0, "Intel ICH4/ICH4-L", enable_flash_ich_4e},
523 {0x8086, 0x24cc, "Intel ICH4-M", enable_flash_ich_4e},
524 {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e},
525 {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc},
526 {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc},
527 {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich_dc},
528 {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich_dc},
529 {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich_dc},
530 {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich_dc},
531 {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich_dc},
532 {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich_dc},
533 {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich_dc},
534 {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x},
535 {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x},
536 {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x},
537 {0x1106, 0x8324, "VIA CX700", enable_flash_vt823x},
538 {0x1106, 0x0686, "VIA VT82C686", enable_flash_amd8111},
539 {0x1078, 0x0100, "AMD CS5530(A)", enable_flash_cs5530},
540 {0x100b, 0x0510, "AMD SC1100", enable_flash_sc1100},
541 {0x1039, 0x0008, "SiS5595", enable_flash_sis5595},
542 {0x1022, 0x2080, "AMD CS5536", enable_flash_cs5536},
543 {0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
544 {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533},
545 {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */
546 {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */
547 /* Slave, should not be here, to fix known bug for A01. */
548 {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804},
549 {0x10de, 0x0260, "NVIDIA MCP51", enable_flash_ck804},
550 {0x10de, 0x0261, "NVIDIA MCP51", enable_flash_ck804},
551 {0x10de, 0x0262, "NVIDIA MCP51", enable_flash_ck804},
552 {0x10de, 0x0263, "NVIDIA MCP51", enable_flash_ck804},
553 {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI*/
554 {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
555 {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
556 {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
557 {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
558 {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
559 {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
560 {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
561 {0x1002, 0x4377, "ATI SB400", enable_flash_sb400},
562 {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000},
565 void print_supported_chipsets(void)
569 printf("\nSupported chipsets:\n\n");
571 for (i = 0; i < ARRAY_SIZE(enables); i++)
572 printf("%s (%04x:%04x)\n", enables[i].name,
573 enables[i].vendor, enables[i].device);
576 int chipset_flash_enable(void)
578 struct pci_dev *dev = 0;
579 int ret = -2; /* Nothing! */
582 /* Now let's try to find the chipset we have... */
583 for (i = 0; i < ARRAY_SIZE(enables); i++) {
584 dev = pci_dev_find(enables[i].vendor, enables[i].device);
590 printf("Found chipset \"%s\", enabling flash write... ",
593 ret = enables[i].doit(dev, enables[i].name);