2 * This file is part of the flashrom project.
4 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
6 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 * Contains the chipset specific flash enables.
26 #define _LARGEFILE64_SOURCE
31 #include <sys/types.h>
38 unsigned long flashbase = 0;
41 * flashrom defaults to LPC flash devices. If a known SPI controller is found
42 * and the SPI strappings are set, this will be overwritten by the probing code.
44 * Eventually, this will become an array when multiple flash support works.
47 flashbus_t flashbus = BUS_TYPE_LPC;
50 extern int ichspi_lock;
52 static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
57 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
58 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
60 tmp = pci_read_byte(dev, 0x47);
62 pci_write_byte(dev, 0x47, tmp);
67 static int enable_flash_sis630(struct pci_dev *dev, const char *name)
71 /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
72 b = pci_read_byte(dev, 0x40);
73 pci_write_byte(dev, 0x40, b | 0xb);
75 /* Flash write enable on SiS 540/630. */
76 b = pci_read_byte(dev, 0x45);
77 pci_write_byte(dev, 0x45, b | 0x40);
79 /* The same thing on SiS 950 Super I/O side... */
81 /* First probe for Super I/O on config port 0x2e. */
87 if (INB(0x2f) != 0x87) {
88 /* If that failed, try config port 0x4e. */
93 if (INB(0x4f) != 0x87) {
94 printf("Can not access SiS 950\n");
106 printf("2f is %#x\n", INB(0x2f));
107 b = INB(0x2f) | 0xfc;
118 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
119 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
120 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
121 * - Order Number: 290562-001
123 static int enable_flash_piix4(struct pci_dev *dev, const char *name)
126 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
128 old = pci_read_word(dev, xbcs);
130 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
131 * FFF00000-FFF7FFFF are forwarded to ISA).
132 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
133 * Set bit 7: Extended BIOS Enable (PCI master accesses to
134 * FFF80000-FFFDFFFF are forwarded to ISA).
135 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
136 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
137 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
138 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
139 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
140 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
142 if (dev->device_id == 0x122e || dev->device_id == 0x7000
143 || dev->device_id == 0x1234)
144 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
151 pci_write_word(dev, xbcs, new);
153 if (pci_read_word(dev, xbcs) != new) {
154 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
162 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
163 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
165 static int enable_flash_ich(struct pci_dev *dev, const char *name,
171 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
172 * just treating it as 8 bit wide seems to work fine in practice.
174 old = pci_read_byte(dev, bios_cntl);
176 printf_debug("\nBIOS Lock Enable: %sabled, ",
177 (old & (1 << 1)) ? "en" : "dis");
178 printf_debug("BIOS Write Enable: %sabled, ",
179 (old & (1 << 0)) ? "en" : "dis");
180 printf_debug("BIOS_CNTL is 0x%x\n", old);
187 pci_write_byte(dev, bios_cntl, new);
189 if (pci_read_byte(dev, bios_cntl) != new) {
190 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
197 static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
199 return enable_flash_ich(dev, name, 0x4e);
202 static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
204 return enable_flash_ich(dev, name, 0xdc);
207 #define ICH_STRAP_RSVD 0x00
208 #define ICH_STRAP_SPI 0x01
209 #define ICH_STRAP_PCI 0x02
210 #define ICH_STRAP_LPC 0x03
212 static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
216 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
217 printf_debug("MMIO base at = 0x%x\n", mmio_base);
218 spibar = mmap(NULL, 0x70, PROT_READ | PROT_WRITE, MAP_SHARED,
221 if (spibar == MAP_FAILED) {
222 perror("Can't mmap memory using " MEM_DEV);
226 printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n",
227 *(uint16_t *) (spibar + 0x6c));
229 flashbus = BUS_TYPE_VIA_SPI;
234 static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
238 uint8_t old, new, bbs, buc;
239 uint16_t spibar_offset, tmp2;
242 //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line
243 //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
244 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
246 /* Enable Flash Writes */
247 ret = enable_flash_ich_dc(dev, name);
249 /* Get physical address of Root Complex Register Block */
250 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
251 printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
253 /* Map RCBA to virtual memory */
254 rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem,
256 if (rcrb == MAP_FAILED) {
257 perror("Can't mmap memory using " MEM_DEV);
261 gcs = *(volatile uint32_t *)(rcrb + 0x3410);
262 printf_debug("GCS = 0x%x: ", gcs);
263 printf_debug("BIOS Interface Lock-Down: %sabled, ",
264 (gcs & 0x1) ? "en" : "dis");
265 bbs = (gcs >> 10) & 0x3;
266 printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
268 buc = *(volatile uint8_t *)(rcrb + 0x3414);
269 printf_debug("Top Swap : %s\n",
270 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
272 /* It seems the ICH7 does not support SPI and LPC chips at the same
273 * time. At least not with our current code. So we prevent searching
274 * on ICH7 when the southbridge is strapped to LPC
277 if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
278 /* No further SPI initialization required */
282 switch (ich_generation) {
284 flashbus = BUS_TYPE_ICH7_SPI;
285 spibar_offset = 0x3020;
288 flashbus = BUS_TYPE_ICH9_SPI;
289 spibar_offset = 0x3020;
293 default: /* Future version might behave the same */
294 flashbus = BUS_TYPE_ICH9_SPI;
295 spibar_offset = 0x3800;
299 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
300 printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
302 /* Assign Virtual Address */
303 spibar = rcrb + spibar_offset;
306 case BUS_TYPE_ICH7_SPI:
307 printf_debug("0x00: 0x%04x (SPIS)\n",
308 *(uint16_t *) (spibar + 0));
309 printf_debug("0x02: 0x%04x (SPIC)\n",
310 *(uint16_t *) (spibar + 2));
311 printf_debug("0x04: 0x%08x (SPIA)\n",
312 *(uint32_t *) (spibar + 4));
313 for (i = 0; i < 8; i++) {
316 printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs,
317 *(uint32_t *) (spibar + offs), i);
318 printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
319 *(uint32_t *) (spibar + offs + 4), i);
321 printf_debug("0x50: 0x%08x (BBAR)\n",
322 *(uint32_t *) (spibar + 0x50));
323 printf_debug("0x54: 0x%04x (PREOP)\n",
324 *(uint16_t *) (spibar + 0x54));
325 printf_debug("0x56: 0x%04x (OPTYPE)\n",
326 *(uint16_t *) (spibar + 0x56));
327 printf_debug("0x58: 0x%08x (OPMENU)\n",
328 *(uint32_t *) (spibar + 0x58));
329 printf_debug("0x5c: 0x%08x (OPMENU+4)\n",
330 *(uint32_t *) (spibar + 0x5c));
331 for (i = 0; i < 4; i++) {
333 offs = 0x60 + (i * 4);
334 printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs,
335 *(uint32_t *) (spibar + offs), i);
338 if ((*(uint16_t *) spibar) & (1 << 15)) {
339 printf("WARNING: SPI Configuration Lockdown activated.\n");
344 case BUS_TYPE_ICH9_SPI:
345 tmp2 = *(uint16_t *) (spibar + 4);
346 printf_debug("0x04: 0x%04x (HSFS)\n", tmp2);
347 printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1));
348 printf_debug("FDV %i, ", (tmp2 >> 14) & 1);
349 printf_debug("FDOPSS %i, ", (tmp2 >> 13) & 1);
350 printf_debug("SCIP %i, ", (tmp2 >> 5) & 1);
351 printf_debug("BERASE %i, ", (tmp2 >> 3) & 3);
352 printf_debug("AEL %i, ", (tmp2 >> 2) & 1);
353 printf_debug("FCERR %i, ", (tmp2 >> 1) & 1);
354 printf_debug("FDONE %i\n", (tmp2 >> 0) & 1);
356 tmp = *(uint32_t *) (spibar + 0x50);
357 printf_debug("0x50: 0x%08x (FRAP)\n", tmp);
358 printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff);
359 printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff);
360 printf_debug("BRWA %i, ", (tmp >> 8) & 0xff);
361 printf_debug("BRRA %i\n", (tmp >> 0) & 0xff);
363 printf_debug("0x54: 0x%08x (FREG0)\n",
364 *(uint32_t *) (spibar + 0x54));
365 printf_debug("0x58: 0x%08x (FREG1)\n",
366 *(uint32_t *) (spibar + 0x58));
367 printf_debug("0x5C: 0x%08x (FREG2)\n",
368 *(uint32_t *) (spibar + 0x5C));
369 printf_debug("0x60: 0x%08x (FREG3)\n",
370 *(uint32_t *) (spibar + 0x60));
371 printf_debug("0x64: 0x%08x (FREG4)\n",
372 *(uint32_t *) (spibar + 0x64));
373 printf_debug("0x74: 0x%08x (PR0)\n",
374 *(uint32_t *) (spibar + 0x74));
375 printf_debug("0x78: 0x%08x (PR1)\n",
376 *(uint32_t *) (spibar + 0x78));
377 printf_debug("0x7C: 0x%08x (PR2)\n",
378 *(uint32_t *) (spibar + 0x7C));
379 printf_debug("0x80: 0x%08x (PR3)\n",
380 *(uint32_t *) (spibar + 0x80));
381 printf_debug("0x84: 0x%08x (PR4)\n",
382 *(uint32_t *) (spibar + 0x84));
383 printf_debug("0x90: 0x%08x (SSFS, SSFC)\n",
384 *(uint32_t *) (spibar + 0x90));
385 printf_debug("0x94: 0x%04x (PREOP)\n",
386 *(uint16_t *) (spibar + 0x94));
387 printf_debug("0x96: 0x%04x (OPTYPE)\n",
388 *(uint16_t *) (spibar + 0x96));
389 printf_debug("0x98: 0x%08x (OPMENU)\n",
390 *(uint32_t *) (spibar + 0x98));
391 printf_debug("0x9C: 0x%08x (OPMENU+4)\n",
392 *(uint32_t *) (spibar + 0x9C));
393 printf_debug("0xA0: 0x%08x (BBAR)\n",
394 *(uint32_t *) (spibar + 0xA0));
395 printf_debug("0xB0: 0x%08x (FDOC)\n",
396 *(uint32_t *) (spibar + 0xB0));
397 if (tmp2 & (1 << 15)) {
398 printf("WARNING: SPI Configuration Lockdown activated.\n");
408 old = pci_read_byte(dev, 0xdc);
409 printf_debug("SPI Read Configuration: ");
410 new = (old >> 2) & 0x3;
415 printf_debug("prefetching %sabled, caching %sabled, ",
416 (new & 0x2) ? "en" : "dis",
417 (new & 0x1) ? "dis" : "en");
420 printf_debug("invalid prefetching/caching settings, ");
427 static int enable_flash_ich7(struct pci_dev *dev, const char *name)
429 return enable_flash_ich_dc_spi(dev, name, 7);
432 static int enable_flash_ich8(struct pci_dev *dev, const char *name)
434 return enable_flash_ich_dc_spi(dev, name, 8);
437 static int enable_flash_ich9(struct pci_dev *dev, const char *name)
439 return enable_flash_ich_dc_spi(dev, name, 9);
442 static int enable_flash_ich10(struct pci_dev *dev, const char *name)
444 return enable_flash_ich_dc_spi(dev, name, 10);
447 static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
451 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
452 pci_write_byte(dev, 0x41, 0x7f);
454 /* ROM write enable */
455 val = pci_read_byte(dev, 0x40);
457 pci_write_byte(dev, 0x40, val);
459 if (pci_read_byte(dev, 0x40) != val) {
460 printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n",
468 static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
472 #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
473 #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
475 #define LOWER_ROM_ADDRESS_RANGE (1 << 0)
476 #define ROM_WRITE_ENABLE (1 << 1)
477 #define UPPER_ROM_ADDRESS_RANGE (1 << 2)
478 #define BIOS_ROM_POSITIVE_DECODE (1 << 5)
480 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
481 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
482 * Make the configured ROM areas writable.
484 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
485 reg8 |= LOWER_ROM_ADDRESS_RANGE;
486 reg8 |= UPPER_ROM_ADDRESS_RANGE;
487 reg8 |= ROM_WRITE_ENABLE;
488 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
490 /* Set positive decode on ROM. */
491 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
492 reg8 |= BIOS_ROM_POSITIVE_DECODE;
493 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
499 * Geode systems write protect the BIOS via RCONFs (cache settings similar
500 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and
501 * writing to MSRs, however requires instructions rdmsr/wrmsr, which are
502 * ring0 privileged instructions so only the kernel can do the read/write.
503 * This function, therefore, requires that the msr kernel module be loaded
504 * to access these instructions from user space using device /dev/cpu/0/msr.
506 * This hard-coded location could have potential problems on SMP machines
507 * since it assumes cpu0, but it is safe on the Geode which is not SMP.
509 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
510 * To enable write to NOR Boot flash for the benefit of systems that have such
511 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
513 * This is probably not portable beyond Linux.
515 static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
517 #define MSR_RCONF_DEFAULT 0x1808
518 #define MSR_NORF_CTL 0x51400018
521 unsigned char buf[8];
523 fd_msr = open("/dev/cpu/0/msr", O_RDWR);
529 if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
531 printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n");
536 if (read(fd_msr, buf, 8) != 8) {
542 if (buf[7] != 0x22) {
544 if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT,
551 if (write(fd_msr, buf, 8) < 0) {
558 if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
564 if (read(fd_msr, buf, 8) != 8) {
570 /* Raise WE_CS3 bit. */
573 if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
578 if (write(fd_msr, buf, 8) < 0) {
586 #undef MSR_RCONF_DEFAULT
591 static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
595 pci_write_byte(dev, 0x52, 0xee);
597 new = pci_read_byte(dev, 0x52);
600 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
607 static int enable_flash_sis5595(struct pci_dev *dev, const char *name)
611 new = pci_read_byte(dev, 0x45);
613 new &= (~0x20); /* Clear bit 5. */
614 new |= 0x4; /* Set bit 2. */
616 pci_write_byte(dev, 0x45, new);
618 newer = pci_read_byte(dev, 0x45);
620 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
621 printf("Stuck at 0x%x\n", newer);
625 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
626 new = pci_read_byte(dev, 0x40);
629 pci_write_byte(dev, 0x40, new);
630 newer = pci_read_byte(dev, 0x40);
632 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
633 printf("Stuck at 0x%x\n", newer);
639 /* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
640 static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
644 /* Enable decoding at 0xffb00000 to 0xffffffff. */
645 old = pci_read_byte(dev, 0x43);
648 pci_write_byte(dev, 0x43, new);
649 if (pci_read_byte(dev, 0x43) != new) {
650 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
654 /* Enable 'ROM write' bit. */
655 old = pci_read_byte(dev, 0x40);
659 pci_write_byte(dev, 0x40, new);
661 if (pci_read_byte(dev, 0x40) != new) {
662 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
669 static int enable_flash_sb600(struct pci_dev *dev, const char *name)
671 uint32_t tmp, low_bits, num;
674 low_bits = tmp = pci_read_long(dev, 0xa0);
675 low_bits &= ~0xffffc000; /* for mmap aligning requirements */
676 low_bits &= 0xfffffff0; /* remove low 4 bits */
678 printf_debug("SPI base address is at 0x%x\n", tmp + low_bits);
680 sb600_spibar = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED,
682 if (sb600_spibar == MAP_FAILED) {
683 perror("Can't mmap memory using " MEM_DEV);
686 sb600_spibar += low_bits;
688 /* Clear ROM protect 0-3. */
689 for (reg = 0x50; reg < 0x60; reg += 4) {
690 num = pci_read_long(dev, reg);
692 pci_write_byte(dev, reg, num);
695 flashbus = BUS_TYPE_SB600_SPI;
697 /* Enable SPI ROM in SB600 PM register. */
704 static int enable_flash_ck804(struct pci_dev *dev, const char *name)
708 old = pci_read_byte(dev, 0x88);
711 pci_write_byte(dev, 0x88, new);
712 if (pci_read_byte(dev, 0x88) != new) {
713 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
717 old = pci_read_byte(dev, 0x6d);
721 pci_write_byte(dev, 0x6d, new);
723 if (pci_read_byte(dev, 0x6d) != new) {
724 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
731 /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
732 static int enable_flash_sb400(struct pci_dev *dev, const char *name)
736 struct pci_dev *smbusdev;
738 /* Look for the SMBus device. */
739 pci_filter_init((struct pci_access *)0, &f);
743 for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
744 if (pci_filter_match(&f, smbusdev))
749 fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
753 /* Enable some SMBus stuff. */
754 tmp = pci_read_byte(smbusdev, 0x79);
756 pci_write_byte(smbusdev, 0x79, tmp);
758 /* Change southbridge. */
759 tmp = pci_read_byte(dev, 0x48);
761 pci_write_byte(dev, 0x48, tmp);
763 /* Now become a bit silly. */
775 static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
777 uint8_t old, new, byte;
780 /* Set the 0-16 MB enable bits. */
781 byte = pci_read_byte(dev, 0x88);
782 byte |= 0xff; /* 256K */
783 pci_write_byte(dev, 0x88, byte);
784 byte = pci_read_byte(dev, 0x8c);
785 byte |= 0xff; /* 1M */
786 pci_write_byte(dev, 0x8c, byte);
787 word = pci_read_word(dev, 0x90);
788 word |= 0x7fff; /* 16M */
789 pci_write_word(dev, 0x90, word);
791 old = pci_read_byte(dev, 0x6d);
795 pci_write_byte(dev, 0x6d, new);
797 if (pci_read_byte(dev, 0x6d) != new) {
798 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
805 static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
809 /* Set the 4MB enable bit. */
810 byte = pci_read_byte(dev, 0x41);
812 pci_write_byte(dev, 0x41, byte);
814 byte = pci_read_byte(dev, 0x43);
816 pci_write_byte(dev, 0x43, byte);
822 * Usually on the x86 architectures (and on other PC-like platforms like some
823 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
824 * Elan SC520 only a small piece of the system flash is mapped there, but the
825 * complete flash is mapped somewhere below 1G. The position can be determined
826 * by the BOOTCS PAR register.
828 static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
830 int i, bootcs_found = 0;
835 mmcr = mmap(0, getpagesize(), PROT_WRITE | PROT_READ,
836 MAP_SHARED, fd_mem, (off_t)0xFFFEF000);
838 if (mmcr == MAP_FAILED) {
839 perror("Can't mmap Elan SC520 specific registers using " MEM_DEV);
843 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
844 * BOOTCS region (PARx[31:29] = 100b)e
846 for (i = 0x88; i <= 0xc4; i += 4) {
847 parx = *(volatile uint32_t *)(mmcr + i);
848 if ((parx >> 29) == 4) {
850 break; /* BOOTCS found */
854 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
855 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
858 if (parx & (1 << 25)) {
859 parx &= (1 << 14) - 1; /* Mask [13:0] */
860 flashbase = parx << 16;
862 parx &= (1 << 18) - 1; /* Mask [17:0] */
863 flashbase = parx << 12;
866 printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
870 munmap (mmcr, getpagesize());
874 typedef struct penable {
875 uint16_t vendor, device;
877 int (*doit) (struct pci_dev *dev, const char *name);
880 static const FLASH_ENABLE enables[] = {
881 {0x1039, 0x0630, "SiS630", enable_flash_sis630},
882 {0x8086, 0x122e, "Intel PIIX", enable_flash_piix4},
883 {0x8086, 0x1234, "Intel MPIIX", enable_flash_piix4},
884 {0x8086, 0x7000, "Intel PIIX3", enable_flash_piix4},
885 {0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4},
886 {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4},
887 {0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e},
888 {0x8086, 0x2420, "Intel ICH0", enable_flash_ich_4e},
889 {0x8086, 0x2440, "Intel ICH2", enable_flash_ich_4e},
890 {0x8086, 0x244c, "Intel ICH2-M", enable_flash_ich_4e},
891 {0x8086, 0x2480, "Intel ICH3-S", enable_flash_ich_4e},
892 {0x8086, 0x248c, "Intel ICH3-M", enable_flash_ich_4e},
893 {0x8086, 0x24c0, "Intel ICH4/ICH4-L", enable_flash_ich_4e},
894 {0x8086, 0x24cc, "Intel ICH4-M", enable_flash_ich_4e},
895 {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e},
896 {0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e},
897 {0x8086, 0x2670, "Intel 631xESB/632xESB/3100", enable_flash_ich_dc},
898 {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc},
899 {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc},
900 {0x8086, 0x5031, "Intel EP80579", enable_flash_ich7},
901 {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich7},
902 {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich7},
903 {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich7},
904 {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich7},
905 {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich8},
906 {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich8},
907 {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich8},
908 {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich8},
909 {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich8},
910 {0x8086, 0x2912, "Intel ICH9DH", enable_flash_ich9},
911 {0x8086, 0x2914, "Intel ICH9DO", enable_flash_ich9},
912 {0x8086, 0x2916, "Intel ICH9R", enable_flash_ich9},
913 {0x8086, 0x2917, "Intel ICH9M-E", enable_flash_ich9},
914 {0x8086, 0x2918, "Intel ICH9", enable_flash_ich9},
915 {0x8086, 0x2919, "Intel ICH9M", enable_flash_ich9},
916 {0x8086, 0x3a14, "Intel ICH10DO", enable_flash_ich10},
917 {0x8086, 0x3a16, "Intel ICH10R", enable_flash_ich10},
918 {0x8086, 0x3a18, "Intel ICH10", enable_flash_ich10},
919 {0x8086, 0x3a1a, "Intel ICH10D", enable_flash_ich10},
920 {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x},
921 {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x},
922 {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x},
923 {0x1106, 0x3372, "VIA VT8237S", enable_flash_vt8237s_spi},
924 {0x1106, 0x8324, "VIA CX700", enable_flash_vt823x},
925 {0x1106, 0x0586, "VIA VT82C586A/B", enable_flash_amd8111},
926 {0x1106, 0x0686, "VIA VT82C686A/B", enable_flash_amd8111},
927 {0x1078, 0x0100, "AMD CS5530(A)", enable_flash_cs5530},
928 {0x100b, 0x0510, "AMD SC1100", enable_flash_sc1100},
929 {0x1039, 0x0008, "SiS5595", enable_flash_sis5595},
930 {0x1022, 0x2080, "AMD CS5536", enable_flash_cs5536},
931 {0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
932 {0x1002, 0x438D, "ATI(AMD) SB600", enable_flash_sb600},
933 {0x1002, 0x439d, "ATI(AMD) SB700", enable_flash_sb600},
934 {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533},
935 {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */
936 {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */
937 /* Slave, should not be here, to fix known bug for A01. */
938 {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804},
939 {0x10de, 0x0260, "NVIDIA MCP51", enable_flash_ck804},
940 {0x10de, 0x0261, "NVIDIA MCP51", enable_flash_ck804},
941 {0x10de, 0x0262, "NVIDIA MCP51", enable_flash_ck804},
942 {0x10de, 0x0263, "NVIDIA MCP51", enable_flash_ck804},
943 {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI*/
944 {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
945 {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
946 {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
947 {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
948 {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
949 {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
950 {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
951 {0x10de, 0x0548, "NVIDIA MCP67", enable_flash_mcp55},
952 {0x1002, 0x4377, "ATI SB400", enable_flash_sb400},
953 {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000},
954 {0x1022, 0x3000, "AMD Elan SC520", get_flashbase_sc520},
955 {0x1022, 0x7440, "AMD AMD-768", enable_flash_amd8111},
958 void print_supported_chipsets(void)
962 printf("\nSupported chipsets:\n\n");
964 for (i = 0; i < ARRAY_SIZE(enables); i++)
965 printf("%s (%04x:%04x)\n", enables[i].name,
966 enables[i].vendor, enables[i].device);
969 int chipset_flash_enable(void)
971 struct pci_dev *dev = 0;
972 int ret = -2; /* Nothing! */
975 /* Now let's try to find the chipset we have... */
976 for (i = 0; i < ARRAY_SIZE(enables); i++) {
977 dev = pci_dev_find(enables[i].vendor, enables[i].device);
983 printf("Found chipset \"%s\", enabling flash write... ",
986 ret = enables[i].doit(dev, enables[i].name);