2 ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
5 Copyright (C) 2009 Bernhard Urban <lewurm@gmx.net>
6 Copyright (C) 2009 Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
8 # This code is licensed to you under the terms of the GNU GPL, version 2;
9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
15 #include "../../types.h"
17 /* stolen from drivers/usb/host/ohci.h (linux-kernel) :) */
19 /* OHCI CONTROL AND STATUS REGISTER MASKS */
22 * HcControl (control) register masks
24 #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
25 #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
26 #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
27 #define OHCI_CTRL_CLE (1 << 4) /* control list enable */
28 #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
29 #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
30 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
31 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
32 #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
34 /* pre-shifted values for HCFS */
35 #define OHCI_USB_RESET (0 << 6)
36 #define OHCI_USB_RESUME (1 << 6)
37 #define OHCI_USB_OPER (2 << 6)
38 #define OHCI_USB_SUSPEND (3 << 6)
41 * HcCommandStatus (cmdstatus) register masks
43 #define OHCI_HCR (1 << 0) /* host controller reset */
44 #define OHCI_CLF (1 << 1) /* control list filled */
45 #define OHCI_BLF (1 << 2) /* bulk list filled */
46 #define OHCI_OCR (1 << 3) /* ownership change request */
47 #define OHCI_SOC (3 << 16) /* scheduling overrun count */
50 * masks used with interrupt registers:
51 * HcInterruptStatus (intrstatus)
52 * HcInterruptEnable (intrenable)
53 * HcInterruptDisable (intrdisable)
55 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
56 #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
57 #define OHCI_INTR_SF (1 << 2) /* start frame */
58 #define OHCI_INTR_RD (1 << 3) /* resume detect */
59 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
60 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
61 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
62 #define OHCI_INTR_OC (1 << 30) /* ownership change */
63 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
65 /* For initializing controller (mask in an HCFS mode too) */
66 #define OHCI_CONTROL_INIT (3 << 0)
67 #define OHCI_INTR_INIT \
68 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE)
70 /* OHCI ROOT HUB REGISTER MASKS */
72 /* roothub.portstatus [i] bits */
73 #define RH_PS_CCS 0x00000001 /* current connect status */
74 #define RH_PS_PES 0x00000002 /* port enable status*/
75 #define RH_PS_PSS 0x00000004 /* port suspend status */
76 #define RH_PS_POCI 0x00000008 /* port over current indicator */
77 #define RH_PS_PRS 0x00000010 /* port reset status */
78 #define RH_PS_PPS 0x00000100 /* port power status */
79 #define RH_PS_LSDA 0x00000200 /* low speed device attached */
80 #define RH_PS_CSC 0x00010000 /* connect status change */
81 #define RH_PS_PESC 0x00020000 /* port enable status change */
82 #define RH_PS_PSSC 0x00040000 /* port suspend status change */
83 #define RH_PS_OCIC 0x00080000 /* over current indicator change */
84 #define RH_PS_PRSC 0x00100000 /* port reset status change */
86 /* roothub.status bits */
87 #define RH_HS_LPS 0x00000001 /* local power status */
88 #define RH_HS_OCI 0x00000002 /* over current indicator */
89 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
90 #define RH_HS_LPSC 0x00010000 /* local power status change */
91 #define RH_HS_OCIC 0x00020000 /* over current indicator change */
92 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
95 #define RH_B_DR 0x0000ffff /* device removable flags */
96 #define RH_B_PPCM 0xffff0000 /* port power control mask */
99 #define RH_A_NDP (0xff << 0) /* number of downstream ports */
100 #define RH_A_PSM (1 << 8) /* power switching mode */
101 #define RH_A_NPS (1 << 9) /* no power switching */
102 #define RH_A_DT (1 << 10) /* device type (mbz) */
103 #define RH_A_OCPM (1 << 11) /* over current protection mode */
104 #define RH_A_NOCP (1 << 12) /* no over current protection */
105 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
109 u32 int_table[NUM_INITS]; /* periodic schedule */
111 * OHCI defines u16 frame_no, followed by u16 zero pad.
112 * Since some processors can't do 16 bit bus accesses,
113 * portable access must be a 32 bits wide.
115 u32 frame_no; /* current frame number */
116 u32 done_head; /* info returned for an interrupt */
117 u8 reserved_for_hc [116];
118 u8 what [4]; /* spec only identifies 252 bytes :) */
121 struct endpoint_descriptor {
128 /* required by software */
132 #define OHCI_ENDPOINT_ADDRESS_MASK 0x0000007f
133 #define OHCI_ENDPOINT_GET_DEVICE_ADDRESS(s) ((s) & 0x7f)
134 #define OHCI_ENDPOINT_SET_DEVICE_ADDRESS(s) (s)
135 #define OHCI_ENDPOINT_GET_ENDPOINT_NUMBER(s) (((s) >> 7) & 0xf)
136 #define OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(s) ((s) << 7)
137 #define OHCI_ENDPOINT_DIRECTION_MASK 0x00001800
138 #define OHCI_ENDPOINT_DIRECTION_DESCRIPTOR 0x00000000
139 #define OHCI_ENDPOINT_DIRECTION_OUT 0x00000800
140 #define OHCI_ENDPOINT_DIRECTION_IN 0x00001000
141 #define OHCI_ENDPOINT_LOW_SPEED 0x00002000
142 #define OHCI_ENDPOINT_FULL_SPEED 0x00000000
143 #define OHCI_ENDPOINT_SKIP 0x00004000
144 #define OHCI_ENDPOINT_GENERAL_FORMAT 0x00000000
145 #define OHCI_ENDPOINT_ISOCHRONOUS_FORMAT 0x00008000
146 #define OHCI_ENDPOINT_MAX_PACKET_SIZE_MASK (0x7ff << 16)
147 #define OHCI_ENDPOINT_GET_MAX_PACKET_SIZE(s) (((s) >> 16) & 0x07ff)
148 #define OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(s) ((s) << 16)
149 #define OHCI_ENDPOINT_HALTED 0x00000001
150 #define OHCI_ENDPOINT_TOGGLE_CARRY 0x00000002
151 #define OHCI_ENDPOINT_HEAD_MASK 0xfffffffc
161 /* required by software */
168 #define OHCI_TD_BUFFER_ROUNDING 0x00040000
169 #define OHCI_TD_DIRECTION_PID_MASK 0x00180000
170 #define OHCI_TD_DIRECTION_PID_SETUP 0x00000000
171 #define OHCI_TD_DIRECTION_PID_OUT 0x00080000
172 #define OHCI_TD_DIRECTION_PID_IN 0x00100000
173 #define OHCI_TD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7)
174 #define OHCI_TD_SET_DELAY_INTERRUPT(x) ((x) << 21)
175 #define OHCI_TD_INTERRUPT_MASK 0x00e00000
176 #define OHCI_TD_TOGGLE_CARRY 0x00000000
177 #define OHCI_TD_TOGGLE_0 0x02000000
178 #define OHCI_TD_TOGGLE_1 0x03000000
179 #define OHCI_TD_TOGGLE_MASK 0x03000000
180 #define OHCI_TD_GET_ERROR_COUNT(x) (((x) >> 26) & 3)
181 #define OHCI_TD_GET_CONDITION_CODE(x) ((x) >> 28)
182 #define OHCI_TD_SET_CONDITION_CODE(x) ((x) << 28)
183 #define OHCI_TD_CONDITION_CODE_MASK 0xf0000000
185 #define OHCI_TD_INTERRUPT_IMMEDIATE 0x00
186 #define OHCI_TD_INTERRUPT_NONE 0x07
188 #define OHCI_TD_CONDITION_NO_ERROR 0x00
189 #define OHCI_TD_CONDITION_CRC_ERROR 0x01
190 #define OHCI_TD_CONDITION_BIT_STUFFING 0x02
191 #define OHCI_TD_CONDITION_TOGGLE_MISMATCH 0x03
192 #define OHCI_TD_CONDITION_STALL 0x04
193 #define OHCI_TD_CONDITION_NO_RESPONSE 0x05
194 #define OHCI_TD_CONDITION_PID_CHECK_FAILURE 0x06
195 #define OHCI_TD_CONDITION_UNEXPECTED_PID 0x07
196 #define OHCI_TD_CONDITION_DATA_OVERRUN 0x08
197 #define OHCI_TD_CONDITION_DATA_UNDERRUN 0x09
198 #define OHCI_TD_CONDITION_BUFFER_OVERRUN 0x0c
199 #define OHCI_TD_CONDITION_BUFFER_UNDERRUN 0x0d
200 #define OHCI_TD_CONDITION_NOT_ACCESSED 0x0f