2 ppcskel - a Free Software replacement for the Nintendo/BroadOn bootloader.
5 Copyright (C) 2009 Bernhard Urban <lewurm@gmx.net>
6 Copyright (C) 2009 Sebastian Falbesoner <sebastian.falbesoner@gmail.com>
8 # This code is licensed to you under the terms of the GNU GPL, version 2;
9 # see file COPYING or http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
12 #include "../../bootmii_ppc.h"
13 #include "../../hollywood.h"
14 #include "../../irq.h"
15 #include "../../string.h"
16 #include "../../malloc.h"
19 #include "../usbspec/usb11spec.h"
21 /* activate control_quirk (from MIKE) */
24 /* macro for accessing u32 variables that need to be in little endian byte order;
26 * whenever you read or write from an u32 field that the ohci host controller
27 * will read or write from too, use this macro for access!
29 #define LE(dword) (u32)( (((dword) & 0xFF000000) >> 24) | \
30 (((dword) & 0x00FF0000) >> 8) | \
31 (((dword) & 0x0000FF00) << 8) | \
32 (((dword) & 0x000000FF) << 24) )
34 static struct general_td *allocate_general_td();
35 static void dbg_op_state();
36 static void configure_ports(u8 from_init);
37 static void setup_port(u32 reg, u8 from_init);
39 static struct ohci_hcca hcca_oh0;
43 static struct endpoint_descriptor *allocate_endpoint()
45 struct endpoint_descriptor *ep;
46 ep = (struct endpoint_descriptor *)memalign(16, sizeof(struct endpoint_descriptor));
47 memset(ep, 0, sizeof(struct endpoint_descriptor));
48 ep->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
49 ep->headp = ep->tailp = ep->nexted = LE(0);
54 static struct general_td *allocate_general_td()
56 struct general_td *td;
57 td = (struct general_td *)memalign(16, sizeof(struct general_td));
58 memset(td, 0, sizeof(struct general_td));
61 td->cbp = td->be = LE(0);
66 static void control_quirk()
68 static struct endpoint_descriptor *ed = 0; /* empty ED */
69 static struct general_td *td = 0; /* dummy TD */
76 * Allocate and keep a special empty ED with just a dummy TD.
79 ed = allocate_endpoint();
83 td = allocate_general_td(0);
90 ed->tailp = ed->headp = LE(virt_to_phys((void*) ((u32)td & OHCI_ENDPOINT_HEAD_MASK)));
91 ed->flags |= LE(OHCI_ENDPOINT_DIRECTION_OUT);
95 * The OHCI USB host controllers on the Nintendo Wii
96 * video game console stop working when new TDs are
97 * added to a scheduled control ED after a transfer has
98 * has taken place on it.
100 * Before scheduling any new control TD, we make the
101 * controller happy by always loading a special control ED
102 * with a single dummy TD and letting the controller attempt
104 * The controller won't do anything with it, as the special
105 * ED has no TDs, but it will keep the controller from failing
106 * on the next transfer.
108 head = read32(OHCI0_HC_CTRL_HEAD_ED);
110 printf("head: 0x%08X\n", head);
112 * Load the special empty ED and tell the controller to
113 * process the control list.
115 sync_after_write(ed, 16);
116 sync_after_write(td, 16);
117 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(ed));
119 status = read32(OHCI0_HC_CONTROL);
120 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
121 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
123 /* spin until the controller is done with the control list */
124 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
127 current = read32(OHCI0_HC_CTRL_CURRENT_ED);
130 printf("current: 0x%08X\n", current);
132 /* restore the old control head and control settings */
133 write32(OHCI0_HC_CONTROL, status);
134 write32(OHCI0_HC_CTRL_HEAD_ED, head);
142 static void dbg_op_state()
144 switch (read32(OHCI0_HC_CONTROL) & OHCI_CTRL_HCFS) {
145 case OHCI_USB_SUSPEND:
146 printf("ohci-- OHCI_USB_SUSPEND\n");
149 printf("ohci-- OHCI_USB_RESET\n");
152 printf("ohci-- OHCI_USB_OPER\n");
154 case OHCI_USB_RESUME:
155 printf("ohci-- OHCI_USB_RESUME\n");
160 static void dbg_td_flag(u32 flag)
162 printf("**************** dbg_td_flag: 0x%08X ***************\n", flag);
163 printf("CC: %X\tshould be 0, see page 32 (ohci spec)\n", (flag>>28)&0xf);
164 printf("EC: %X\tsee page 20 (ohci spec)\n", (flag>>26)&3);
165 printf(" T: %X\n", (flag>>24)&3);
166 printf("DI: %X\n", (flag>>21)&7);
167 printf("DP: %X\n", (flag>>19)&3);
168 printf(" R: %X\n", (flag>>18)&1);
169 printf("********************************************************\n");
172 static void general_td_fill(struct general_td *dest, const usb_transfer_descriptor *src)
175 dest->cbp = LE(virt_to_phys(src->buffer));
176 dest->be = LE(LE(dest->cbp) + src->actlen - 1);
177 /* save virtual address here */
178 dest->bufaddr = (u32) src->buffer;
181 dest->cbp = dest->be = LE(0);
185 dest->buflen = src->actlen;
187 dest->flags &= LE(~OHCI_TD_DIRECTION_PID_MASK);
190 printf("pid_setup\n");
191 dest->flags |= LE(OHCI_TD_DIRECTION_PID_SETUP);
192 dest->flags |= LE(OHCI_TD_TOGGLE_0);
193 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
197 dest->flags |= LE(OHCI_TD_DIRECTION_PID_OUT);
198 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
201 * TODO: just temporary solution! (consider it with len?)
202 * there can be also regular PID_OUT pakets
204 dest->flags |= LE(OHCI_TD_TOGGLE_1);
208 dest->flags |= LE(OHCI_TD_DIRECTION_PID_IN);
209 if(src->maxp > src->actlen) {
210 dest->flags |= LE(OHCI_TD_BUFFER_ROUNDING);
211 printf("round buffer!\n");
214 * let the endpoint do the togglestuff!
215 * TODO: just temporary solution!
216 * there can be also inregular PID_IN pakets (@Status Stage)
218 dest->flags |= LE(OHCI_TD_TOGGLE_CARRY);
221 dest->flags |= LE(OHCI_TD_SET_DELAY_INTERRUPT(7));
225 static void dump_address(void *addr, u32 size, const char* str)
227 printf("%s hexdump (%d) @ 0x%08X:\n", str, size, addr);
232 static struct endpoint_descriptor _edhead;
233 struct endpoint_descriptor *edhead = 0;
237 printf("<^> <^> <^> hcdi_fire(start)\n");
244 required? YES! :O ... erm... or no? :/ ... in fact I have no idea
248 write32(OHCI0_HC_CTRL_HEAD_ED, virt_to_phys(edhead));
251 sync_after_write(edhead, sizeof(struct endpoint_descriptor));
253 dump_address(edhead, sizeof(struct endpoint_descriptor), "edhead(before)");
256 struct general_td *x = phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
257 while(virt_to_phys(x)) {
258 sync_after_write(x, sizeof(struct general_td));
260 dump_address(x, sizeof(struct general_td), "x(before)");
264 sync_after_write((void*) phys_to_virt(LE(x->cbp)), x->buflen);
266 dump_address((void*) phys_to_virt(LE(x->cbp)), x->buflen, "x->cbp(before)");
269 x = phys_to_virt(LE(x->nexttd));
272 /* trigger control list */
273 set32(OHCI0_HC_CONTROL, OHCI_CTRL_CLE);
274 write32(OHCI0_HC_COMMAND_STATUS, OHCI_CLF);
276 struct general_td *n=0, *prev = 0, *next = 0;
277 /* poll until edhead->headp is null */
279 sync_before_read(edhead, sizeof(struct endpoint_descriptor));
281 printf("edhead->headp: 0x%08X\n", LE(edhead->headp));
285 /* if halted, debug output plz. will break the transfer */
286 if((LE(edhead->headp) & OHCI_ENDPOINT_HALTED)) {
287 n = phys_to_virt(LE(edhead->headp)&~0xf);
288 prev = phys_to_virt((u32)prev);
293 sync_before_read((void*) n, sizeof(struct general_td));
295 printf("n: 0x%08X\n", n);
296 dump_address(n, sizeof(struct general_td), "n(after)");
299 sync_before_read((void*) n->bufaddr, n->buflen);
301 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
304 dbg_td_flag(LE(n->flags));
306 sync_before_read((void*) prev, sizeof(struct general_td));
308 printf("prev: 0x%08X\n", prev);
309 dump_address(prev, sizeof(struct general_td), "prev(after)");
311 if(prev->buflen >0) {
312 sync_before_read((void*) prev->bufaddr, prev->buflen);
314 dump_address((void*) prev->bufaddr, prev->buflen, "prev->bufaddr(after)");
318 dbg_td_flag(LE(prev->flags));
319 printf("halted end!\n");
323 prev = (struct general_td*) (LE(edhead->headp)&~0xf);
324 } while(LE(edhead->headp)&~0xf);
326 n = phys_to_virt(read32(OHCI0_HC_DONE_HEAD) & ~1);
328 printf("hc_done_head: 0x%08X\n", read32(OHCI0_HC_DONE_HEAD));
332 /* reverse done queue */
333 while(virt_to_phys(n) && edhead->tdcount) {
334 sync_before_read((void*) n, sizeof(struct general_td));
336 printf("n: 0x%08X\n", n);
337 printf("next: 0x%08X\n", next);
338 printf("prev: 0x%08X\n", prev);
342 n = (struct general_td*) phys_to_virt(LE(n->nexttd));
343 next->nexttd = (u32) prev;
351 while(virt_to_phys(n)) {
353 dump_address(n, sizeof(struct general_td), "n(after)");
356 sync_before_read((void*) n->bufaddr, n->buflen);
358 dump_address((void*) n->bufaddr, n->buflen, "n->bufaddr(after)");
362 dbg_td_flag(LE(n->flags));
365 n = (struct general_td*) n->nexttd;
369 hcca_oh0.done_head = 0;
370 sync_after_write(&hcca_oh0, sizeof(hcca_oh0));
372 write32(OHCI0_HC_CONTROL, read32(OHCI0_HC_CONTROL)&~OHCI_CTRL_CLE);
377 printf("<^> <^> <^> hcdi_fire(end)\n");
382 * Enqueue a transfer descriptor.
384 u8 hcdi_enqueue(const usb_transfer_descriptor *td) {
386 printf("*()*()*()*()*()*()*() hcdi_enqueue(start)\n");
390 memset(edhead, 0, sizeof(struct endpoint_descriptor));
391 edhead->flags = LE(OHCI_ENDPOINT_GENERAL_FORMAT);
392 edhead->headp = edhead->tailp = edhead->nexted = LE(0);
393 edhead->flags |= LE(OHCI_ENDPOINT_LOW_SPEED |
394 OHCI_ENDPOINT_SET_DEVICE_ADDRESS(td->devaddress) |
395 OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(td->endpoint) |
396 OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(td->maxp));
400 struct general_td *tdhw = allocate_general_td();
401 general_td_fill(tdhw, td);
406 edhead->headp = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
409 /* headp in endpoint already exists
412 struct general_td *n = (struct general_td*) phys_to_virt(LE(edhead->headp) & OHCI_ENDPOINT_HEAD_MASK);
413 while(LE(n->nexttd)) {
414 n = phys_to_virt(LE(n->nexttd));
416 n->nexttd = LE(virt_to_phys((void*) ((u32)tdhw & OHCI_ENDPOINT_HEAD_MASK)));
418 printf("n: 0x%08X\n", n);
419 printf("n->nexttd: 0x%08X\n", phys_to_virt(LE(n->nexttd)));
424 printf("*()*()*()*()*()*()*() hcdi_enqueue(end)\n");
431 * Remove an transfer descriptor from transfer queue.
433 u8 hcdi_dequeue(usb_transfer_descriptor *td) {
439 printf("ohci-- init\n");
442 /* disable hc interrupts */
443 set32(OHCI0_HC_INT_DISABLE, OHCI_INTR_MIE);
445 /* save fmInterval and calculate FSMPS */
446 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
447 #define FI 0x2edf /* 12000 bits per frame (-1) */
448 u32 fmint = read32(OHCI0_HC_FM_INTERVAL) & 0x3fff;
450 printf("ohci-- fminterval delta: %d\n", fmint - FI);
451 fmint |= FSMP (fmint) << 16;
453 /* enable interrupts of both usb host controllers */
454 set32(EHCI_CTL, EHCI_CTL_OH0INTE | EHCI_CTL_OH1INTE | 0xe0000);
457 write32(OHCI0_HC_COMMAND_STATUS, OHCI_HCR);
461 while ((read32(OHCI0_HC_COMMAND_STATUS) & OHCI_HCR) != 0) {
463 printf("ohci-- FAILED");
469 /* disable interrupts; 2ms timelimit here!
470 now we're in the SUSPEND state ... must go OPERATIONAL
471 within 2msec else HC enters RESUME */
473 u32 cookie = irq_kill();
475 /* Tell the controller where the control and bulk lists are
476 * The lists are empty now. */
477 write32(OHCI0_HC_CTRL_HEAD_ED, 0);
478 write32(OHCI0_HC_BULK_HEAD_ED, 0);
480 /* set hcca adress */
481 sync_after_write(&hcca_oh0, 256);
482 write32(OHCI0_HC_HCCA, virt_to_phys(&hcca_oh0));
484 /* set periodicstart */
486 u32 fmInterval = read32(OHCI0_HC_FM_INTERVAL) &0x3fff;
487 u32 fit = read32(OHCI0_HC_FM_INTERVAL) & FIT;
489 write32(OHCI0_HC_FM_INTERVAL, fmint | (fit ^ FIT));
490 write32(OHCI0_HC_PERIODIC_START, ((9*fmInterval)/10)&0x3fff);
493 if ((read32(OHCI0_HC_FM_INTERVAL) & 0x3fff0000) == 0 || !read32(OHCI0_HC_PERIODIC_START)) {
494 printf("ohci-- w00t, fail!! see ohci-hcd.c:669\n");
497 /* start HC operations */
498 write32(OHCI0_HC_CONTROL, OHCI_CONTROL_INIT | OHCI_USB_OPER);
500 /* wake on ConnectStatusChange, matching external hubs */
501 write32(OHCI0_HC_RH_STATUS, /*RH_HS_DRWE |*/ RH_HS_LPSC);
503 /* Choose the interrupts we care about now, others later on demand */
504 write32(OHCI0_HC_INT_STATUS, ~0);
505 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_INIT);
508 wait_ms ((read32(OHCI0_HC_RH_DESCRIPTOR_A) >> 23) & 0x1fe);
510 configure_ports((u8)1);
516 static void configure_ports(u8 from_init)
519 printf("OHCI0_HC_RH_DESCRIPTOR_A:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_A));
520 printf("OHCI0_HC_RH_DESCRIPTOR_B:\t0x%08X\n", read32(OHCI0_HC_RH_DESCRIPTOR_B));
521 printf("OHCI0_HC_RH_STATUS:\t\t0x%08X\n", read32(OHCI0_HC_RH_STATUS));
522 printf("OHCI0_HC_RH_PORT_STATUS_1:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_1));
523 printf("OHCI0_HC_RH_PORT_STATUS_2:\t0x%08X\n", read32(OHCI0_HC_RH_PORT_STATUS_2));
526 setup_port(OHCI0_HC_RH_PORT_STATUS_1, from_init);
527 setup_port(OHCI0_HC_RH_PORT_STATUS_2, from_init);
529 printf("configure_ports done\n");
533 static void setup_port(u32 reg, u8 from_init)
535 u32 port = read32(reg);
536 if((port & RH_PS_CCS) && ((port & RH_PS_CSC) || from_init)) {
537 write32(reg, RH_PS_CSC);
541 /* clear CSC flag, set PES and start port reset (PRS) */
542 write32(reg, RH_PS_PES);
543 while(!(read32(reg) & RH_PS_PES)) {
550 write32(reg, RH_PS_PRS);
552 /* spin until port reset is complete */
553 while(!(read32(reg) & RH_PS_PRSC)); // hint: it may stuck here
555 printf("loop done\n");
558 (void) usb_add_device();
564 /* read interrupt status */
565 u32 flags = read32(OHCI0_HC_INT_STATUS);
567 /* when all bits are set to 1 some problem occured */
568 if (flags == 0xffffffff) {
569 printf("ohci-- Houston, we have a serious problem! :(\n");
573 /* only care about interrupts that are enabled */
574 flags &= read32(OHCI0_HC_INT_ENABLE);
578 printf("OHCI Interrupt occured: but not for you! WTF?!\n");
582 printf("OHCI Interrupt occured: ");
583 /* UnrecoverableError */
584 if (flags & OHCI_INTR_UE) {
585 printf("UnrecoverableError\n");
586 /* TODO: well, I don't know... nothing,
587 * because it won't happen anyway? ;-) */
590 /* RootHubStatusChange */
591 if (flags & OHCI_INTR_RHSC) {
592 printf("RootHubStatusChange\n");
593 /* TODO: set some next_statechange variable... */
595 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD | OHCI_INTR_RHSC);
598 else if (flags & OHCI_INTR_RD) {
599 printf("ResumeDetected\n");
600 write32(OHCI0_HC_INT_STATUS, OHCI_INTR_RD);
601 /* TODO: figure out what the linux kernel does here... */
604 /* WritebackDoneHead */
605 if (flags & OHCI_INTR_WDH) {
606 printf("WritebackDoneHead\n");
607 /* basically the linux irq handler reverse TDs to their urbs
608 * and set done_head to null.
609 * since we are polling atm, just should do the latter task.
610 * however, this won't work for now (i don't know why...)
614 sync_before_read(&hcca_oh0, 256);
615 hcca_oh0.done_head = 0;
616 sync_after_write(&hcca_oh0, 256);
620 /* TODO: handle any pending URB/ED unlinks... */
622 #define HC_IS_RUNNING() 1 /* dirty, i know... just a temporary solution */
623 if (HC_IS_RUNNING()) {
624 write32(OHCI0_HC_INT_STATUS, flags);
625 write32(OHCI0_HC_INT_ENABLE, OHCI_INTR_MIE);
631 sync_before_read(&hcca_oh0, 256);
632 printf("***** frame_no: %d *****\n", LE(hcca_oh0.frame_no));