1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007, 2008, 2009
4 CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
6 This file is part of CACAO.
8 This program is free software; you can redistribute it and/or
9 modify it under the terms of the GNU General Public License as
10 published by the Free Software Foundation; either version 2, or (at
11 your option) any later version.
13 This program is distributed in the hope that it will be useful, but
14 WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
34 #include "vm/jit/x86_64/codegen.h"
35 #include "vm/jit/x86_64/emit.h"
37 #include "mm/memory.hpp"
39 #include "threads/lock.hpp"
41 #include "vm/options.h"
43 #include "vm/jit/abi.h"
44 #include "vm/jit/abi-asm.h"
45 #include "vm/jit/asmpart.h"
46 #include "vm/jit/codegen-common.hpp"
47 #include "vm/jit/emit-common.hpp"
48 #include "vm/jit/jit.hpp"
49 #include "vm/jit/patcher-common.hpp"
50 #include "vm/jit/replace.hpp"
51 #include "vm/jit/trace.hpp"
52 #include "vm/jit/trap.hpp"
55 /* emit_load *******************************************************************
57 Emits a possible load of an operand.
59 *******************************************************************************/
61 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
67 /* get required compiler data */
71 if (IS_INMEMORY(src->flags)) {
74 disp = src->vv.regoff;
78 M_ILD(tempreg, REG_SP, disp);
82 M_LLD(tempreg, REG_SP, disp);
85 M_FLD(tempreg, REG_SP, disp);
88 M_DLD(tempreg, REG_SP, disp);
91 vm_abort("emit_load: unknown type %d", src->type);
103 /* emit_store ******************************************************************
105 This function generates the code to store the result of an
106 operation back into a spilled pseudo-variable. If the
107 pseudo-variable has not been spilled in the first place, this
108 function will generate nothing.
110 *******************************************************************************/
112 void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
117 /* get required compiler data */
121 if (IS_INMEMORY(dst->flags)) {
124 disp = dst->vv.regoff;
130 M_LST(d, REG_SP, disp);
133 M_FST(d, REG_SP, disp);
136 M_DST(d, REG_SP, disp);
139 vm_abort("emit_store: unknown type %d", dst->type);
145 /* emit_copy *******************************************************************
147 Generates a register/memory to register/memory copy.
149 *******************************************************************************/
151 void emit_copy(jitdata *jd, instruction *iptr)
158 /* get required compiler data */
162 /* get source and destination variables */
164 src = VAROP(iptr->s1);
165 dst = VAROP(iptr->dst);
167 if ((src->vv.regoff != dst->vv.regoff) ||
168 ((src->flags ^ dst->flags) & INMEMORY)) {
170 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
171 /* emit nothing, as the value won't be used anyway */
175 /* If one of the variables resides in memory, we can eliminate
176 the register move from/to the temporary register with the
177 order of getting the destination register and the load. */
179 if (IS_INMEMORY(src->flags)) {
180 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
181 s1 = emit_load(jd, iptr, src, d);
184 s1 = emit_load(jd, iptr, src, REG_IFTMP);
185 d = codegen_reg_of_var(iptr->opc, dst, s1);
200 vm_abort("emit_copy: unknown type %d", src->type);
204 emit_store(jd, iptr, dst, d);
209 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
212 switch (iptr->flags.fields.condition) {
237 * Emits code updating the condition register by comparing one integer
238 * register to an immediate integer value.
240 void emit_icmp_imm(codegendata* cd, int reg, int32_t value)
242 M_ICMP_IMM(value, reg);
246 /* emit_branch *****************************************************************
248 Emits the code for conditional and unconditional branchs.
250 *******************************************************************************/
252 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
256 /* NOTE: A displacement overflow cannot happen. */
258 /* check which branch to generate */
260 if (condition == BRANCH_UNCONDITIONAL) {
262 /* calculate the different displacements */
264 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
266 M_JMP_IMM(branchdisp);
269 /* calculate the different displacements */
271 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
305 vm_abort("emit_branch: unknown condition %d", condition);
311 /* emit_arithmetic_check *******************************************************
313 Emit an ArithmeticException check.
315 *******************************************************************************/
317 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
319 if (INSTRUCTION_MUST_CHECK(iptr)) {
322 M_ALD_MEM(reg, TRAP_ArithmeticException);
327 /* emit_arrayindexoutofbounds_check ********************************************
329 Emit a ArrayIndexOutOfBoundsException check.
331 *******************************************************************************/
333 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
335 if (INSTRUCTION_MUST_CHECK(iptr)) {
336 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
337 M_ICMP(REG_ITMP3, s2);
339 M_ALD_MEM(s2, TRAP_ArrayIndexOutOfBoundsException);
344 /* emit_arraystore_check *******************************************************
346 Emit an ArrayStoreException check.
348 *******************************************************************************/
350 void emit_arraystore_check(codegendata *cd, instruction *iptr)
352 if (INSTRUCTION_MUST_CHECK(iptr)) {
355 M_ALD_MEM(REG_RESULT, TRAP_ArrayStoreException);
360 /* emit_classcast_check ********************************************************
362 Emit a ClassCastException check.
364 *******************************************************************************/
366 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
368 if (INSTRUCTION_MUST_CHECK(iptr)) {
386 vm_abort("emit_classcast_check: unknown condition %d", condition);
388 M_ALD_MEM(s1, TRAP_ClassCastException);
393 /* emit_nullpointer_check ******************************************************
395 Emit a NullPointerException check.
397 *******************************************************************************/
399 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
401 if (INSTRUCTION_MUST_CHECK(iptr)) {
404 M_ALD_MEM(reg, TRAP_NullPointerException);
409 /* emit_exception_check ********************************************************
411 Emit an Exception check.
413 *******************************************************************************/
415 void emit_exception_check(codegendata *cd, instruction *iptr)
417 if (INSTRUCTION_MUST_CHECK(iptr)) {
420 M_ALD_MEM(REG_RESULT, TRAP_CHECK_EXCEPTION);
425 /* emit_trap_compiler **********************************************************
427 Emit a trap instruction which calls the JIT compiler.
429 *******************************************************************************/
431 void emit_trap_compiler(codegendata *cd)
433 M_ALD_MEM(REG_METHODPTR, TRAP_COMPILER);
437 /* emit_patcher_alignment ******************************************************
439 Emit NOP to ensure placement at an even address.
441 *******************************************************************************/
443 void emit_patcher_alignment(codegendata *cd)
445 if ((uintptr_t) cd->mcodeptr & 1)
450 /* emit_trap *******************************************************************
452 Emit a trap instruction and return the original machine code.
454 *******************************************************************************/
456 uint32_t emit_trap(codegendata *cd)
460 /* Get machine code which is patched back in later. The trap is 2
463 mcode = *((uint16_t *) cd->mcodeptr);
465 /* XXX This needs to be change to INT3 when the debugging problems
466 with gdb are resolved. */
475 * Generates fast-path code for the below builtin.
476 * Function: LOCK_monitor_enter
477 * Signature: (Ljava/lang/Object;)V
478 * Slow-path: bool lock_monitor_enter(java_handle_t*);
480 void emit_fastpath_monitor_enter(jitdata* jd, instruction* iptr, int d)
482 // Get required compiler data.
483 codegendata* cd = jd->cd;
485 // XXX Currently the fast-path always fails. Implement me!
491 * Generates fast-path code for the below builtin.
492 * Function: LOCK_monitor_exit
493 * Signature: (Ljava/lang/Object;)V
494 * Slow-path: bool lock_monitor_exit(java_handle_t*);
496 void emit_fastpath_monitor_exit(jitdata* jd, instruction* iptr, int d)
498 // Get required compiler data.
499 codegendata* cd = jd->cd;
501 // XXX Currently the fast-path always fails. Implement me!
507 * Generates synchronization code to enter a monitor.
509 #if defined(ENABLE_THREADS)
510 void emit_monitor_enter(jitdata* jd, int32_t syncslot_offset)
514 // Get required compiler data.
515 methodinfo* m = jd->m;
516 codegendata* cd = jd->cd;
518 # if !defined(NDEBUG)
519 if (JITDATA_HAS_FLAG_VERBOSECALL(jd)) {
520 M_LSUB_IMM((INT_ARG_CNT + FLT_ARG_CNT) * 8, REG_SP);
522 for (p = 0; p < INT_ARG_CNT; p++)
523 M_LST(abi_registers_integer_argument[p], REG_SP, p * 8);
525 for (p = 0; p < FLT_ARG_CNT; p++)
526 M_DST(abi_registers_float_argument[p], REG_SP, (INT_ARG_CNT + p) * 8);
528 syncslot_offset += (INT_ARG_CNT + FLT_ARG_CNT) * 8;
532 /* decide which monitor enter function to call */
534 if (m->flags & ACC_STATIC) {
535 M_MOV_IMM(&m->clazz->object.header, REG_A0);
540 M_ALD_MEM(REG_A0, TRAP_NullPointerException);
543 M_AST(REG_A0, REG_SP, syncslot_offset);
544 M_MOV_IMM(LOCK_monitor_enter, REG_ITMP1);
547 # if !defined(NDEBUG)
548 if (JITDATA_HAS_FLAG_VERBOSECALL(jd)) {
550 for (p = 0; p < INT_ARG_CNT; p++)
551 M_LLD(abi_registers_integer_argument[p], REG_SP, p * 8);
553 for (p = 0; p < FLT_ARG_CNT; p++)
554 M_DLD(abi_registers_float_argument[p], REG_SP, (INT_ARG_CNT + p) * 8);
556 M_LADD_IMM((INT_ARG_CNT + FLT_ARG_CNT) * 8, REG_SP);
564 * Generates synchronization code to leave a monitor.
566 #if defined(ENABLE_THREADS)
567 void emit_monitor_exit(jitdata* jd, int32_t syncslot_offset)
569 // Get required compiler data.
570 methodinfo* m = jd->m;
571 codegendata* cd = jd->cd;
573 M_ALD(REG_A0, REG_SP, syncslot_offset);
575 /* we need to save the proper return value */
577 methoddesc* md = m->parseddesc;
579 switch (md->returntype.type) {
583 M_LST(REG_RESULT, REG_SP, syncslot_offset);
587 M_DST(REG_FRESULT, REG_SP, syncslot_offset);
591 M_MOV_IMM(LOCK_monitor_exit, REG_ITMP1);
594 /* and now restore the proper return value */
596 switch (md->returntype.type) {
600 M_LLD(REG_RESULT, REG_SP, syncslot_offset);
604 M_DLD(REG_FRESULT, REG_SP, syncslot_offset);
612 * Emit profiling code for method frequency counting.
614 #if defined(ENABLE_PROFILING)
615 void emit_profile_method(codegendata* cd, codeinfo* code)
617 M_MOV_IMM(code, REG_ITMP3);
618 M_IINC_MEMBASE(REG_ITMP3, OFFSET(codeinfo, frequency));
624 * Emit profiling code for basicblock frequency counting.
626 #if defined(ENABLE_PROFILING)
627 void emit_profile_basicblock(codegendata* cd, codeinfo* code, basicblock* bptr)
629 M_MOV_IMM(code->bbfrequency, REG_ITMP3);
630 M_IINC_MEMBASE(REG_ITMP3, bptr->nr * 4);
636 * Emit profiling code to start CPU cycle counting.
638 #if defined(ENABLE_PROFILING)
639 void emit_profile_cycle_start(codegendata* cd, codeinfo* code)
644 M_MOV_IMM(code, REG_ITMP3);
646 M_ISUB_MEMBASE(RAX, REG_ITMP3, OFFSET(codeinfo, cycles));
647 M_ISBB_MEMBASE(RDX, REG_ITMP3, OFFSET(codeinfo, cycles) + 4);
656 * Emit profiling code to stop CPU cycle counting.
658 #if defined(ENABLE_PROFILING)
659 void emit_profile_cycle_stop(codegendata* cd, codeinfo* code)
664 M_MOV_IMM(code, REG_ITMP3);
666 M_IADD_MEMBASE(RAX, REG_ITMP3, OFFSET(codeinfo, cycles));
667 M_IADC_MEMBASE(RDX, REG_ITMP3, OFFSET(codeinfo, cycles) + 4);
675 /* emit_verbosecall_enter ******************************************************
677 Generates the code for the call trace.
679 *******************************************************************************/
682 void emit_verbosecall_enter(jitdata *jd)
692 /* get required compiler data */
701 /* mark trace code */
705 /* keep 16-byte stack alignment */
707 stackframesize = md->paramcount + ARG_CNT + TMP_CNT;
708 ALIGN_2(stackframesize);
710 M_LSUB_IMM(stackframesize * 8, REG_SP);
712 /* save argument registers */
714 for (i = 0; i < md->paramcount; i++) {
715 if (!md->params[i].inmemory) {
716 s = md->params[i].regoff;
718 switch (md->paramtypes[i].type) {
722 M_LST(s, REG_SP, i * 8);
726 M_DST(s, REG_SP, i * 8);
732 /* save all argument and temporary registers for leaf methods */
734 if (code_is_leafmethod(code)) {
735 for (i = 0; i < INT_ARG_CNT; i++)
736 M_LST(abi_registers_integer_argument[i], REG_SP, (md->paramcount + i) * 8);
738 for (i = 0; i < FLT_ARG_CNT; i++)
739 M_DST(abi_registers_float_argument[i], REG_SP, (md->paramcount + INT_ARG_CNT + i) * 8);
741 for (i = 0; i < INT_TMP_CNT; i++)
742 M_LST(rd->tmpintregs[i], REG_SP, (md->paramcount + ARG_CNT + i) * 8);
744 for (i = 0; i < FLT_TMP_CNT; i++)
745 M_DST(rd->tmpfltregs[i], REG_SP, (md->paramcount + ARG_CNT + INT_TMP_CNT + i) * 8);
748 M_MOV_IMM(m, REG_A0);
749 M_MOV(REG_SP, REG_A1);
750 M_MOV(REG_SP, REG_A2);
751 M_AADD_IMM((stackframesize + cd->stackframesize + 1) * 8, REG_A2);
752 M_MOV_IMM(trace_java_call_enter, REG_ITMP1);
755 /* restore argument registers */
757 for (i = 0; i < md->paramcount; i++) {
758 if (!md->params[i].inmemory) {
759 s = md->params[i].regoff;
761 switch (md->paramtypes[i].type) {
765 M_LLD(s, REG_SP, i * 8);
769 M_DLD(s, REG_SP, i * 8);
776 /* restore all argument and temporary registers for leaf methods */
778 if (code_is_leafmethod(code)) {
779 for (i = 0; i < INT_ARG_CNT; i++)
780 M_LLD(abi_registers_integer_argument[i], REG_SP, (md->paramcount + i) * 8);
782 for (i = 0; i < FLT_ARG_CNT; i++)
783 M_DLD(abi_registers_float_argument[i], REG_SP, (md->paramcount + INT_ARG_CNT + i) * 8);
785 for (i = 0; i < INT_TMP_CNT; i++)
786 M_LLD(rd->tmpintregs[i], REG_SP, (md->paramcount + ARG_CNT + i) * 8);
788 for (i = 0; i < FLT_TMP_CNT; i++)
789 M_DLD(rd->tmpfltregs[i], REG_SP, (md->paramcount + ARG_CNT + INT_TMP_CNT + i) * 8);
792 M_LADD_IMM(stackframesize * 8, REG_SP);
794 /* mark trace code */
798 #endif /* !defined(NDEBUG) */
801 /* emit_verbosecall_exit *******************************************************
803 Generates the code for the call trace.
805 *******************************************************************************/
808 void emit_verbosecall_exit(jitdata *jd)
815 /* get required compiler data */
823 /* mark trace code */
827 /* keep 16-byte stack alignment */
829 M_ASUB_IMM(2 * 8, REG_SP);
831 /* save return value */
833 switch (md->returntype.type) {
837 M_LST(REG_RESULT, REG_SP, 0 * 8);
841 M_DST(REG_FRESULT, REG_SP, 0 * 8);
845 M_MOV_IMM(m, REG_A0);
846 M_MOV(REG_SP, REG_A1);
848 M_MOV_IMM(trace_java_call_exit, REG_ITMP1);
851 /* restore return value */
853 switch (md->returntype.type) {
857 M_LLD(REG_RESULT, REG_SP, 0 * 8);
861 M_DLD(REG_FRESULT, REG_SP, 0 * 8);
865 M_AADD_IMM(2 * 8, REG_SP);
867 /* mark trace code */
871 #endif /* !defined(NDEBUG) */
874 /* code generation functions **************************************************/
876 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
878 if ((basereg == REG_SP) || (basereg == R12)) {
880 emit_address_byte(0, dreg, REG_SP);
881 emit_address_byte(0, REG_SP, REG_SP);
883 } else if (IS_IMM8(disp)) {
884 emit_address_byte(1, dreg, REG_SP);
885 emit_address_byte(0, REG_SP, REG_SP);
889 emit_address_byte(2, dreg, REG_SP);
890 emit_address_byte(0, REG_SP, REG_SP);
894 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
895 emit_address_byte(0,(dreg),(basereg));
897 } else if ((basereg) == RIP) {
898 emit_address_byte(0, dreg, RBP);
903 emit_address_byte(1, dreg, basereg);
907 emit_address_byte(2, dreg, basereg);
914 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
916 if ((basereg == REG_SP) || (basereg == R12)) {
917 emit_address_byte(2, dreg, REG_SP);
918 emit_address_byte(0, REG_SP, REG_SP);
922 emit_address_byte(2, dreg, basereg);
928 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
931 emit_address_byte(0, reg, 4);
932 emit_address_byte(scale, indexreg, 5);
935 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
936 emit_address_byte(0, reg, 4);
937 emit_address_byte(scale, indexreg, basereg);
939 else if (IS_IMM8(disp)) {
940 emit_address_byte(1, reg, 4);
941 emit_address_byte(scale, indexreg, basereg);
945 emit_address_byte(2, reg, 4);
946 emit_address_byte(scale, indexreg, basereg);
952 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
955 varinfo *v_s1,*v_s2,*v_dst;
958 /* get required compiler data */
962 v_s1 = VAROP(iptr->s1);
963 v_s2 = VAROP(iptr->sx.s23.s2);
964 v_dst = VAROP(iptr->dst);
966 s1 = v_s1->vv.regoff;
967 s2 = v_s2->vv.regoff;
968 d = v_dst->vv.regoff;
970 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
972 if (IS_INMEMORY(v_dst->flags)) {
973 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
975 M_ILD(RCX, REG_SP, s2);
976 emit_shiftl_membase(cd, shift_op, REG_SP, d);
979 M_ILD(RCX, REG_SP, s2);
980 M_ILD(REG_ITMP2, REG_SP, s1);
981 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
982 M_IST(REG_ITMP2, REG_SP, d);
985 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
986 /* s1 may be equal to RCX */
989 M_ILD(REG_ITMP1, REG_SP, s2);
990 M_IST(s1, REG_SP, d);
991 M_INTMOVE(REG_ITMP1, RCX);
994 M_IST(s1, REG_SP, d);
995 M_ILD(RCX, REG_SP, s2);
999 M_ILD(RCX, REG_SP, s2);
1000 M_IST(s1, REG_SP, d);
1003 emit_shiftl_membase(cd, shift_op, REG_SP, d);
1005 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1008 emit_shiftl_membase(cd, shift_op, REG_SP, d);
1012 M_ILD(REG_ITMP2, REG_SP, s1);
1013 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
1014 M_IST(REG_ITMP2, REG_SP, d);
1018 /* s1 may be equal to RCX */
1019 M_IST(s1, REG_SP, d);
1021 emit_shiftl_membase(cd, shift_op, REG_SP, d);
1024 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1032 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1033 M_ILD(RCX, REG_SP, s2);
1034 M_ILD(d, REG_SP, s1);
1035 emit_shiftl_reg(cd, shift_op, d);
1037 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
1038 /* s1 may be equal to RCX */
1040 M_ILD(RCX, REG_SP, s2);
1041 emit_shiftl_reg(cd, shift_op, d);
1043 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1045 M_ILD(d, REG_SP, s1);
1046 emit_shiftl_reg(cd, shift_op, d);
1049 /* s1 may be equal to RCX */
1052 /* d cannot be used to backup s1 since this would
1054 M_INTMOVE(s1, REG_ITMP3);
1056 M_INTMOVE(REG_ITMP3, d);
1064 /* d may be equal to s2 */
1068 emit_shiftl_reg(cd, shift_op, d);
1072 M_INTMOVE(REG_ITMP3, RCX);
1074 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1079 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
1081 s4 s1, s2, d, d_old;
1082 varinfo *v_s1,*v_s2,*v_dst;
1085 /* get required compiler data */
1089 v_s1 = VAROP(iptr->s1);
1090 v_s2 = VAROP(iptr->sx.s23.s2);
1091 v_dst = VAROP(iptr->dst);
1093 s1 = v_s1->vv.regoff;
1094 s2 = v_s2->vv.regoff;
1095 d = v_dst->vv.regoff;
1097 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
1099 if (IS_INMEMORY(v_dst->flags)) {
1100 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1102 M_ILD(RCX, REG_SP, s2);
1103 emit_shift_membase(cd, shift_op, REG_SP, d);
1106 M_ILD(RCX, REG_SP, s2);
1107 M_LLD(REG_ITMP2, REG_SP, s1);
1108 emit_shift_reg(cd, shift_op, REG_ITMP2);
1109 M_LST(REG_ITMP2, REG_SP, d);
1112 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
1113 /* s1 may be equal to RCX */
1116 M_ILD(REG_ITMP1, REG_SP, s2);
1117 M_LST(s1, REG_SP, d);
1118 M_INTMOVE(REG_ITMP1, RCX);
1121 M_LST(s1, REG_SP, d);
1122 M_ILD(RCX, REG_SP, s2);
1126 M_ILD(RCX, REG_SP, s2);
1127 M_LST(s1, REG_SP, d);
1130 emit_shift_membase(cd, shift_op, REG_SP, d);
1132 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1135 emit_shift_membase(cd, shift_op, REG_SP, d);
1139 M_LLD(REG_ITMP2, REG_SP, s1);
1140 emit_shift_reg(cd, shift_op, REG_ITMP2);
1141 M_LST(REG_ITMP2, REG_SP, d);
1145 /* s1 may be equal to RCX */
1146 M_LST(s1, REG_SP, d);
1148 emit_shift_membase(cd, shift_op, REG_SP, d);
1151 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1159 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1160 M_ILD(RCX, REG_SP, s2);
1161 M_LLD(d, REG_SP, s1);
1162 emit_shift_reg(cd, shift_op, d);
1164 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
1165 /* s1 may be equal to RCX */
1167 M_ILD(RCX, REG_SP, s2);
1168 emit_shift_reg(cd, shift_op, d);
1170 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1172 M_LLD(d, REG_SP, s1);
1173 emit_shift_reg(cd, shift_op, d);
1176 /* s1 may be equal to RCX */
1179 /* d cannot be used to backup s1 since this would
1181 M_INTMOVE(s1, REG_ITMP3);
1183 M_INTMOVE(REG_ITMP3, d);
1191 /* d may be equal to s2 */
1195 emit_shift_reg(cd, shift_op, d);
1199 M_INTMOVE(REG_ITMP3, RCX);
1201 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1206 /* low-level code emitter functions *******************************************/
1208 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1210 emit_rex(1,(reg),0,(dreg));
1211 *(cd->mcodeptr++) = 0x89;
1212 emit_reg((reg),(dreg));
1216 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1218 emit_rex(1,0,0,(reg));
1219 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1224 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1226 emit_rex(0,(reg),0,(dreg));
1227 *(cd->mcodeptr++) = 0x89;
1228 emit_reg((reg),(dreg));
1232 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1233 emit_rex(0,0,0,(reg));
1234 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1239 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1240 emit_rex(1,(reg),0,(basereg));
1241 *(cd->mcodeptr++) = 0x8b;
1242 emit_membase(cd, (basereg),(disp),(reg));
1247 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1248 * constant membase immediate length of 32bit
1250 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1251 emit_rex(1,(reg),0,(basereg));
1252 *(cd->mcodeptr++) = 0x8b;
1253 emit_membase32(cd, (basereg),(disp),(reg));
1257 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1259 emit_rex(0,(reg),0,(basereg));
1260 *(cd->mcodeptr++) = 0x8b;
1261 emit_membase(cd, (basereg),(disp),(reg));
1265 /* ATTENTION: Always emit a REX byte, because the instruction size can
1266 be smaller when all register indexes are smaller than 7. */
1267 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1269 emit_byte_rex((reg),0,(basereg));
1270 *(cd->mcodeptr++) = 0x8b;
1271 emit_membase32(cd, (basereg),(disp),(reg));
1275 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1276 emit_rex(1,(reg),0,(basereg));
1277 *(cd->mcodeptr++) = 0x89;
1278 emit_membase(cd, (basereg),(disp),(reg));
1282 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1283 emit_rex(1,(reg),0,(basereg));
1284 *(cd->mcodeptr++) = 0x89;
1285 emit_membase32(cd, (basereg),(disp),(reg));
1289 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1290 emit_rex(0,(reg),0,(basereg));
1291 *(cd->mcodeptr++) = 0x89;
1292 emit_membase(cd, (basereg),(disp),(reg));
1296 /* Always emit a REX byte, because the instruction size can be smaller when */
1297 /* all register indexes are smaller than 7. */
1298 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1299 emit_byte_rex((reg),0,(basereg));
1300 *(cd->mcodeptr++) = 0x89;
1301 emit_membase32(cd, (basereg),(disp),(reg));
1305 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1306 emit_rex(1,(reg),(indexreg),(basereg));
1307 *(cd->mcodeptr++) = 0x8b;
1308 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1312 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1313 emit_rex(0,(reg),(indexreg),(basereg));
1314 *(cd->mcodeptr++) = 0x8b;
1315 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1319 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1320 emit_rex(1,(reg),(indexreg),(basereg));
1321 *(cd->mcodeptr++) = 0x89;
1322 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1326 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1327 emit_rex(0,(reg),(indexreg),(basereg));
1328 *(cd->mcodeptr++) = 0x89;
1329 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1333 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1334 *(cd->mcodeptr++) = 0x66;
1335 emit_rex(0,(reg),(indexreg),(basereg));
1336 *(cd->mcodeptr++) = 0x89;
1337 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1341 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1342 emit_byte_rex((reg),(indexreg),(basereg));
1343 *(cd->mcodeptr++) = 0x88;
1344 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1348 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1349 emit_rex(1,0,0,(basereg));
1350 *(cd->mcodeptr++) = 0xc7;
1351 emit_membase(cd, (basereg),(disp),0);
1356 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1357 emit_rex(1,0,0,(basereg));
1358 *(cd->mcodeptr++) = 0xc7;
1359 emit_membase32(cd, (basereg),(disp),0);
1364 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1365 emit_rex(0,0,0,(basereg));
1366 *(cd->mcodeptr++) = 0xc7;
1367 emit_membase(cd, (basereg),(disp),0);
1372 /* Always emit a REX byte, because the instruction size can be smaller when */
1373 /* all register indexes are smaller than 7. */
1374 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1375 emit_byte_rex(0,0,(basereg));
1376 *(cd->mcodeptr++) = 0xc7;
1377 emit_membase32(cd, (basereg),(disp),0);
1382 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1384 emit_rex(1,(dreg),0,(reg));
1385 *(cd->mcodeptr++) = 0x0f;
1386 *(cd->mcodeptr++) = 0xbe;
1387 /* XXX: why do reg and dreg have to be exchanged */
1388 emit_reg((dreg),(reg));
1392 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1394 emit_rex(1,(dreg),0,(reg));
1395 *(cd->mcodeptr++) = 0x0f;
1396 *(cd->mcodeptr++) = 0xbf;
1397 /* XXX: why do reg and dreg have to be exchanged */
1398 emit_reg((dreg),(reg));
1402 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1404 emit_rex(1,(dreg),0,(reg));
1405 *(cd->mcodeptr++) = 0x63;
1406 /* XXX: why do reg and dreg have to be exchanged */
1407 emit_reg((dreg),(reg));
1411 void emit_movzbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1413 emit_rex(1,(dreg),0,(reg));
1414 *(cd->mcodeptr++) = 0x0f;
1415 *(cd->mcodeptr++) = 0xb6;
1416 /* XXX: why do reg and dreg have to be exchanged */
1417 emit_reg((dreg),(reg));
1421 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1423 emit_rex(1,(dreg),0,(reg));
1424 *(cd->mcodeptr++) = 0x0f;
1425 *(cd->mcodeptr++) = 0xb7;
1426 /* XXX: why do reg and dreg have to be exchanged */
1427 emit_reg((dreg),(reg));
1431 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1432 emit_rex(1,(reg),(indexreg),(basereg));
1433 *(cd->mcodeptr++) = 0x0f;
1434 *(cd->mcodeptr++) = 0xbf;
1435 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1439 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1440 emit_rex(1,(reg),(indexreg),(basereg));
1441 *(cd->mcodeptr++) = 0x0f;
1442 *(cd->mcodeptr++) = 0xbe;
1443 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1447 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1448 emit_rex(1,(reg),(indexreg),(basereg));
1449 *(cd->mcodeptr++) = 0x0f;
1450 *(cd->mcodeptr++) = 0xb7;
1451 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1455 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1457 emit_rex(1,0,(indexreg),(basereg));
1458 *(cd->mcodeptr++) = 0xc7;
1459 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1464 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1466 emit_rex(0,0,(indexreg),(basereg));
1467 *(cd->mcodeptr++) = 0xc7;
1468 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1473 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1475 *(cd->mcodeptr++) = 0x66;
1476 emit_rex(0,0,(indexreg),(basereg));
1477 *(cd->mcodeptr++) = 0xc7;
1478 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1483 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1485 emit_rex(0,0,(indexreg),(basereg));
1486 *(cd->mcodeptr++) = 0xc6;
1487 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1492 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1494 emit_rex(1, dreg, 0, 0);
1495 *(cd->mcodeptr++) = 0x8b;
1496 emit_address_byte(0, dreg, 4);
1504 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1506 emit_rex(1,(reg),0,(dreg));
1507 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1508 emit_reg((reg),(dreg));
1512 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1514 emit_rex(0,(reg),0,(dreg));
1515 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1516 emit_reg((reg),(dreg));
1520 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1522 emit_rex(1,(reg),0,(basereg));
1523 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1524 emit_membase(cd, (basereg),(disp),(reg));
1528 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1530 emit_rex(0,(reg),0,(basereg));
1531 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1532 emit_membase(cd, (basereg),(disp),(reg));
1536 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1538 emit_rex(1,(reg),0,(basereg));
1539 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1540 emit_membase(cd, (basereg),(disp),(reg));
1544 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1546 emit_rex(0,(reg),0,(basereg));
1547 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1548 emit_membase(cd, (basereg),(disp),(reg));
1552 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1554 emit_rex(1,0,0,(dreg));
1555 *(cd->mcodeptr++) = 0x83;
1556 emit_reg((opc),(dreg));
1559 emit_rex(1,0,0,(dreg));
1560 *(cd->mcodeptr++) = 0x81;
1561 emit_reg((opc),(dreg));
1567 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1569 emit_rex(1,0,0,(dreg));
1570 *(cd->mcodeptr++) = 0x81;
1571 emit_reg((opc),(dreg));
1576 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1578 emit_rex(0,0,0,(dreg));
1579 *(cd->mcodeptr++) = 0x81;
1580 emit_reg((opc),(dreg));
1585 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1587 emit_rex(0,0,0,(dreg));
1588 *(cd->mcodeptr++) = 0x83;
1589 emit_reg((opc),(dreg));
1592 emit_rex(0,0,0,(dreg));
1593 *(cd->mcodeptr++) = 0x81;
1594 emit_reg((opc),(dreg));
1600 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1602 emit_rex(1,0,0,(basereg));
1603 *(cd->mcodeptr++) = 0x83;
1604 emit_membase(cd, (basereg),(disp),(opc));
1607 emit_rex(1,0,0,(basereg));
1608 *(cd->mcodeptr++) = 0x81;
1609 emit_membase(cd, (basereg),(disp),(opc));
1615 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1617 emit_rex(0,0,0,(basereg));
1618 *(cd->mcodeptr++) = 0x83;
1619 emit_membase(cd, (basereg),(disp),(opc));
1622 emit_rex(0,0,0,(basereg));
1623 *(cd->mcodeptr++) = 0x81;
1624 emit_membase(cd, (basereg),(disp),(opc));
1629 void emit_alu_memindex_reg(codegendata *cd, s8 opc, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg)
1631 emit_rex(1,(reg),(indexreg),(basereg));
1632 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1633 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1636 void emit_alul_memindex_reg(codegendata *cd, s8 opc, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg)
1638 emit_rex(0,(reg),(indexreg),(basereg));
1639 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1640 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1643 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1644 emit_rex(1,(reg),0,(dreg));
1645 *(cd->mcodeptr++) = 0x85;
1646 emit_reg((reg),(dreg));
1650 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1651 emit_rex(0,(reg),0,(dreg));
1652 *(cd->mcodeptr++) = 0x85;
1653 emit_reg((reg),(dreg));
1657 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1658 *(cd->mcodeptr++) = 0xf7;
1664 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1665 *(cd->mcodeptr++) = 0x66;
1666 *(cd->mcodeptr++) = 0xf7;
1672 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1673 *(cd->mcodeptr++) = 0xf6;
1679 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1680 emit_rex(1,(reg),0,(basereg));
1681 *(cd->mcodeptr++) = 0x8d;
1682 emit_membase(cd, (basereg),(disp),(reg));
1686 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1687 emit_rex(0,(reg),0,(basereg));
1688 *(cd->mcodeptr++) = 0x8d;
1689 emit_membase(cd, (basereg),(disp),(reg));
1693 void emit_incl_reg(codegendata *cd, s8 reg)
1695 *(cd->mcodeptr++) = 0xff;
1699 void emit_incq_reg(codegendata *cd, s8 reg)
1701 emit_rex(1,0,0,(reg));
1702 *(cd->mcodeptr++) = 0xff;
1706 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1708 emit_rex(0,0,0,(basereg));
1709 *(cd->mcodeptr++) = 0xff;
1710 emit_membase(cd, (basereg),(disp),0);
1713 void emit_incq_membase(codegendata *cd, s8 basereg, s8 disp)
1715 emit_rex(1,0,0,(basereg));
1716 *(cd->mcodeptr++) = 0xff;
1717 emit_membase(cd, (basereg),(disp),0);
1722 void emit_cltd(codegendata *cd) {
1723 *(cd->mcodeptr++) = 0x99;
1727 void emit_cqto(codegendata *cd) {
1729 *(cd->mcodeptr++) = 0x99;
1734 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1735 emit_rex(1,(dreg),0,(reg));
1736 *(cd->mcodeptr++) = 0x0f;
1737 *(cd->mcodeptr++) = 0xaf;
1738 emit_reg((dreg),(reg));
1742 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1743 emit_rex(0,(dreg),0,(reg));
1744 *(cd->mcodeptr++) = 0x0f;
1745 *(cd->mcodeptr++) = 0xaf;
1746 emit_reg((dreg),(reg));
1750 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1751 emit_rex(1,(dreg),0,(basereg));
1752 *(cd->mcodeptr++) = 0x0f;
1753 *(cd->mcodeptr++) = 0xaf;
1754 emit_membase(cd, (basereg),(disp),(dreg));
1758 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1759 emit_rex(0,(dreg),0,(basereg));
1760 *(cd->mcodeptr++) = 0x0f;
1761 *(cd->mcodeptr++) = 0xaf;
1762 emit_membase(cd, (basereg),(disp),(dreg));
1766 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1767 if (IS_IMM8((imm))) {
1768 emit_rex(1,0,0,(dreg));
1769 *(cd->mcodeptr++) = 0x6b;
1773 emit_rex(1,0,0,(dreg));
1774 *(cd->mcodeptr++) = 0x69;
1781 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1782 if (IS_IMM8((imm))) {
1783 emit_rex(1,(dreg),0,(reg));
1784 *(cd->mcodeptr++) = 0x6b;
1785 emit_reg((dreg),(reg));
1788 emit_rex(1,(dreg),0,(reg));
1789 *(cd->mcodeptr++) = 0x69;
1790 emit_reg((dreg),(reg));
1796 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1797 if (IS_IMM8((imm))) {
1798 emit_rex(0,(dreg),0,(reg));
1799 *(cd->mcodeptr++) = 0x6b;
1800 emit_reg((dreg),(reg));
1803 emit_rex(0,(dreg),0,(reg));
1804 *(cd->mcodeptr++) = 0x69;
1805 emit_reg((dreg),(reg));
1811 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1812 if (IS_IMM8((imm))) {
1813 emit_rex(1,(dreg),0,(basereg));
1814 *(cd->mcodeptr++) = 0x6b;
1815 emit_membase(cd, (basereg),(disp),(dreg));
1818 emit_rex(1,(dreg),0,(basereg));
1819 *(cd->mcodeptr++) = 0x69;
1820 emit_membase(cd, (basereg),(disp),(dreg));
1826 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1827 if (IS_IMM8((imm))) {
1828 emit_rex(0,(dreg),0,(basereg));
1829 *(cd->mcodeptr++) = 0x6b;
1830 emit_membase(cd, (basereg),(disp),(dreg));
1833 emit_rex(0,(dreg),0,(basereg));
1834 *(cd->mcodeptr++) = 0x69;
1835 emit_membase(cd, (basereg),(disp),(dreg));
1841 void emit_idiv_reg(codegendata *cd, s8 reg) {
1842 emit_rex(1,0,0,(reg));
1843 *(cd->mcodeptr++) = 0xf7;
1848 void emit_idivl_reg(codegendata *cd, s8 reg) {
1849 emit_rex(0,0,0,(reg));
1850 *(cd->mcodeptr++) = 0xf7;
1859 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1860 emit_rex(1,0,0,(reg));
1861 *(cd->mcodeptr++) = 0xd3;
1862 emit_reg((opc),(reg));
1866 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1867 emit_rex(0,0,0,(reg));
1868 *(cd->mcodeptr++) = 0xd3;
1869 emit_reg((opc),(reg));
1873 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1874 emit_rex(1,0,0,(basereg));
1875 *(cd->mcodeptr++) = 0xd3;
1876 emit_membase(cd, (basereg),(disp),(opc));
1880 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1881 emit_rex(0,0,0,(basereg));
1882 *(cd->mcodeptr++) = 0xd3;
1883 emit_membase(cd, (basereg),(disp),(opc));
1887 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1889 emit_rex(1,0,0,(dreg));
1890 *(cd->mcodeptr++) = 0xd1;
1891 emit_reg((opc),(dreg));
1893 emit_rex(1,0,0,(dreg));
1894 *(cd->mcodeptr++) = 0xc1;
1895 emit_reg((opc),(dreg));
1901 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1903 emit_rex(0,0,0,(dreg));
1904 *(cd->mcodeptr++) = 0xd1;
1905 emit_reg((opc),(dreg));
1907 emit_rex(0,0,0,(dreg));
1908 *(cd->mcodeptr++) = 0xc1;
1909 emit_reg((opc),(dreg));
1915 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1917 emit_rex(1,0,0,(basereg));
1918 *(cd->mcodeptr++) = 0xd1;
1919 emit_membase(cd, (basereg),(disp),(opc));
1921 emit_rex(1,0,0,(basereg));
1922 *(cd->mcodeptr++) = 0xc1;
1923 emit_membase(cd, (basereg),(disp),(opc));
1929 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1931 emit_rex(0,0,0,(basereg));
1932 *(cd->mcodeptr++) = 0xd1;
1933 emit_membase(cd, (basereg),(disp),(opc));
1935 emit_rex(0,0,0,(basereg));
1936 *(cd->mcodeptr++) = 0xc1;
1937 emit_membase(cd, (basereg),(disp),(opc));
1947 void emit_jmp_imm(codegendata *cd, s8 imm) {
1948 *(cd->mcodeptr++) = 0xe9;
1952 /* like emit_jmp_imm but allows 8 bit optimization */
1953 void emit_jmp_imm2(codegendata *cd, s8 imm) {
1955 *(cd->mcodeptr++) = 0xeb;
1959 *(cd->mcodeptr++) = 0xe9;
1965 void emit_jmp_reg(codegendata *cd, s8 reg) {
1966 emit_rex(0,0,0,(reg));
1967 *(cd->mcodeptr++) = 0xff;
1972 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1973 *(cd->mcodeptr++) = 0x0f;
1974 *(cd->mcodeptr++) = (0x80 + (opc));
1981 * conditional set and move operations
1984 /* we need the rex byte to get all low bytes */
1985 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1987 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1988 *(cd->mcodeptr++) = 0x0f;
1989 *(cd->mcodeptr++) = (0x90 + (opc));
1994 /* we need the rex byte to get all low bytes */
1995 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1997 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1998 *(cd->mcodeptr++) = 0x0f;
1999 *(cd->mcodeptr++) = (0x90 + (opc));
2000 emit_membase(cd, (basereg),(disp),0);
2004 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
2006 emit_rex(1,(dreg),0,(reg));
2007 *(cd->mcodeptr++) = 0x0f;
2008 *(cd->mcodeptr++) = (0x40 + (opc));
2009 emit_reg((dreg),(reg));
2013 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
2015 emit_rex(0,(dreg),0,(reg));
2016 *(cd->mcodeptr++) = 0x0f;
2017 *(cd->mcodeptr++) = (0x40 + (opc));
2018 emit_reg((dreg),(reg));
2022 void emit_neg_reg(codegendata *cd, s8 reg)
2024 emit_rex(1,0,0,(reg));
2025 *(cd->mcodeptr++) = 0xf7;
2030 void emit_negl_reg(codegendata *cd, s8 reg)
2032 emit_rex(0,0,0,(reg));
2033 *(cd->mcodeptr++) = 0xf7;
2038 void emit_push_reg(codegendata *cd, s8 reg) {
2039 emit_rex(0,0,0,(reg));
2040 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
2044 void emit_push_imm(codegendata *cd, s8 imm) {
2045 *(cd->mcodeptr++) = 0x68;
2050 void emit_pop_reg(codegendata *cd, s8 reg) {
2051 emit_rex(0,0,0,(reg));
2052 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
2056 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2057 emit_rex(1,(reg),0,(dreg));
2058 *(cd->mcodeptr++) = 0x87;
2059 emit_reg((reg),(dreg));
2067 void emit_call_reg(codegendata *cd, s8 reg)
2069 emit_rex(0,0,0,(reg));
2070 *(cd->mcodeptr++) = 0xff;
2075 void emit_call_imm(codegendata *cd, s8 imm)
2077 *(cd->mcodeptr++) = 0xe8;
2082 void emit_call_mem(codegendata *cd, ptrint mem)
2084 *(cd->mcodeptr++) = 0xff;
2091 * floating point instructions (SSE2)
2093 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2094 *(cd->mcodeptr++) = 0xf2;
2095 emit_rex(0,(dreg),0,(reg));
2096 *(cd->mcodeptr++) = 0x0f;
2097 *(cd->mcodeptr++) = 0x58;
2098 emit_reg((dreg),(reg));
2102 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2103 *(cd->mcodeptr++) = 0xf3;
2104 emit_rex(0,(dreg),0,(reg));
2105 *(cd->mcodeptr++) = 0x0f;
2106 *(cd->mcodeptr++) = 0x58;
2107 emit_reg((dreg),(reg));
2111 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2112 *(cd->mcodeptr++) = 0xf3;
2113 emit_rex(1,(dreg),0,(reg));
2114 *(cd->mcodeptr++) = 0x0f;
2115 *(cd->mcodeptr++) = 0x2a;
2116 emit_reg((dreg),(reg));
2120 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2121 *(cd->mcodeptr++) = 0xf3;
2122 emit_rex(0,(dreg),0,(reg));
2123 *(cd->mcodeptr++) = 0x0f;
2124 *(cd->mcodeptr++) = 0x2a;
2125 emit_reg((dreg),(reg));
2129 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2130 *(cd->mcodeptr++) = 0xf2;
2131 emit_rex(1,(dreg),0,(reg));
2132 *(cd->mcodeptr++) = 0x0f;
2133 *(cd->mcodeptr++) = 0x2a;
2134 emit_reg((dreg),(reg));
2138 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2139 *(cd->mcodeptr++) = 0xf2;
2140 emit_rex(0,(dreg),0,(reg));
2141 *(cd->mcodeptr++) = 0x0f;
2142 *(cd->mcodeptr++) = 0x2a;
2143 emit_reg((dreg),(reg));
2147 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2148 *(cd->mcodeptr++) = 0xf3;
2149 emit_rex(0,(dreg),0,(reg));
2150 *(cd->mcodeptr++) = 0x0f;
2151 *(cd->mcodeptr++) = 0x5a;
2152 emit_reg((dreg),(reg));
2156 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2157 *(cd->mcodeptr++) = 0xf2;
2158 emit_rex(0,(dreg),0,(reg));
2159 *(cd->mcodeptr++) = 0x0f;
2160 *(cd->mcodeptr++) = 0x5a;
2161 emit_reg((dreg),(reg));
2165 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2166 *(cd->mcodeptr++) = 0xf3;
2167 emit_rex(1,(dreg),0,(reg));
2168 *(cd->mcodeptr++) = 0x0f;
2169 *(cd->mcodeptr++) = 0x2c;
2170 emit_reg((dreg),(reg));
2174 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2175 *(cd->mcodeptr++) = 0xf3;
2176 emit_rex(0,(dreg),0,(reg));
2177 *(cd->mcodeptr++) = 0x0f;
2178 *(cd->mcodeptr++) = 0x2c;
2179 emit_reg((dreg),(reg));
2183 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2184 *(cd->mcodeptr++) = 0xf2;
2185 emit_rex(1,(dreg),0,(reg));
2186 *(cd->mcodeptr++) = 0x0f;
2187 *(cd->mcodeptr++) = 0x2c;
2188 emit_reg((dreg),(reg));
2192 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2193 *(cd->mcodeptr++) = 0xf2;
2194 emit_rex(0,(dreg),0,(reg));
2195 *(cd->mcodeptr++) = 0x0f;
2196 *(cd->mcodeptr++) = 0x2c;
2197 emit_reg((dreg),(reg));
2201 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2202 *(cd->mcodeptr++) = 0xf3;
2203 emit_rex(0,(dreg),0,(reg));
2204 *(cd->mcodeptr++) = 0x0f;
2205 *(cd->mcodeptr++) = 0x5e;
2206 emit_reg((dreg),(reg));
2210 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2211 *(cd->mcodeptr++) = 0xf2;
2212 emit_rex(0,(dreg),0,(reg));
2213 *(cd->mcodeptr++) = 0x0f;
2214 *(cd->mcodeptr++) = 0x5e;
2215 emit_reg((dreg),(reg));
2219 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
2220 *(cd->mcodeptr++) = 0x66;
2221 emit_rex(1,(freg),0,(reg));
2222 *(cd->mcodeptr++) = 0x0f;
2223 *(cd->mcodeptr++) = 0x6e;
2224 emit_reg((freg),(reg));
2228 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
2229 *(cd->mcodeptr++) = 0x66;
2230 emit_rex(1,(freg),0,(reg));
2231 *(cd->mcodeptr++) = 0x0f;
2232 *(cd->mcodeptr++) = 0x7e;
2233 emit_reg((freg),(reg));
2237 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2238 *(cd->mcodeptr++) = 0x66;
2239 emit_rex(0,(reg),0,(basereg));
2240 *(cd->mcodeptr++) = 0x0f;
2241 *(cd->mcodeptr++) = 0x7e;
2242 emit_membase(cd, (basereg),(disp),(reg));
2246 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2247 *(cd->mcodeptr++) = 0x66;
2248 emit_rex(0,(reg),(indexreg),(basereg));
2249 *(cd->mcodeptr++) = 0x0f;
2250 *(cd->mcodeptr++) = 0x7e;
2251 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2255 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2256 *(cd->mcodeptr++) = 0x66;
2257 emit_rex(1,(dreg),0,(basereg));
2258 *(cd->mcodeptr++) = 0x0f;
2259 *(cd->mcodeptr++) = 0x6e;
2260 emit_membase(cd, (basereg),(disp),(dreg));
2264 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2265 *(cd->mcodeptr++) = 0x66;
2266 emit_rex(0,(dreg),0,(basereg));
2267 *(cd->mcodeptr++) = 0x0f;
2268 *(cd->mcodeptr++) = 0x6e;
2269 emit_membase(cd, (basereg),(disp),(dreg));
2273 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2274 *(cd->mcodeptr++) = 0x66;
2275 emit_rex(0,(dreg),(indexreg),(basereg));
2276 *(cd->mcodeptr++) = 0x0f;
2277 *(cd->mcodeptr++) = 0x6e;
2278 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2282 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2283 *(cd->mcodeptr++) = 0xf3;
2284 emit_rex(0,(dreg),0,(reg));
2285 *(cd->mcodeptr++) = 0x0f;
2286 *(cd->mcodeptr++) = 0x7e;
2287 emit_reg((dreg),(reg));
2291 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2292 *(cd->mcodeptr++) = 0x66;
2293 emit_rex(0,(reg),0,(basereg));
2294 *(cd->mcodeptr++) = 0x0f;
2295 *(cd->mcodeptr++) = 0xd6;
2296 emit_membase(cd, (basereg),(disp),(reg));
2300 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2301 *(cd->mcodeptr++) = 0xf3;
2302 emit_rex(0,(dreg),0,(basereg));
2303 *(cd->mcodeptr++) = 0x0f;
2304 *(cd->mcodeptr++) = 0x7e;
2305 emit_membase(cd, (basereg),(disp),(dreg));
2309 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2310 *(cd->mcodeptr++) = 0xf3;
2311 emit_rex(0,(reg),0,(dreg));
2312 *(cd->mcodeptr++) = 0x0f;
2313 *(cd->mcodeptr++) = 0x10;
2314 emit_reg((reg),(dreg));
2318 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2319 *(cd->mcodeptr++) = 0xf2;
2320 emit_rex(0,(reg),0,(dreg));
2321 *(cd->mcodeptr++) = 0x0f;
2322 *(cd->mcodeptr++) = 0x10;
2323 emit_reg((reg),(dreg));
2327 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2328 *(cd->mcodeptr++) = 0xf3;
2329 emit_rex(0,(reg),0,(basereg));
2330 *(cd->mcodeptr++) = 0x0f;
2331 *(cd->mcodeptr++) = 0x11;
2332 emit_membase(cd, (basereg),(disp),(reg));
2336 /* Always emit a REX byte, because the instruction size can be smaller when */
2337 /* all register indexes are smaller than 7. */
2338 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2339 *(cd->mcodeptr++) = 0xf3;
2340 emit_byte_rex((reg),0,(basereg));
2341 *(cd->mcodeptr++) = 0x0f;
2342 *(cd->mcodeptr++) = 0x11;
2343 emit_membase32(cd, (basereg),(disp),(reg));
2347 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2348 *(cd->mcodeptr++) = 0xf2;
2349 emit_rex(0,(reg),0,(basereg));
2350 *(cd->mcodeptr++) = 0x0f;
2351 *(cd->mcodeptr++) = 0x11;
2352 emit_membase(cd, (basereg),(disp),(reg));
2356 /* Always emit a REX byte, because the instruction size can be smaller when */
2357 /* all register indexes are smaller than 7. */
2358 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2359 *(cd->mcodeptr++) = 0xf2;
2360 emit_byte_rex((reg),0,(basereg));
2361 *(cd->mcodeptr++) = 0x0f;
2362 *(cd->mcodeptr++) = 0x11;
2363 emit_membase32(cd, (basereg),(disp),(reg));
2367 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2368 *(cd->mcodeptr++) = 0xf3;
2369 emit_rex(0,(dreg),0,(basereg));
2370 *(cd->mcodeptr++) = 0x0f;
2371 *(cd->mcodeptr++) = 0x10;
2372 emit_membase(cd, (basereg),(disp),(dreg));
2376 /* Always emit a REX byte, because the instruction size can be smaller when */
2377 /* all register indexes are smaller than 7. */
2378 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2379 *(cd->mcodeptr++) = 0xf3;
2380 emit_byte_rex((dreg),0,(basereg));
2381 *(cd->mcodeptr++) = 0x0f;
2382 *(cd->mcodeptr++) = 0x10;
2383 emit_membase32(cd, (basereg),(disp),(dreg));
2387 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2389 emit_rex(0,(dreg),0,(basereg));
2390 *(cd->mcodeptr++) = 0x0f;
2391 *(cd->mcodeptr++) = 0x12;
2392 emit_membase(cd, (basereg),(disp),(dreg));
2396 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2398 emit_rex(0,(reg),0,(basereg));
2399 *(cd->mcodeptr++) = 0x0f;
2400 *(cd->mcodeptr++) = 0x13;
2401 emit_membase(cd, (basereg),(disp),(reg));
2405 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2406 *(cd->mcodeptr++) = 0xf2;
2407 emit_rex(0,(dreg),0,(basereg));
2408 *(cd->mcodeptr++) = 0x0f;
2409 *(cd->mcodeptr++) = 0x10;
2410 emit_membase(cd, (basereg),(disp),(dreg));
2414 /* Always emit a REX byte, because the instruction size can be smaller when */
2415 /* all register indexes are smaller than 7. */
2416 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2417 *(cd->mcodeptr++) = 0xf2;
2418 emit_byte_rex((dreg),0,(basereg));
2419 *(cd->mcodeptr++) = 0x0f;
2420 *(cd->mcodeptr++) = 0x10;
2421 emit_membase32(cd, (basereg),(disp),(dreg));
2425 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2427 *(cd->mcodeptr++) = 0x66;
2428 emit_rex(0,(dreg),0,(basereg));
2429 *(cd->mcodeptr++) = 0x0f;
2430 *(cd->mcodeptr++) = 0x12;
2431 emit_membase(cd, (basereg),(disp),(dreg));
2435 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2437 *(cd->mcodeptr++) = 0x66;
2438 emit_rex(0,(reg),0,(basereg));
2439 *(cd->mcodeptr++) = 0x0f;
2440 *(cd->mcodeptr++) = 0x13;
2441 emit_membase(cd, (basereg),(disp),(reg));
2445 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2446 *(cd->mcodeptr++) = 0xf3;
2447 emit_rex(0,(reg),(indexreg),(basereg));
2448 *(cd->mcodeptr++) = 0x0f;
2449 *(cd->mcodeptr++) = 0x11;
2450 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2454 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2455 *(cd->mcodeptr++) = 0xf2;
2456 emit_rex(0,(reg),(indexreg),(basereg));
2457 *(cd->mcodeptr++) = 0x0f;
2458 *(cd->mcodeptr++) = 0x11;
2459 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2463 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2464 *(cd->mcodeptr++) = 0xf3;
2465 emit_rex(0,(dreg),(indexreg),(basereg));
2466 *(cd->mcodeptr++) = 0x0f;
2467 *(cd->mcodeptr++) = 0x10;
2468 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2472 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2473 *(cd->mcodeptr++) = 0xf2;
2474 emit_rex(0,(dreg),(indexreg),(basereg));
2475 *(cd->mcodeptr++) = 0x0f;
2476 *(cd->mcodeptr++) = 0x10;
2477 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2481 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2482 *(cd->mcodeptr++) = 0xf3;
2483 emit_rex(0,(dreg),0,(reg));
2484 *(cd->mcodeptr++) = 0x0f;
2485 *(cd->mcodeptr++) = 0x59;
2486 emit_reg((dreg),(reg));
2490 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2491 *(cd->mcodeptr++) = 0xf2;
2492 emit_rex(0,(dreg),0,(reg));
2493 *(cd->mcodeptr++) = 0x0f;
2494 *(cd->mcodeptr++) = 0x59;
2495 emit_reg((dreg),(reg));
2499 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2500 *(cd->mcodeptr++) = 0xf3;
2501 emit_rex(0,(dreg),0,(reg));
2502 *(cd->mcodeptr++) = 0x0f;
2503 *(cd->mcodeptr++) = 0x5c;
2504 emit_reg((dreg),(reg));
2508 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2509 *(cd->mcodeptr++) = 0xf2;
2510 emit_rex(0,(dreg),0,(reg));
2511 *(cd->mcodeptr++) = 0x0f;
2512 *(cd->mcodeptr++) = 0x5c;
2513 emit_reg((dreg),(reg));
2517 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2518 emit_rex(0,(dreg),0,(reg));
2519 *(cd->mcodeptr++) = 0x0f;
2520 *(cd->mcodeptr++) = 0x2e;
2521 emit_reg((dreg),(reg));
2525 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2526 *(cd->mcodeptr++) = 0x66;
2527 emit_rex(0,(dreg),0,(reg));
2528 *(cd->mcodeptr++) = 0x0f;
2529 *(cd->mcodeptr++) = 0x2e;
2530 emit_reg((dreg),(reg));
2534 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2535 emit_rex(0,(dreg),0,(reg));
2536 *(cd->mcodeptr++) = 0x0f;
2537 *(cd->mcodeptr++) = 0x57;
2538 emit_reg((dreg),(reg));
2542 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2543 emit_rex(0,(dreg),0,(basereg));
2544 *(cd->mcodeptr++) = 0x0f;
2545 *(cd->mcodeptr++) = 0x57;
2546 emit_membase(cd, (basereg),(disp),(dreg));
2550 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2551 *(cd->mcodeptr++) = 0x66;
2552 emit_rex(0,(dreg),0,(reg));
2553 *(cd->mcodeptr++) = 0x0f;
2554 *(cd->mcodeptr++) = 0x57;
2555 emit_reg((dreg),(reg));
2559 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2560 *(cd->mcodeptr++) = 0x66;
2561 emit_rex(0,(dreg),0,(basereg));
2562 *(cd->mcodeptr++) = 0x0f;
2563 *(cd->mcodeptr++) = 0x57;
2564 emit_membase(cd, (basereg),(disp),(dreg));
2568 /* system instructions ********************************************************/
2570 void emit_rdtsc(codegendata *cd)
2572 *(cd->mcodeptr++) = 0x0f;
2573 *(cd->mcodeptr++) = 0x31;
2578 * These are local overrides for various environment variables in Emacs.
2579 * Please do not remove this and leave it at the end of the file, where
2580 * Emacs will automagically detect them.
2581 * ---------------------------------------------------------------------
2584 * indent-tabs-mode: t