1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 Contact: cacao@cacaojvm.org
27 Authors: Christian Thalinger
29 $Id: emit.c 6137 2006-12-07 22:25:42Z edwin $
39 #include "vm/jit/x86_64/codegen.h"
40 #include "vm/jit/x86_64/emit.h"
42 #if defined(ENABLE_THREADS)
43 # include "threads/native/lock.h"
46 #include "vm/builtin.h"
47 #include "vm/options.h"
48 #include "vm/jit/abi-asm.h"
49 #include "vm/jit/asmpart.h"
50 #include "vm/jit/codegen-common.h"
51 #include "vm/jit/emit-common.h"
52 #include "vm/jit/jit.h"
53 #include "vm/jit/replace.h"
56 /* emit_load *******************************************************************
58 Emits a possible load of an operand.
60 *******************************************************************************/
62 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
68 /* get required compiler data */
72 if (IS_INMEMORY(src->flags)) {
75 disp = src->vv.regoff * 8;
77 if (IS_FLT_DBL_TYPE(src->type)) {
78 if (IS_2_WORD_TYPE(src->type))
79 M_DLD(tempreg, REG_SP, disp);
81 M_FLD(tempreg, REG_SP, disp);
84 if (IS_INT_TYPE(src->type))
85 M_ILD(tempreg, REG_SP, disp);
87 M_LLD(tempreg, REG_SP, disp);
99 /* emit_store ******************************************************************
101 This function generates the code to store the result of an
102 operation back into a spilled pseudo-variable. If the
103 pseudo-variable has not been spilled in the first place, this
104 function will generate nothing.
106 *******************************************************************************/
108 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
117 /* get required compiler data */
122 /* do we have to generate a conditional move? */
124 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
125 /* the passed register d is actually the source register */
129 /* Only pass the opcode to codegen_reg_of_var to get the real
130 destination register. */
132 opcode = iptr->opc & ICMD_OPCODE_MASK;
134 /* get the real destination register */
136 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
138 /* and emit the conditional move */
140 emit_cmovxx(cd, iptr, s, d);
144 if (IS_INMEMORY(dst->flags)) {
147 disp = dst->vv.regoff * 8;
149 if (IS_FLT_DBL_TYPE(dst->type)) {
150 if (IS_2_WORD_TYPE(dst->type))
151 M_DST(d, REG_SP, disp);
153 M_FST(d, REG_SP, disp);
156 M_LST(d, REG_SP, disp);
161 /* emit_copy *******************************************************************
163 Generates a register/memory to register/memory copy.
165 *******************************************************************************/
167 void emit_copy(jitdata *jd, instruction *iptr, varinfo *src, varinfo *dst)
172 /* get required compiler data */
176 if ((src->vv.regoff != dst->vv.regoff) ||
177 ((src->flags ^ dst->flags) & INMEMORY)) {
179 /* If one of the variables resides in memory, we can eliminate
180 the register move from/to the temporary register with the
181 order of getting the destination register and the load. */
183 if (IS_INMEMORY(src->flags)) {
184 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
185 s1 = emit_load(jd, iptr, src, d);
188 s1 = emit_load(jd, iptr, src, REG_IFTMP);
189 d = codegen_reg_of_var(iptr->opc, dst, s1);
193 if (IS_FLT_DBL_TYPE(src->type))
199 emit_store(jd, iptr, dst, d);
204 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
207 switch (iptr->flags.fields.condition) {
231 /* emit_arithmetic_check *******************************************************
233 Emit an ArithmeticException check.
235 *******************************************************************************/
237 void emit_arithmetic_check(codegendata *cd, s4 reg)
242 codegen_add_arithmeticexception_ref(cd);
247 /* emit_arrayindexoutofbounds_check ********************************************
249 Emit a ArrayIndexOutOfBoundsException check.
251 *******************************************************************************/
253 void emit_arrayindexoutofbounds_check(codegendata *cd, s4 s1, s4 s2)
256 M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));
257 M_ICMP(REG_ITMP3, s2);
259 codegen_add_arrayindexoutofboundsexception_ref(cd, s2);
264 /* emit_classcast_check ********************************************************
266 Emit a ClassCastException check.
268 *******************************************************************************/
270 void emit_classcast_check(codegendata *cd, s4 condition, s4 reg, s4 s1)
272 vm_abort("IMPLEMENT ME!");
276 /* emit_nullpointer_check ******************************************************
278 Emit a NullPointerException check.
280 *******************************************************************************/
282 void emit_nullpointer_check(codegendata *cd, s4 reg)
287 codegen_add_nullpointerexception_ref(cd);
292 /* emit_exception_stubs ********************************************************
294 Generates the code for the exception stubs.
296 *******************************************************************************/
298 void emit_exception_stubs(jitdata *jd)
307 /* get required compiler data */
312 /* generate exception stubs */
316 for (er = cd->exceptionrefs; er != NULL; er = er->next) {
317 /* back-patch the branch to this exception code */
319 branchmpc = er->branchpos;
320 targetmpc = cd->mcodeptr - cd->mcodebase;
322 md_codegen_patch_branch(cd, branchmpc, targetmpc);
326 /* Check if the exception is an
327 ArrayIndexOutOfBoundsException. If so, move index register
331 M_MOV(er->reg, rd->argintregs[4]);
333 /* calcuate exception address */
335 M_MOV_IMM(0, rd->argintregs[3]);
337 M_AADD_IMM32(er->branchpos - 6, rd->argintregs[3]);
339 /* move function to call into REG_ITMP3 */
341 M_MOV_IMM(er->function, REG_ITMP3);
343 if (targetdisp == 0) {
344 targetdisp = cd->mcodeptr - cd->mcodebase;
346 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase), rd->argintregs[0]);
347 M_MOV(REG_SP, rd->argintregs[1]);
348 M_ALD(rd->argintregs[2], REG_SP, cd->stackframesize * 8);
350 M_ASUB_IMM(2 * 8, REG_SP);
351 M_AST(rd->argintregs[3], REG_SP, 0 * 8); /* store XPC */
355 M_ALD(REG_ITMP2_XPC, REG_SP, 0 * 8);
356 M_AADD_IMM(2 * 8, REG_SP);
358 M_MOV_IMM(asm_handle_exception, REG_ITMP3);
362 M_JMP_IMM((cd->mcodebase + targetdisp) -
363 (cd->mcodeptr + PATCHER_CALL_SIZE));
369 /* emit_patcher_stubs **********************************************************
371 Generates the code for the patcher stubs.
373 *******************************************************************************/
375 void emit_patcher_stubs(jitdata *jd)
385 /* get required compiler data */
389 /* generate code patching stub call code */
393 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
394 /* check size of code segment */
398 /* Get machine code which is patched back in later. A
399 `call rel32' is 5 bytes long (but read 8 bytes). */
401 savedmcodeptr = cd->mcodebase + pref->branchpos;
402 mcode = *((u8 *) savedmcodeptr);
404 /* patch in `call rel32' to call the following code */
406 tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
407 cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
409 M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE));
411 cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
413 /* move pointer to java_objectheader onto stack */
415 #if defined(ENABLE_THREADS)
416 /* create a virtual java_objectheader */
418 (void) dseg_add_unique_address(cd, NULL); /* flcword */
419 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
420 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
422 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase) + disp, REG_ITMP3);
428 /* move machine code bytes and classinfo pointer into registers */
430 M_MOV_IMM(mcode, REG_ITMP3);
433 M_MOV_IMM(pref->ref, REG_ITMP3);
436 M_MOV_IMM(pref->disp, REG_ITMP3);
439 M_MOV_IMM(pref->patcher, REG_ITMP3);
442 if (targetdisp == 0) {
443 targetdisp = cd->mcodeptr - cd->mcodebase;
445 M_MOV_IMM(asm_patcher_wrapper, REG_ITMP3);
449 M_JMP_IMM((cd->mcodebase + targetdisp) -
450 (cd->mcodeptr + PATCHER_CALL_SIZE));
456 /* emit_replacement_stubs ******************************************************
458 Generates the code for the replacement stubs.
460 *******************************************************************************/
462 void emit_replacement_stubs(jitdata *jd)
473 /* get required compiler data */
478 rplp = code->rplpoints;
480 /* store beginning of replacement stubs */
482 code->replacementstubs = (u1*) (cd->mcodeptr - cd->mcodebase);
484 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
485 /* do not generate stubs for non-trappable points */
487 if (rplp->flags & RPLPOINT_FLAG_NOTRAP)
490 /* check code segment size */
494 /* note start of stub code */
497 savedmcodeptr = cd->mcodeptr;
500 /* push address of `rplpoint` struct */
504 /* jump to replacement function */
506 M_PUSH_IMM(asm_replacement_out);
509 assert((cd->mcodeptr - savedmcodeptr) == REPLACEMENT_STUB_SIZE);
514 /* emit_verbosecall_enter ******************************************************
516 Generates the code for the call trace.
518 *******************************************************************************/
521 void emit_verbosecall_enter(jitdata *jd)
529 /* get required compiler data */
537 /* mark trace code */
541 /* additional +1 is for 16-byte stack alignment */
543 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
545 /* save argument registers */
547 for (i = 0; i < INT_ARG_CNT; i++)
548 M_LST(rd->argintregs[i], REG_SP, (1 + i) * 8);
550 for (i = 0; i < FLT_ARG_CNT; i++)
551 M_DST(rd->argfltregs[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
553 /* save temporary registers for leaf methods */
555 if (jd->isleafmethod) {
556 for (i = 0; i < INT_TMP_CNT; i++)
557 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
559 for (i = 0; i < FLT_TMP_CNT; i++)
560 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
563 /* show integer hex code for float arguments */
565 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
566 /* If the paramtype is a float, we have to right shift all
567 following integer registers. */
569 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
570 for (k = INT_ARG_CNT - 2; k >= i; k--)
571 M_MOV(rd->argintregs[k], rd->argintregs[k + 1]);
573 emit_movd_freg_reg(cd, rd->argfltregs[j], rd->argintregs[i]);
578 M_MOV_IMM(m, REG_ITMP2);
579 M_AST(REG_ITMP2, REG_SP, 0 * 8);
580 M_MOV_IMM(builtin_trace_args, REG_ITMP1);
583 /* restore argument registers */
585 for (i = 0; i < INT_ARG_CNT; i++)
586 M_LLD(rd->argintregs[i], REG_SP, (1 + i) * 8);
588 for (i = 0; i < FLT_ARG_CNT; i++)
589 M_DLD(rd->argfltregs[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
591 /* restore temporary registers for leaf methods */
593 if (jd->isleafmethod) {
594 for (i = 0; i < INT_TMP_CNT; i++)
595 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
597 for (i = 0; i < FLT_TMP_CNT; i++)
598 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
601 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
603 /* mark trace code */
607 #endif /* !defined(NDEBUG) */
610 /* emit_verbosecall_exit *******************************************************
612 Generates the code for the call trace.
614 *******************************************************************************/
617 void emit_verbosecall_exit(jitdata *jd)
623 /* get required compiler data */
629 /* mark trace code */
633 M_ASUB_IMM(2 * 8, REG_SP);
635 M_LST(REG_RESULT, REG_SP, 0 * 8);
636 M_DST(REG_FRESULT, REG_SP, 1 * 8);
638 M_MOV_IMM(m, rd->argintregs[0]);
639 M_MOV(REG_RESULT, rd->argintregs[1]);
640 M_FLTMOVE(REG_FRESULT, rd->argfltregs[0]);
641 M_FLTMOVE(REG_FRESULT, rd->argfltregs[1]);
643 M_MOV_IMM(builtin_displaymethodstop, REG_ITMP1);
646 M_LLD(REG_RESULT, REG_SP, 0 * 8);
647 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
649 M_AADD_IMM(2 * 8, REG_SP);
651 /* mark trace code */
655 #endif /* !defined(NDEBUG) */
658 /* code generation functions **************************************************/
660 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
662 if ((basereg == REG_SP) || (basereg == R12)) {
664 emit_address_byte(0, dreg, REG_SP);
665 emit_address_byte(0, REG_SP, REG_SP);
667 } else if (IS_IMM8(disp)) {
668 emit_address_byte(1, dreg, REG_SP);
669 emit_address_byte(0, REG_SP, REG_SP);
673 emit_address_byte(2, dreg, REG_SP);
674 emit_address_byte(0, REG_SP, REG_SP);
678 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
679 emit_address_byte(0,(dreg),(basereg));
681 } else if ((basereg) == RIP) {
682 emit_address_byte(0, dreg, RBP);
687 emit_address_byte(1, dreg, basereg);
691 emit_address_byte(2, dreg, basereg);
698 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
700 if ((basereg == REG_SP) || (basereg == R12)) {
701 emit_address_byte(2, dreg, REG_SP);
702 emit_address_byte(0, REG_SP, REG_SP);
706 emit_address_byte(2, dreg, basereg);
712 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
715 emit_address_byte(0, reg, 4);
716 emit_address_byte(scale, indexreg, 5);
719 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
720 emit_address_byte(0, reg, 4);
721 emit_address_byte(scale, indexreg, basereg);
723 else if (IS_IMM8(disp)) {
724 emit_address_byte(1, reg, 4);
725 emit_address_byte(scale, indexreg, basereg);
729 emit_address_byte(2, reg, 4);
730 emit_address_byte(scale, indexreg, basereg);
736 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
739 varinfo *v_s1,*v_s2,*v_dst;
742 /* get required compiler data */
746 v_s1 = VAROP(iptr->s1);
747 v_s2 = VAROP(iptr->sx.s23.s2);
748 v_dst = VAROP(iptr->dst);
750 s1 = v_s1->vv.regoff;
751 s2 = v_s2->vv.regoff;
752 d = v_dst->vv.regoff;
754 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
756 if (IS_INMEMORY(v_dst->flags)) {
757 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
759 M_ILD(RCX, REG_SP, s2 * 8);
760 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
763 M_ILD(RCX, REG_SP, s2 * 8);
764 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
765 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
766 M_IST(REG_ITMP2, REG_SP, d * 8);
769 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
770 /* s1 may be equal to RCX */
773 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
774 M_IST(s1, REG_SP, d * 8);
775 M_INTMOVE(REG_ITMP1, RCX);
778 M_IST(s1, REG_SP, d * 8);
779 M_ILD(RCX, REG_SP, s2 * 8);
783 M_ILD(RCX, REG_SP, s2 * 8);
784 M_IST(s1, REG_SP, d * 8);
787 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
789 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
792 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
796 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
797 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
798 M_IST(REG_ITMP2, REG_SP, d * 8);
802 /* s1 may be equal to RCX */
803 M_IST(s1, REG_SP, d * 8);
805 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
808 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
816 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
817 M_ILD(RCX, REG_SP, s2 * 8);
818 M_ILD(d, REG_SP, s1 * 8);
819 emit_shiftl_reg(cd, shift_op, d);
821 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
822 /* s1 may be equal to RCX */
824 M_ILD(RCX, REG_SP, s2 * 8);
825 emit_shiftl_reg(cd, shift_op, d);
827 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
829 M_ILD(d, REG_SP, s1 * 8);
830 emit_shiftl_reg(cd, shift_op, d);
833 /* s1 may be equal to RCX */
836 /* d cannot be used to backup s1 since this would
838 M_INTMOVE(s1, REG_ITMP3);
840 M_INTMOVE(REG_ITMP3, d);
848 /* d may be equal to s2 */
852 emit_shiftl_reg(cd, shift_op, d);
856 M_INTMOVE(REG_ITMP3, RCX);
858 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
863 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
866 varinfo *v_s1,*v_s2,*v_dst;
869 /* get required compiler data */
873 v_s1 = VAROP(iptr->s1);
874 v_s2 = VAROP(iptr->sx.s23.s2);
875 v_dst = VAROP(iptr->dst);
877 s1 = v_s1->vv.regoff;
878 s2 = v_s2->vv.regoff;
879 d = v_dst->vv.regoff;
881 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
883 if (IS_INMEMORY(v_dst->flags)) {
884 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
886 M_ILD(RCX, REG_SP, s2 * 8);
887 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
890 M_ILD(RCX, REG_SP, s2 * 8);
891 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
892 emit_shift_reg(cd, shift_op, REG_ITMP2);
893 M_LST(REG_ITMP2, REG_SP, d * 8);
896 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
897 /* s1 may be equal to RCX */
900 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
901 M_LST(s1, REG_SP, d * 8);
902 M_INTMOVE(REG_ITMP1, RCX);
905 M_LST(s1, REG_SP, d * 8);
906 M_ILD(RCX, REG_SP, s2 * 8);
910 M_ILD(RCX, REG_SP, s2 * 8);
911 M_LST(s1, REG_SP, d * 8);
914 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
916 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
919 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
923 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
924 emit_shift_reg(cd, shift_op, REG_ITMP2);
925 M_LST(REG_ITMP2, REG_SP, d * 8);
929 /* s1 may be equal to RCX */
930 M_LST(s1, REG_SP, d * 8);
932 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
935 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
943 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
944 M_ILD(RCX, REG_SP, s2 * 8);
945 M_LLD(d, REG_SP, s1 * 8);
946 emit_shift_reg(cd, shift_op, d);
948 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
949 /* s1 may be equal to RCX */
951 M_ILD(RCX, REG_SP, s2 * 8);
952 emit_shift_reg(cd, shift_op, d);
954 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
956 M_LLD(d, REG_SP, s1 * 8);
957 emit_shift_reg(cd, shift_op, d);
960 /* s1 may be equal to RCX */
963 /* d cannot be used to backup s1 since this would
965 M_INTMOVE(s1, REG_ITMP3);
967 M_INTMOVE(REG_ITMP3, d);
975 /* d may be equal to s2 */
979 emit_shift_reg(cd, shift_op, d);
983 M_INTMOVE(REG_ITMP3, RCX);
985 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
990 /* low-level code emitter functions *******************************************/
992 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
994 emit_rex(1,(reg),0,(dreg));
995 *(cd->mcodeptr++) = 0x89;
996 emit_reg((reg),(dreg));
1000 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1002 emit_rex(1,0,0,(reg));
1003 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1008 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1010 emit_rex(0,(reg),0,(dreg));
1011 *(cd->mcodeptr++) = 0x89;
1012 emit_reg((reg),(dreg));
1016 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1017 emit_rex(0,0,0,(reg));
1018 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1023 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1024 emit_rex(1,(reg),0,(basereg));
1025 *(cd->mcodeptr++) = 0x8b;
1026 emit_membase(cd, (basereg),(disp),(reg));
1031 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1032 * constant membase immediate length of 32bit
1034 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1035 emit_rex(1,(reg),0,(basereg));
1036 *(cd->mcodeptr++) = 0x8b;
1037 emit_membase32(cd, (basereg),(disp),(reg));
1041 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1043 emit_rex(0,(reg),0,(basereg));
1044 *(cd->mcodeptr++) = 0x8b;
1045 emit_membase(cd, (basereg),(disp),(reg));
1049 /* ATTENTION: Always emit a REX byte, because the instruction size can
1050 be smaller when all register indexes are smaller than 7. */
1051 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1053 emit_byte_rex((reg),0,(basereg));
1054 *(cd->mcodeptr++) = 0x8b;
1055 emit_membase32(cd, (basereg),(disp),(reg));
1059 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1060 emit_rex(1,(reg),0,(basereg));
1061 *(cd->mcodeptr++) = 0x89;
1062 emit_membase(cd, (basereg),(disp),(reg));
1066 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1067 emit_rex(1,(reg),0,(basereg));
1068 *(cd->mcodeptr++) = 0x89;
1069 emit_membase32(cd, (basereg),(disp),(reg));
1073 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1074 emit_rex(0,(reg),0,(basereg));
1075 *(cd->mcodeptr++) = 0x89;
1076 emit_membase(cd, (basereg),(disp),(reg));
1080 /* Always emit a REX byte, because the instruction size can be smaller when */
1081 /* all register indexes are smaller than 7. */
1082 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1083 emit_byte_rex((reg),0,(basereg));
1084 *(cd->mcodeptr++) = 0x89;
1085 emit_membase32(cd, (basereg),(disp),(reg));
1089 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1090 emit_rex(1,(reg),(indexreg),(basereg));
1091 *(cd->mcodeptr++) = 0x8b;
1092 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1096 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1097 emit_rex(0,(reg),(indexreg),(basereg));
1098 *(cd->mcodeptr++) = 0x8b;
1099 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1103 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1104 emit_rex(1,(reg),(indexreg),(basereg));
1105 *(cd->mcodeptr++) = 0x89;
1106 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1110 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1111 emit_rex(0,(reg),(indexreg),(basereg));
1112 *(cd->mcodeptr++) = 0x89;
1113 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1117 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1118 *(cd->mcodeptr++) = 0x66;
1119 emit_rex(0,(reg),(indexreg),(basereg));
1120 *(cd->mcodeptr++) = 0x89;
1121 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1125 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1126 emit_byte_rex((reg),(indexreg),(basereg));
1127 *(cd->mcodeptr++) = 0x88;
1128 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1132 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1133 emit_rex(1,0,0,(basereg));
1134 *(cd->mcodeptr++) = 0xc7;
1135 emit_membase(cd, (basereg),(disp),0);
1140 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1141 emit_rex(1,0,0,(basereg));
1142 *(cd->mcodeptr++) = 0xc7;
1143 emit_membase32(cd, (basereg),(disp),0);
1148 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1149 emit_rex(0,0,0,(basereg));
1150 *(cd->mcodeptr++) = 0xc7;
1151 emit_membase(cd, (basereg),(disp),0);
1156 /* Always emit a REX byte, because the instruction size can be smaller when */
1157 /* all register indexes are smaller than 7. */
1158 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1159 emit_byte_rex(0,0,(basereg));
1160 *(cd->mcodeptr++) = 0xc7;
1161 emit_membase32(cd, (basereg),(disp),0);
1166 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1168 emit_rex(1,(dreg),0,(reg));
1169 *(cd->mcodeptr++) = 0x0f;
1170 *(cd->mcodeptr++) = 0xbe;
1171 /* XXX: why do reg and dreg have to be exchanged */
1172 emit_reg((dreg),(reg));
1176 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1178 emit_rex(1,(dreg),0,(reg));
1179 *(cd->mcodeptr++) = 0x0f;
1180 *(cd->mcodeptr++) = 0xbf;
1181 /* XXX: why do reg and dreg have to be exchanged */
1182 emit_reg((dreg),(reg));
1186 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1188 emit_rex(1,(dreg),0,(reg));
1189 *(cd->mcodeptr++) = 0x63;
1190 /* XXX: why do reg and dreg have to be exchanged */
1191 emit_reg((dreg),(reg));
1195 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1197 emit_rex(1,(dreg),0,(reg));
1198 *(cd->mcodeptr++) = 0x0f;
1199 *(cd->mcodeptr++) = 0xb7;
1200 /* XXX: why do reg and dreg have to be exchanged */
1201 emit_reg((dreg),(reg));
1205 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1206 emit_rex(1,(reg),(indexreg),(basereg));
1207 *(cd->mcodeptr++) = 0x0f;
1208 *(cd->mcodeptr++) = 0xbf;
1209 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1213 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1214 emit_rex(1,(reg),(indexreg),(basereg));
1215 *(cd->mcodeptr++) = 0x0f;
1216 *(cd->mcodeptr++) = 0xbe;
1217 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1221 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1222 emit_rex(1,(reg),(indexreg),(basereg));
1223 *(cd->mcodeptr++) = 0x0f;
1224 *(cd->mcodeptr++) = 0xb7;
1225 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1229 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1231 emit_rex(1,0,(indexreg),(basereg));
1232 *(cd->mcodeptr++) = 0xc7;
1233 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1238 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1240 emit_rex(0,0,(indexreg),(basereg));
1241 *(cd->mcodeptr++) = 0xc7;
1242 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1247 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1249 *(cd->mcodeptr++) = 0x66;
1250 emit_rex(0,0,(indexreg),(basereg));
1251 *(cd->mcodeptr++) = 0xc7;
1252 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1257 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1259 emit_rex(0,0,(indexreg),(basereg));
1260 *(cd->mcodeptr++) = 0xc6;
1261 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1269 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1271 emit_rex(1,(reg),0,(dreg));
1272 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1273 emit_reg((reg),(dreg));
1277 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1279 emit_rex(0,(reg),0,(dreg));
1280 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1281 emit_reg((reg),(dreg));
1285 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1287 emit_rex(1,(reg),0,(basereg));
1288 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1289 emit_membase(cd, (basereg),(disp),(reg));
1293 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1295 emit_rex(0,(reg),0,(basereg));
1296 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1297 emit_membase(cd, (basereg),(disp),(reg));
1301 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1303 emit_rex(1,(reg),0,(basereg));
1304 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1305 emit_membase(cd, (basereg),(disp),(reg));
1309 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1311 emit_rex(0,(reg),0,(basereg));
1312 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1313 emit_membase(cd, (basereg),(disp),(reg));
1317 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1319 emit_rex(1,0,0,(dreg));
1320 *(cd->mcodeptr++) = 0x83;
1321 emit_reg((opc),(dreg));
1324 emit_rex(1,0,0,(dreg));
1325 *(cd->mcodeptr++) = 0x81;
1326 emit_reg((opc),(dreg));
1332 void emit_alu_imm32_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1333 emit_rex(1,0,0,(dreg));
1334 *(cd->mcodeptr++) = 0x81;
1335 emit_reg((opc),(dreg));
1340 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1342 emit_rex(0,0,0,(dreg));
1343 *(cd->mcodeptr++) = 0x83;
1344 emit_reg((opc),(dreg));
1347 emit_rex(0,0,0,(dreg));
1348 *(cd->mcodeptr++) = 0x81;
1349 emit_reg((opc),(dreg));
1355 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1357 emit_rex(1,(basereg),0,0);
1358 *(cd->mcodeptr++) = 0x83;
1359 emit_membase(cd, (basereg),(disp),(opc));
1362 emit_rex(1,(basereg),0,0);
1363 *(cd->mcodeptr++) = 0x81;
1364 emit_membase(cd, (basereg),(disp),(opc));
1370 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1372 emit_rex(0,(basereg),0,0);
1373 *(cd->mcodeptr++) = 0x83;
1374 emit_membase(cd, (basereg),(disp),(opc));
1377 emit_rex(0,(basereg),0,0);
1378 *(cd->mcodeptr++) = 0x81;
1379 emit_membase(cd, (basereg),(disp),(opc));
1385 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1386 emit_rex(1,(reg),0,(dreg));
1387 *(cd->mcodeptr++) = 0x85;
1388 emit_reg((reg),(dreg));
1392 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1393 emit_rex(0,(reg),0,(dreg));
1394 *(cd->mcodeptr++) = 0x85;
1395 emit_reg((reg),(dreg));
1399 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1400 *(cd->mcodeptr++) = 0xf7;
1406 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1407 *(cd->mcodeptr++) = 0x66;
1408 *(cd->mcodeptr++) = 0xf7;
1414 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1415 *(cd->mcodeptr++) = 0xf6;
1421 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1422 emit_rex(1,(reg),0,(basereg));
1423 *(cd->mcodeptr++) = 0x8d;
1424 emit_membase(cd, (basereg),(disp),(reg));
1428 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1429 emit_rex(0,(reg),0,(basereg));
1430 *(cd->mcodeptr++) = 0x8d;
1431 emit_membase(cd, (basereg),(disp),(reg));
1436 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1438 emit_rex(0,0,0,(basereg));
1439 *(cd->mcodeptr++) = 0xff;
1440 emit_membase(cd, (basereg),(disp),0);
1445 void emit_cltd(codegendata *cd) {
1446 *(cd->mcodeptr++) = 0x99;
1450 void emit_cqto(codegendata *cd) {
1452 *(cd->mcodeptr++) = 0x99;
1457 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1458 emit_rex(1,(dreg),0,(reg));
1459 *(cd->mcodeptr++) = 0x0f;
1460 *(cd->mcodeptr++) = 0xaf;
1461 emit_reg((dreg),(reg));
1465 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1466 emit_rex(0,(dreg),0,(reg));
1467 *(cd->mcodeptr++) = 0x0f;
1468 *(cd->mcodeptr++) = 0xaf;
1469 emit_reg((dreg),(reg));
1473 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1474 emit_rex(1,(dreg),0,(basereg));
1475 *(cd->mcodeptr++) = 0x0f;
1476 *(cd->mcodeptr++) = 0xaf;
1477 emit_membase(cd, (basereg),(disp),(dreg));
1481 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1482 emit_rex(0,(dreg),0,(basereg));
1483 *(cd->mcodeptr++) = 0x0f;
1484 *(cd->mcodeptr++) = 0xaf;
1485 emit_membase(cd, (basereg),(disp),(dreg));
1489 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1490 if (IS_IMM8((imm))) {
1491 emit_rex(1,0,0,(dreg));
1492 *(cd->mcodeptr++) = 0x6b;
1496 emit_rex(1,0,0,(dreg));
1497 *(cd->mcodeptr++) = 0x69;
1504 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1505 if (IS_IMM8((imm))) {
1506 emit_rex(1,(dreg),0,(reg));
1507 *(cd->mcodeptr++) = 0x6b;
1508 emit_reg((dreg),(reg));
1511 emit_rex(1,(dreg),0,(reg));
1512 *(cd->mcodeptr++) = 0x69;
1513 emit_reg((dreg),(reg));
1519 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1520 if (IS_IMM8((imm))) {
1521 emit_rex(0,(dreg),0,(reg));
1522 *(cd->mcodeptr++) = 0x6b;
1523 emit_reg((dreg),(reg));
1526 emit_rex(0,(dreg),0,(reg));
1527 *(cd->mcodeptr++) = 0x69;
1528 emit_reg((dreg),(reg));
1534 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1535 if (IS_IMM8((imm))) {
1536 emit_rex(1,(dreg),0,(basereg));
1537 *(cd->mcodeptr++) = 0x6b;
1538 emit_membase(cd, (basereg),(disp),(dreg));
1541 emit_rex(1,(dreg),0,(basereg));
1542 *(cd->mcodeptr++) = 0x69;
1543 emit_membase(cd, (basereg),(disp),(dreg));
1549 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1550 if (IS_IMM8((imm))) {
1551 emit_rex(0,(dreg),0,(basereg));
1552 *(cd->mcodeptr++) = 0x6b;
1553 emit_membase(cd, (basereg),(disp),(dreg));
1556 emit_rex(0,(dreg),0,(basereg));
1557 *(cd->mcodeptr++) = 0x69;
1558 emit_membase(cd, (basereg),(disp),(dreg));
1564 void emit_idiv_reg(codegendata *cd, s8 reg) {
1565 emit_rex(1,0,0,(reg));
1566 *(cd->mcodeptr++) = 0xf7;
1571 void emit_idivl_reg(codegendata *cd, s8 reg) {
1572 emit_rex(0,0,0,(reg));
1573 *(cd->mcodeptr++) = 0xf7;
1579 void emit_ret(codegendata *cd) {
1580 *(cd->mcodeptr++) = 0xc3;
1588 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1589 emit_rex(1,0,0,(reg));
1590 *(cd->mcodeptr++) = 0xd3;
1591 emit_reg((opc),(reg));
1595 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1596 emit_rex(0,0,0,(reg));
1597 *(cd->mcodeptr++) = 0xd3;
1598 emit_reg((opc),(reg));
1602 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1603 emit_rex(1,0,0,(basereg));
1604 *(cd->mcodeptr++) = 0xd3;
1605 emit_membase(cd, (basereg),(disp),(opc));
1609 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1610 emit_rex(0,0,0,(basereg));
1611 *(cd->mcodeptr++) = 0xd3;
1612 emit_membase(cd, (basereg),(disp),(opc));
1616 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1618 emit_rex(1,0,0,(dreg));
1619 *(cd->mcodeptr++) = 0xd1;
1620 emit_reg((opc),(dreg));
1622 emit_rex(1,0,0,(dreg));
1623 *(cd->mcodeptr++) = 0xc1;
1624 emit_reg((opc),(dreg));
1630 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1632 emit_rex(0,0,0,(dreg));
1633 *(cd->mcodeptr++) = 0xd1;
1634 emit_reg((opc),(dreg));
1636 emit_rex(0,0,0,(dreg));
1637 *(cd->mcodeptr++) = 0xc1;
1638 emit_reg((opc),(dreg));
1644 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1646 emit_rex(1,0,0,(basereg));
1647 *(cd->mcodeptr++) = 0xd1;
1648 emit_membase(cd, (basereg),(disp),(opc));
1650 emit_rex(1,0,0,(basereg));
1651 *(cd->mcodeptr++) = 0xc1;
1652 emit_membase(cd, (basereg),(disp),(opc));
1658 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1660 emit_rex(0,0,0,(basereg));
1661 *(cd->mcodeptr++) = 0xd1;
1662 emit_membase(cd, (basereg),(disp),(opc));
1664 emit_rex(0,0,0,(basereg));
1665 *(cd->mcodeptr++) = 0xc1;
1666 emit_membase(cd, (basereg),(disp),(opc));
1676 void emit_jmp_imm(codegendata *cd, s8 imm) {
1677 *(cd->mcodeptr++) = 0xe9;
1682 void emit_jmp_reg(codegendata *cd, s8 reg) {
1683 emit_rex(0,0,0,(reg));
1684 *(cd->mcodeptr++) = 0xff;
1689 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1690 *(cd->mcodeptr++) = 0x0f;
1691 *(cd->mcodeptr++) = (0x80 + (opc));
1698 * conditional set and move operations
1701 /* we need the rex byte to get all low bytes */
1702 void emit_setcc_reg(codegendata *cd, s8 opc, s8 reg) {
1703 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1704 *(cd->mcodeptr++) = 0x0f;
1705 *(cd->mcodeptr++) = (0x90 + (opc));
1710 /* we need the rex byte to get all low bytes */
1711 void emit_setcc_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1712 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1713 *(cd->mcodeptr++) = 0x0f;
1714 *(cd->mcodeptr++) = (0x90 + (opc));
1715 emit_membase(cd, (basereg),(disp),0);
1719 void emit_cmovcc_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1721 emit_rex(1,(dreg),0,(reg));
1722 *(cd->mcodeptr++) = 0x0f;
1723 *(cd->mcodeptr++) = (0x40 + (opc));
1724 emit_reg((dreg),(reg));
1728 void emit_cmovccl_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1730 emit_rex(0,(dreg),0,(reg));
1731 *(cd->mcodeptr++) = 0x0f;
1732 *(cd->mcodeptr++) = (0x40 + (opc));
1733 emit_reg((dreg),(reg));
1738 void emit_neg_reg(codegendata *cd, s8 reg)
1740 emit_rex(1,0,0,(reg));
1741 *(cd->mcodeptr++) = 0xf7;
1746 void emit_negl_reg(codegendata *cd, s8 reg)
1748 emit_rex(0,0,0,(reg));
1749 *(cd->mcodeptr++) = 0xf7;
1754 void emit_push_reg(codegendata *cd, s8 reg) {
1755 emit_rex(0,0,0,(reg));
1756 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1760 void emit_push_imm(codegendata *cd, s8 imm) {
1761 *(cd->mcodeptr++) = 0x68;
1766 void emit_pop_reg(codegendata *cd, s8 reg) {
1767 emit_rex(0,0,0,(reg));
1768 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1772 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1773 emit_rex(1,(reg),0,(dreg));
1774 *(cd->mcodeptr++) = 0x87;
1775 emit_reg((reg),(dreg));
1779 void emit_nop(codegendata *cd) {
1780 *(cd->mcodeptr++) = 0x90;
1788 void emit_call_reg(codegendata *cd, s8 reg) {
1789 emit_rex(1,0,0,(reg));
1790 *(cd->mcodeptr++) = 0xff;
1795 void emit_call_imm(codegendata *cd, s8 imm) {
1796 *(cd->mcodeptr++) = 0xe8;
1801 void emit_call_mem(codegendata *cd, ptrint mem)
1803 *(cd->mcodeptr++) = 0xff;
1810 * floating point instructions (SSE2)
1812 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1813 *(cd->mcodeptr++) = 0xf2;
1814 emit_rex(0,(dreg),0,(reg));
1815 *(cd->mcodeptr++) = 0x0f;
1816 *(cd->mcodeptr++) = 0x58;
1817 emit_reg((dreg),(reg));
1821 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1822 *(cd->mcodeptr++) = 0xf3;
1823 emit_rex(0,(dreg),0,(reg));
1824 *(cd->mcodeptr++) = 0x0f;
1825 *(cd->mcodeptr++) = 0x58;
1826 emit_reg((dreg),(reg));
1830 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1831 *(cd->mcodeptr++) = 0xf3;
1832 emit_rex(1,(dreg),0,(reg));
1833 *(cd->mcodeptr++) = 0x0f;
1834 *(cd->mcodeptr++) = 0x2a;
1835 emit_reg((dreg),(reg));
1839 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1840 *(cd->mcodeptr++) = 0xf3;
1841 emit_rex(0,(dreg),0,(reg));
1842 *(cd->mcodeptr++) = 0x0f;
1843 *(cd->mcodeptr++) = 0x2a;
1844 emit_reg((dreg),(reg));
1848 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1849 *(cd->mcodeptr++) = 0xf2;
1850 emit_rex(1,(dreg),0,(reg));
1851 *(cd->mcodeptr++) = 0x0f;
1852 *(cd->mcodeptr++) = 0x2a;
1853 emit_reg((dreg),(reg));
1857 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1858 *(cd->mcodeptr++) = 0xf2;
1859 emit_rex(0,(dreg),0,(reg));
1860 *(cd->mcodeptr++) = 0x0f;
1861 *(cd->mcodeptr++) = 0x2a;
1862 emit_reg((dreg),(reg));
1866 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1867 *(cd->mcodeptr++) = 0xf3;
1868 emit_rex(0,(dreg),0,(reg));
1869 *(cd->mcodeptr++) = 0x0f;
1870 *(cd->mcodeptr++) = 0x5a;
1871 emit_reg((dreg),(reg));
1875 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1876 *(cd->mcodeptr++) = 0xf2;
1877 emit_rex(0,(dreg),0,(reg));
1878 *(cd->mcodeptr++) = 0x0f;
1879 *(cd->mcodeptr++) = 0x5a;
1880 emit_reg((dreg),(reg));
1884 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1885 *(cd->mcodeptr++) = 0xf3;
1886 emit_rex(1,(dreg),0,(reg));
1887 *(cd->mcodeptr++) = 0x0f;
1888 *(cd->mcodeptr++) = 0x2c;
1889 emit_reg((dreg),(reg));
1893 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1894 *(cd->mcodeptr++) = 0xf3;
1895 emit_rex(0,(dreg),0,(reg));
1896 *(cd->mcodeptr++) = 0x0f;
1897 *(cd->mcodeptr++) = 0x2c;
1898 emit_reg((dreg),(reg));
1902 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1903 *(cd->mcodeptr++) = 0xf2;
1904 emit_rex(1,(dreg),0,(reg));
1905 *(cd->mcodeptr++) = 0x0f;
1906 *(cd->mcodeptr++) = 0x2c;
1907 emit_reg((dreg),(reg));
1911 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1912 *(cd->mcodeptr++) = 0xf2;
1913 emit_rex(0,(dreg),0,(reg));
1914 *(cd->mcodeptr++) = 0x0f;
1915 *(cd->mcodeptr++) = 0x2c;
1916 emit_reg((dreg),(reg));
1920 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1921 *(cd->mcodeptr++) = 0xf3;
1922 emit_rex(0,(dreg),0,(reg));
1923 *(cd->mcodeptr++) = 0x0f;
1924 *(cd->mcodeptr++) = 0x5e;
1925 emit_reg((dreg),(reg));
1929 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1930 *(cd->mcodeptr++) = 0xf2;
1931 emit_rex(0,(dreg),0,(reg));
1932 *(cd->mcodeptr++) = 0x0f;
1933 *(cd->mcodeptr++) = 0x5e;
1934 emit_reg((dreg),(reg));
1938 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1939 *(cd->mcodeptr++) = 0x66;
1940 emit_rex(1,(freg),0,(reg));
1941 *(cd->mcodeptr++) = 0x0f;
1942 *(cd->mcodeptr++) = 0x6e;
1943 emit_reg((freg),(reg));
1947 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1948 *(cd->mcodeptr++) = 0x66;
1949 emit_rex(1,(freg),0,(reg));
1950 *(cd->mcodeptr++) = 0x0f;
1951 *(cd->mcodeptr++) = 0x7e;
1952 emit_reg((freg),(reg));
1956 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1957 *(cd->mcodeptr++) = 0x66;
1958 emit_rex(0,(reg),0,(basereg));
1959 *(cd->mcodeptr++) = 0x0f;
1960 *(cd->mcodeptr++) = 0x7e;
1961 emit_membase(cd, (basereg),(disp),(reg));
1965 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1966 *(cd->mcodeptr++) = 0x66;
1967 emit_rex(0,(reg),(indexreg),(basereg));
1968 *(cd->mcodeptr++) = 0x0f;
1969 *(cd->mcodeptr++) = 0x7e;
1970 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1974 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1975 *(cd->mcodeptr++) = 0x66;
1976 emit_rex(1,(dreg),0,(basereg));
1977 *(cd->mcodeptr++) = 0x0f;
1978 *(cd->mcodeptr++) = 0x6e;
1979 emit_membase(cd, (basereg),(disp),(dreg));
1983 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1984 *(cd->mcodeptr++) = 0x66;
1985 emit_rex(0,(dreg),0,(basereg));
1986 *(cd->mcodeptr++) = 0x0f;
1987 *(cd->mcodeptr++) = 0x6e;
1988 emit_membase(cd, (basereg),(disp),(dreg));
1992 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
1993 *(cd->mcodeptr++) = 0x66;
1994 emit_rex(0,(dreg),(indexreg),(basereg));
1995 *(cd->mcodeptr++) = 0x0f;
1996 *(cd->mcodeptr++) = 0x6e;
1997 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2001 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2002 *(cd->mcodeptr++) = 0xf3;
2003 emit_rex(0,(dreg),0,(reg));
2004 *(cd->mcodeptr++) = 0x0f;
2005 *(cd->mcodeptr++) = 0x7e;
2006 emit_reg((dreg),(reg));
2010 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2011 *(cd->mcodeptr++) = 0x66;
2012 emit_rex(0,(reg),0,(basereg));
2013 *(cd->mcodeptr++) = 0x0f;
2014 *(cd->mcodeptr++) = 0xd6;
2015 emit_membase(cd, (basereg),(disp),(reg));
2019 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2020 *(cd->mcodeptr++) = 0xf3;
2021 emit_rex(0,(dreg),0,(basereg));
2022 *(cd->mcodeptr++) = 0x0f;
2023 *(cd->mcodeptr++) = 0x7e;
2024 emit_membase(cd, (basereg),(disp),(dreg));
2028 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2029 *(cd->mcodeptr++) = 0xf3;
2030 emit_rex(0,(reg),0,(dreg));
2031 *(cd->mcodeptr++) = 0x0f;
2032 *(cd->mcodeptr++) = 0x10;
2033 emit_reg((reg),(dreg));
2037 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2038 *(cd->mcodeptr++) = 0xf2;
2039 emit_rex(0,(reg),0,(dreg));
2040 *(cd->mcodeptr++) = 0x0f;
2041 *(cd->mcodeptr++) = 0x10;
2042 emit_reg((reg),(dreg));
2046 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2047 *(cd->mcodeptr++) = 0xf3;
2048 emit_rex(0,(reg),0,(basereg));
2049 *(cd->mcodeptr++) = 0x0f;
2050 *(cd->mcodeptr++) = 0x11;
2051 emit_membase(cd, (basereg),(disp),(reg));
2055 /* Always emit a REX byte, because the instruction size can be smaller when */
2056 /* all register indexes are smaller than 7. */
2057 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2058 *(cd->mcodeptr++) = 0xf3;
2059 emit_byte_rex((reg),0,(basereg));
2060 *(cd->mcodeptr++) = 0x0f;
2061 *(cd->mcodeptr++) = 0x11;
2062 emit_membase32(cd, (basereg),(disp),(reg));
2066 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2067 *(cd->mcodeptr++) = 0xf2;
2068 emit_rex(0,(reg),0,(basereg));
2069 *(cd->mcodeptr++) = 0x0f;
2070 *(cd->mcodeptr++) = 0x11;
2071 emit_membase(cd, (basereg),(disp),(reg));
2075 /* Always emit a REX byte, because the instruction size can be smaller when */
2076 /* all register indexes are smaller than 7. */
2077 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2078 *(cd->mcodeptr++) = 0xf2;
2079 emit_byte_rex((reg),0,(basereg));
2080 *(cd->mcodeptr++) = 0x0f;
2081 *(cd->mcodeptr++) = 0x11;
2082 emit_membase32(cd, (basereg),(disp),(reg));
2086 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2087 *(cd->mcodeptr++) = 0xf3;
2088 emit_rex(0,(dreg),0,(basereg));
2089 *(cd->mcodeptr++) = 0x0f;
2090 *(cd->mcodeptr++) = 0x10;
2091 emit_membase(cd, (basereg),(disp),(dreg));
2095 /* Always emit a REX byte, because the instruction size can be smaller when */
2096 /* all register indexes are smaller than 7. */
2097 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2098 *(cd->mcodeptr++) = 0xf3;
2099 emit_byte_rex((dreg),0,(basereg));
2100 *(cd->mcodeptr++) = 0x0f;
2101 *(cd->mcodeptr++) = 0x10;
2102 emit_membase32(cd, (basereg),(disp),(dreg));
2106 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2108 emit_rex(0,(dreg),0,(basereg));
2109 *(cd->mcodeptr++) = 0x0f;
2110 *(cd->mcodeptr++) = 0x12;
2111 emit_membase(cd, (basereg),(disp),(dreg));
2115 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2117 emit_rex(0,(reg),0,(basereg));
2118 *(cd->mcodeptr++) = 0x0f;
2119 *(cd->mcodeptr++) = 0x13;
2120 emit_membase(cd, (basereg),(disp),(reg));
2124 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2125 *(cd->mcodeptr++) = 0xf2;
2126 emit_rex(0,(dreg),0,(basereg));
2127 *(cd->mcodeptr++) = 0x0f;
2128 *(cd->mcodeptr++) = 0x10;
2129 emit_membase(cd, (basereg),(disp),(dreg));
2133 /* Always emit a REX byte, because the instruction size can be smaller when */
2134 /* all register indexes are smaller than 7. */
2135 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2136 *(cd->mcodeptr++) = 0xf2;
2137 emit_byte_rex((dreg),0,(basereg));
2138 *(cd->mcodeptr++) = 0x0f;
2139 *(cd->mcodeptr++) = 0x10;
2140 emit_membase32(cd, (basereg),(disp),(dreg));
2144 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2146 *(cd->mcodeptr++) = 0x66;
2147 emit_rex(0,(dreg),0,(basereg));
2148 *(cd->mcodeptr++) = 0x0f;
2149 *(cd->mcodeptr++) = 0x12;
2150 emit_membase(cd, (basereg),(disp),(dreg));
2154 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2156 *(cd->mcodeptr++) = 0x66;
2157 emit_rex(0,(reg),0,(basereg));
2158 *(cd->mcodeptr++) = 0x0f;
2159 *(cd->mcodeptr++) = 0x13;
2160 emit_membase(cd, (basereg),(disp),(reg));
2164 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2165 *(cd->mcodeptr++) = 0xf3;
2166 emit_rex(0,(reg),(indexreg),(basereg));
2167 *(cd->mcodeptr++) = 0x0f;
2168 *(cd->mcodeptr++) = 0x11;
2169 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2173 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2174 *(cd->mcodeptr++) = 0xf2;
2175 emit_rex(0,(reg),(indexreg),(basereg));
2176 *(cd->mcodeptr++) = 0x0f;
2177 *(cd->mcodeptr++) = 0x11;
2178 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2182 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2183 *(cd->mcodeptr++) = 0xf3;
2184 emit_rex(0,(dreg),(indexreg),(basereg));
2185 *(cd->mcodeptr++) = 0x0f;
2186 *(cd->mcodeptr++) = 0x10;
2187 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2191 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2192 *(cd->mcodeptr++) = 0xf2;
2193 emit_rex(0,(dreg),(indexreg),(basereg));
2194 *(cd->mcodeptr++) = 0x0f;
2195 *(cd->mcodeptr++) = 0x10;
2196 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2200 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2201 *(cd->mcodeptr++) = 0xf3;
2202 emit_rex(0,(dreg),0,(reg));
2203 *(cd->mcodeptr++) = 0x0f;
2204 *(cd->mcodeptr++) = 0x59;
2205 emit_reg((dreg),(reg));
2209 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2210 *(cd->mcodeptr++) = 0xf2;
2211 emit_rex(0,(dreg),0,(reg));
2212 *(cd->mcodeptr++) = 0x0f;
2213 *(cd->mcodeptr++) = 0x59;
2214 emit_reg((dreg),(reg));
2218 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2219 *(cd->mcodeptr++) = 0xf3;
2220 emit_rex(0,(dreg),0,(reg));
2221 *(cd->mcodeptr++) = 0x0f;
2222 *(cd->mcodeptr++) = 0x5c;
2223 emit_reg((dreg),(reg));
2227 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2228 *(cd->mcodeptr++) = 0xf2;
2229 emit_rex(0,(dreg),0,(reg));
2230 *(cd->mcodeptr++) = 0x0f;
2231 *(cd->mcodeptr++) = 0x5c;
2232 emit_reg((dreg),(reg));
2236 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2237 emit_rex(0,(dreg),0,(reg));
2238 *(cd->mcodeptr++) = 0x0f;
2239 *(cd->mcodeptr++) = 0x2e;
2240 emit_reg((dreg),(reg));
2244 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2245 *(cd->mcodeptr++) = 0x66;
2246 emit_rex(0,(dreg),0,(reg));
2247 *(cd->mcodeptr++) = 0x0f;
2248 *(cd->mcodeptr++) = 0x2e;
2249 emit_reg((dreg),(reg));
2253 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2254 emit_rex(0,(dreg),0,(reg));
2255 *(cd->mcodeptr++) = 0x0f;
2256 *(cd->mcodeptr++) = 0x57;
2257 emit_reg((dreg),(reg));
2261 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2262 emit_rex(0,(dreg),0,(basereg));
2263 *(cd->mcodeptr++) = 0x0f;
2264 *(cd->mcodeptr++) = 0x57;
2265 emit_membase(cd, (basereg),(disp),(dreg));
2269 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2270 *(cd->mcodeptr++) = 0x66;
2271 emit_rex(0,(dreg),0,(reg));
2272 *(cd->mcodeptr++) = 0x0f;
2273 *(cd->mcodeptr++) = 0x57;
2274 emit_reg((dreg),(reg));
2278 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2279 *(cd->mcodeptr++) = 0x66;
2280 emit_rex(0,(dreg),0,(basereg));
2281 *(cd->mcodeptr++) = 0x0f;
2282 *(cd->mcodeptr++) = 0x57;
2283 emit_membase(cd, (basereg),(disp),(dreg));
2287 /* system instructions ********************************************************/
2289 void emit_rdtsc(codegendata *cd)
2291 *(cd->mcodeptr++) = 0x0f;
2292 *(cd->mcodeptr++) = 0x31;
2297 * These are local overrides for various environment variables in Emacs.
2298 * Please do not remove this and leave it at the end of the file, where
2299 * Emacs will automagically detect them.
2300 * ---------------------------------------------------------------------
2303 * indent-tabs-mode: t