1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
35 #include "vm/jit/x86_64/codegen.h"
36 #include "vm/jit/x86_64/emit.h"
38 #include "mm/memory.h"
40 #include "threads/lock-common.h"
42 #include "vm/builtin.h"
43 #include "vm/exceptions.h"
45 #include "vm/jit/abi.h"
46 #include "vm/jit/abi-asm.h"
47 #include "vm/jit/asmpart.h"
48 #include "vm/jit/codegen-common.h"
49 #include "vm/jit/emit-common.h"
50 #include "vm/jit/jit.h"
51 #include "vm/jit/patcher-common.h"
52 #include "vm/jit/replace.h"
54 #include "vmcore/options.h"
57 /* emit_load *******************************************************************
59 Emits a possible load of an operand.
61 *******************************************************************************/
63 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
69 /* get required compiler data */
73 if (IS_INMEMORY(src->flags)) {
76 disp = src->vv.regoff;
80 M_ILD(tempreg, REG_SP, disp);
84 M_LLD(tempreg, REG_SP, disp);
87 M_FLD(tempreg, REG_SP, disp);
90 M_DLD(tempreg, REG_SP, disp);
93 vm_abort("emit_load: unknown type %d", src->type);
105 /* emit_store ******************************************************************
107 This function generates the code to store the result of an
108 operation back into a spilled pseudo-variable. If the
109 pseudo-variable has not been spilled in the first place, this
110 function will generate nothing.
112 *******************************************************************************/
114 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
123 /* get required compiler data */
128 /* do we have to generate a conditional move? */
130 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
131 /* the passed register d is actually the source register */
135 /* Only pass the opcode to codegen_reg_of_var to get the real
136 destination register. */
138 opcode = iptr->opc & ICMD_OPCODE_MASK;
140 /* get the real destination register */
142 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
144 /* and emit the conditional move */
146 emit_cmovxx(cd, iptr, s, d);
150 if (IS_INMEMORY(dst->flags)) {
153 disp = dst->vv.regoff;
159 M_LST(d, REG_SP, disp);
162 M_FST(d, REG_SP, disp);
165 M_DST(d, REG_SP, disp);
168 vm_abort("emit_store: unknown type %d", dst->type);
174 /* emit_copy *******************************************************************
176 Generates a register/memory to register/memory copy.
178 *******************************************************************************/
180 void emit_copy(jitdata *jd, instruction *iptr)
187 /* get required compiler data */
191 /* get source and destination variables */
193 src = VAROP(iptr->s1);
194 dst = VAROP(iptr->dst);
196 if ((src->vv.regoff != dst->vv.regoff) ||
197 ((src->flags ^ dst->flags) & INMEMORY)) {
199 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
200 /* emit nothing, as the value won't be used anyway */
204 /* If one of the variables resides in memory, we can eliminate
205 the register move from/to the temporary register with the
206 order of getting the destination register and the load. */
208 if (IS_INMEMORY(src->flags)) {
209 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
210 s1 = emit_load(jd, iptr, src, d);
213 s1 = emit_load(jd, iptr, src, REG_IFTMP);
214 d = codegen_reg_of_var(iptr->opc, dst, s1);
229 vm_abort("emit_copy: unknown type %d", src->type);
233 emit_store(jd, iptr, dst, d);
238 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
241 switch (iptr->flags.fields.condition) {
265 /* emit_branch *****************************************************************
267 Emits the code for conditional and unconditional branchs.
269 *******************************************************************************/
271 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
275 /* NOTE: A displacement overflow cannot happen. */
277 /* check which branch to generate */
279 if (condition == BRANCH_UNCONDITIONAL) {
281 /* calculate the different displacements */
283 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
285 M_JMP_IMM(branchdisp);
288 /* calculate the different displacements */
290 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
324 vm_abort("emit_branch: unknown condition %d", condition);
330 /* emit_arithmetic_check *******************************************************
332 Emit an ArithmeticException check.
334 *******************************************************************************/
336 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
338 if (INSTRUCTION_MUST_CHECK(iptr)) {
341 M_ALD_MEM(reg, EXCEPTION_HARDWARE_ARITHMETIC);
346 /* emit_arrayindexoutofbounds_check ********************************************
348 Emit a ArrayIndexOutOfBoundsException check.
350 *******************************************************************************/
352 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
354 if (INSTRUCTION_MUST_CHECK(iptr)) {
355 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
356 M_ICMP(REG_ITMP3, s2);
358 M_ALD_MEM(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
363 /* emit_arraystore_check *******************************************************
365 Emit an ArrayStoreException check.
367 *******************************************************************************/
369 void emit_arraystore_check(codegendata *cd, instruction *iptr)
371 if (INSTRUCTION_MUST_CHECK(iptr)) {
374 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_ARRAYSTORE);
379 /* emit_classcast_check ********************************************************
381 Emit a ClassCastException check.
383 *******************************************************************************/
385 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
387 if (INSTRUCTION_MUST_CHECK(iptr)) {
399 vm_abort("emit_classcast_check: unknown condition %d", condition);
401 M_ALD_MEM(s1, EXCEPTION_HARDWARE_CLASSCAST);
406 /* emit_nullpointer_check ******************************************************
408 Emit a NullPointerException check.
410 *******************************************************************************/
412 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
414 if (INSTRUCTION_MUST_CHECK(iptr)) {
417 M_ALD_MEM(reg, EXCEPTION_HARDWARE_NULLPOINTER);
422 /* emit_exception_check ********************************************************
424 Emit an Exception check.
426 *******************************************************************************/
428 void emit_exception_check(codegendata *cd, instruction *iptr)
430 if (INSTRUCTION_MUST_CHECK(iptr)) {
433 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_EXCEPTION);
438 /* emit_trap_compiler **********************************************************
440 Emit a trap instruction which calls the JIT compiler.
442 *******************************************************************************/
444 void emit_trap_compiler(codegendata *cd)
446 M_ALD_MEM(REG_METHODPTR, EXCEPTION_HARDWARE_COMPILER);
450 /* emit_trap *******************************************************************
452 Emit a trap instruction and return the original machine code.
454 *******************************************************************************/
456 uint32_t emit_trap(codegendata *cd)
460 /* Get machine code which is patched back in later. The trap is 2
463 mcode = *((uint16_t *) cd->mcodeptr);
465 /* XXX This needs to be change to INT3 when the debugging problems
466 with gdb are resolved. */
474 /* emit_verbosecall_enter ******************************************************
476 Generates the code for the call trace.
478 *******************************************************************************/
481 void emit_verbosecall_enter(jitdata *jd)
489 /* get required compiler data */
497 /* mark trace code */
501 /* additional +1 is for 16-byte stack alignment */
503 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
505 /* save argument registers */
507 for (i = 0; i < INT_ARG_CNT; i++)
508 M_LST(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
510 for (i = 0; i < FLT_ARG_CNT; i++)
511 M_DST(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
513 /* save temporary registers for leaf methods */
515 if (jd->isleafmethod) {
516 for (i = 0; i < INT_TMP_CNT; i++)
517 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
519 for (i = 0; i < FLT_TMP_CNT; i++)
520 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
523 /* show integer hex code for float arguments */
525 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
526 /* If the paramtype is a float, we have to right shift all
527 following integer registers. */
529 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
530 for (k = INT_ARG_CNT - 2; k >= i; k--)
531 M_MOV(abi_registers_integer_argument[k],
532 abi_registers_integer_argument[k + 1]);
534 emit_movd_freg_reg(cd, abi_registers_float_argument[j],
535 abi_registers_integer_argument[i]);
540 M_MOV_IMM(m, REG_ITMP2);
541 M_AST(REG_ITMP2, REG_SP, 0 * 8);
542 M_MOV_IMM(builtin_verbosecall_enter, REG_ITMP1);
545 /* restore argument registers */
547 for (i = 0; i < INT_ARG_CNT; i++)
548 M_LLD(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
550 for (i = 0; i < FLT_ARG_CNT; i++)
551 M_DLD(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
553 /* restore temporary registers for leaf methods */
555 if (jd->isleafmethod) {
556 for (i = 0; i < INT_TMP_CNT; i++)
557 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
559 for (i = 0; i < FLT_TMP_CNT; i++)
560 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
563 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
565 /* mark trace code */
569 #endif /* !defined(NDEBUG) */
572 /* emit_verbosecall_exit *******************************************************
574 Generates the code for the call trace.
576 *******************************************************************************/
579 void emit_verbosecall_exit(jitdata *jd)
585 /* get required compiler data */
591 /* mark trace code */
595 M_ASUB_IMM(2 * 8, REG_SP);
597 M_LST(REG_RESULT, REG_SP, 0 * 8);
598 M_DST(REG_FRESULT, REG_SP, 1 * 8);
600 M_INTMOVE(REG_RESULT, REG_A0);
601 M_FLTMOVE(REG_FRESULT, REG_FA0);
602 M_FLTMOVE(REG_FRESULT, REG_FA1);
603 M_MOV_IMM(m, REG_A1);
605 M_MOV_IMM(builtin_verbosecall_exit, REG_ITMP1);
608 M_LLD(REG_RESULT, REG_SP, 0 * 8);
609 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
611 M_AADD_IMM(2 * 8, REG_SP);
613 /* mark trace code */
617 #endif /* !defined(NDEBUG) */
620 /* code generation functions **************************************************/
622 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
624 if ((basereg == REG_SP) || (basereg == R12)) {
626 emit_address_byte(0, dreg, REG_SP);
627 emit_address_byte(0, REG_SP, REG_SP);
629 } else if (IS_IMM8(disp)) {
630 emit_address_byte(1, dreg, REG_SP);
631 emit_address_byte(0, REG_SP, REG_SP);
635 emit_address_byte(2, dreg, REG_SP);
636 emit_address_byte(0, REG_SP, REG_SP);
640 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
641 emit_address_byte(0,(dreg),(basereg));
643 } else if ((basereg) == RIP) {
644 emit_address_byte(0, dreg, RBP);
649 emit_address_byte(1, dreg, basereg);
653 emit_address_byte(2, dreg, basereg);
660 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
662 if ((basereg == REG_SP) || (basereg == R12)) {
663 emit_address_byte(2, dreg, REG_SP);
664 emit_address_byte(0, REG_SP, REG_SP);
668 emit_address_byte(2, dreg, basereg);
674 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
677 emit_address_byte(0, reg, 4);
678 emit_address_byte(scale, indexreg, 5);
681 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
682 emit_address_byte(0, reg, 4);
683 emit_address_byte(scale, indexreg, basereg);
685 else if (IS_IMM8(disp)) {
686 emit_address_byte(1, reg, 4);
687 emit_address_byte(scale, indexreg, basereg);
691 emit_address_byte(2, reg, 4);
692 emit_address_byte(scale, indexreg, basereg);
698 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
701 varinfo *v_s1,*v_s2,*v_dst;
704 /* get required compiler data */
708 v_s1 = VAROP(iptr->s1);
709 v_s2 = VAROP(iptr->sx.s23.s2);
710 v_dst = VAROP(iptr->dst);
712 s1 = v_s1->vv.regoff;
713 s2 = v_s2->vv.regoff;
714 d = v_dst->vv.regoff;
716 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
718 if (IS_INMEMORY(v_dst->flags)) {
719 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
721 M_ILD(RCX, REG_SP, s2);
722 emit_shiftl_membase(cd, shift_op, REG_SP, d);
725 M_ILD(RCX, REG_SP, s2);
726 M_ILD(REG_ITMP2, REG_SP, s1);
727 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
728 M_IST(REG_ITMP2, REG_SP, d);
731 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
732 /* s1 may be equal to RCX */
735 M_ILD(REG_ITMP1, REG_SP, s2);
736 M_IST(s1, REG_SP, d);
737 M_INTMOVE(REG_ITMP1, RCX);
740 M_IST(s1, REG_SP, d);
741 M_ILD(RCX, REG_SP, s2);
745 M_ILD(RCX, REG_SP, s2);
746 M_IST(s1, REG_SP, d);
749 emit_shiftl_membase(cd, shift_op, REG_SP, d);
751 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
754 emit_shiftl_membase(cd, shift_op, REG_SP, d);
758 M_ILD(REG_ITMP2, REG_SP, s1);
759 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
760 M_IST(REG_ITMP2, REG_SP, d);
764 /* s1 may be equal to RCX */
765 M_IST(s1, REG_SP, d);
767 emit_shiftl_membase(cd, shift_op, REG_SP, d);
770 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
778 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
779 M_ILD(RCX, REG_SP, s2);
780 M_ILD(d, REG_SP, s1);
781 emit_shiftl_reg(cd, shift_op, d);
783 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
784 /* s1 may be equal to RCX */
786 M_ILD(RCX, REG_SP, s2);
787 emit_shiftl_reg(cd, shift_op, d);
789 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
791 M_ILD(d, REG_SP, s1);
792 emit_shiftl_reg(cd, shift_op, d);
795 /* s1 may be equal to RCX */
798 /* d cannot be used to backup s1 since this would
800 M_INTMOVE(s1, REG_ITMP3);
802 M_INTMOVE(REG_ITMP3, d);
810 /* d may be equal to s2 */
814 emit_shiftl_reg(cd, shift_op, d);
818 M_INTMOVE(REG_ITMP3, RCX);
820 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
825 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
828 varinfo *v_s1,*v_s2,*v_dst;
831 /* get required compiler data */
835 v_s1 = VAROP(iptr->s1);
836 v_s2 = VAROP(iptr->sx.s23.s2);
837 v_dst = VAROP(iptr->dst);
839 s1 = v_s1->vv.regoff;
840 s2 = v_s2->vv.regoff;
841 d = v_dst->vv.regoff;
843 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
845 if (IS_INMEMORY(v_dst->flags)) {
846 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
848 M_ILD(RCX, REG_SP, s2);
849 emit_shift_membase(cd, shift_op, REG_SP, d);
852 M_ILD(RCX, REG_SP, s2);
853 M_LLD(REG_ITMP2, REG_SP, s1);
854 emit_shift_reg(cd, shift_op, REG_ITMP2);
855 M_LST(REG_ITMP2, REG_SP, d);
858 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
859 /* s1 may be equal to RCX */
862 M_ILD(REG_ITMP1, REG_SP, s2);
863 M_LST(s1, REG_SP, d);
864 M_INTMOVE(REG_ITMP1, RCX);
867 M_LST(s1, REG_SP, d);
868 M_ILD(RCX, REG_SP, s2);
872 M_ILD(RCX, REG_SP, s2);
873 M_LST(s1, REG_SP, d);
876 emit_shift_membase(cd, shift_op, REG_SP, d);
878 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
881 emit_shift_membase(cd, shift_op, REG_SP, d);
885 M_LLD(REG_ITMP2, REG_SP, s1);
886 emit_shift_reg(cd, shift_op, REG_ITMP2);
887 M_LST(REG_ITMP2, REG_SP, d);
891 /* s1 may be equal to RCX */
892 M_LST(s1, REG_SP, d);
894 emit_shift_membase(cd, shift_op, REG_SP, d);
897 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
905 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
906 M_ILD(RCX, REG_SP, s2);
907 M_LLD(d, REG_SP, s1);
908 emit_shift_reg(cd, shift_op, d);
910 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
911 /* s1 may be equal to RCX */
913 M_ILD(RCX, REG_SP, s2);
914 emit_shift_reg(cd, shift_op, d);
916 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
918 M_LLD(d, REG_SP, s1);
919 emit_shift_reg(cd, shift_op, d);
922 /* s1 may be equal to RCX */
925 /* d cannot be used to backup s1 since this would
927 M_INTMOVE(s1, REG_ITMP3);
929 M_INTMOVE(REG_ITMP3, d);
937 /* d may be equal to s2 */
941 emit_shift_reg(cd, shift_op, d);
945 M_INTMOVE(REG_ITMP3, RCX);
947 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
952 /* low-level code emitter functions *******************************************/
954 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
956 emit_rex(1,(reg),0,(dreg));
957 *(cd->mcodeptr++) = 0x89;
958 emit_reg((reg),(dreg));
962 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
964 emit_rex(1,0,0,(reg));
965 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
970 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
972 emit_rex(0,(reg),0,(dreg));
973 *(cd->mcodeptr++) = 0x89;
974 emit_reg((reg),(dreg));
978 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
979 emit_rex(0,0,0,(reg));
980 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
985 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
986 emit_rex(1,(reg),0,(basereg));
987 *(cd->mcodeptr++) = 0x8b;
988 emit_membase(cd, (basereg),(disp),(reg));
993 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
994 * constant membase immediate length of 32bit
996 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
997 emit_rex(1,(reg),0,(basereg));
998 *(cd->mcodeptr++) = 0x8b;
999 emit_membase32(cd, (basereg),(disp),(reg));
1003 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1005 emit_rex(0,(reg),0,(basereg));
1006 *(cd->mcodeptr++) = 0x8b;
1007 emit_membase(cd, (basereg),(disp),(reg));
1011 /* ATTENTION: Always emit a REX byte, because the instruction size can
1012 be smaller when all register indexes are smaller than 7. */
1013 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1015 emit_byte_rex((reg),0,(basereg));
1016 *(cd->mcodeptr++) = 0x8b;
1017 emit_membase32(cd, (basereg),(disp),(reg));
1021 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1022 emit_rex(1,(reg),0,(basereg));
1023 *(cd->mcodeptr++) = 0x89;
1024 emit_membase(cd, (basereg),(disp),(reg));
1028 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1029 emit_rex(1,(reg),0,(basereg));
1030 *(cd->mcodeptr++) = 0x89;
1031 emit_membase32(cd, (basereg),(disp),(reg));
1035 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1036 emit_rex(0,(reg),0,(basereg));
1037 *(cd->mcodeptr++) = 0x89;
1038 emit_membase(cd, (basereg),(disp),(reg));
1042 /* Always emit a REX byte, because the instruction size can be smaller when */
1043 /* all register indexes are smaller than 7. */
1044 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1045 emit_byte_rex((reg),0,(basereg));
1046 *(cd->mcodeptr++) = 0x89;
1047 emit_membase32(cd, (basereg),(disp),(reg));
1051 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1052 emit_rex(1,(reg),(indexreg),(basereg));
1053 *(cd->mcodeptr++) = 0x8b;
1054 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1058 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1059 emit_rex(0,(reg),(indexreg),(basereg));
1060 *(cd->mcodeptr++) = 0x8b;
1061 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1065 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1066 emit_rex(1,(reg),(indexreg),(basereg));
1067 *(cd->mcodeptr++) = 0x89;
1068 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1072 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1073 emit_rex(0,(reg),(indexreg),(basereg));
1074 *(cd->mcodeptr++) = 0x89;
1075 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1079 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1080 *(cd->mcodeptr++) = 0x66;
1081 emit_rex(0,(reg),(indexreg),(basereg));
1082 *(cd->mcodeptr++) = 0x89;
1083 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1087 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1088 emit_byte_rex((reg),(indexreg),(basereg));
1089 *(cd->mcodeptr++) = 0x88;
1090 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1094 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1095 emit_rex(1,0,0,(basereg));
1096 *(cd->mcodeptr++) = 0xc7;
1097 emit_membase(cd, (basereg),(disp),0);
1102 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1103 emit_rex(1,0,0,(basereg));
1104 *(cd->mcodeptr++) = 0xc7;
1105 emit_membase32(cd, (basereg),(disp),0);
1110 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1111 emit_rex(0,0,0,(basereg));
1112 *(cd->mcodeptr++) = 0xc7;
1113 emit_membase(cd, (basereg),(disp),0);
1118 /* Always emit a REX byte, because the instruction size can be smaller when */
1119 /* all register indexes are smaller than 7. */
1120 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1121 emit_byte_rex(0,0,(basereg));
1122 *(cd->mcodeptr++) = 0xc7;
1123 emit_membase32(cd, (basereg),(disp),0);
1128 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1130 emit_rex(1,(dreg),0,(reg));
1131 *(cd->mcodeptr++) = 0x0f;
1132 *(cd->mcodeptr++) = 0xbe;
1133 /* XXX: why do reg and dreg have to be exchanged */
1134 emit_reg((dreg),(reg));
1138 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1140 emit_rex(1,(dreg),0,(reg));
1141 *(cd->mcodeptr++) = 0x0f;
1142 *(cd->mcodeptr++) = 0xbf;
1143 /* XXX: why do reg and dreg have to be exchanged */
1144 emit_reg((dreg),(reg));
1148 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1150 emit_rex(1,(dreg),0,(reg));
1151 *(cd->mcodeptr++) = 0x63;
1152 /* XXX: why do reg and dreg have to be exchanged */
1153 emit_reg((dreg),(reg));
1157 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1159 emit_rex(1,(dreg),0,(reg));
1160 *(cd->mcodeptr++) = 0x0f;
1161 *(cd->mcodeptr++) = 0xb7;
1162 /* XXX: why do reg and dreg have to be exchanged */
1163 emit_reg((dreg),(reg));
1167 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1168 emit_rex(1,(reg),(indexreg),(basereg));
1169 *(cd->mcodeptr++) = 0x0f;
1170 *(cd->mcodeptr++) = 0xbf;
1171 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1175 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1176 emit_rex(1,(reg),(indexreg),(basereg));
1177 *(cd->mcodeptr++) = 0x0f;
1178 *(cd->mcodeptr++) = 0xbe;
1179 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1183 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1184 emit_rex(1,(reg),(indexreg),(basereg));
1185 *(cd->mcodeptr++) = 0x0f;
1186 *(cd->mcodeptr++) = 0xb7;
1187 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1191 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1193 emit_rex(1,0,(indexreg),(basereg));
1194 *(cd->mcodeptr++) = 0xc7;
1195 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1200 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1202 emit_rex(0,0,(indexreg),(basereg));
1203 *(cd->mcodeptr++) = 0xc7;
1204 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1209 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1211 *(cd->mcodeptr++) = 0x66;
1212 emit_rex(0,0,(indexreg),(basereg));
1213 *(cd->mcodeptr++) = 0xc7;
1214 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1219 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1221 emit_rex(0,0,(indexreg),(basereg));
1222 *(cd->mcodeptr++) = 0xc6;
1223 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1228 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1230 emit_rex(1, dreg, 0, 0);
1231 *(cd->mcodeptr++) = 0x8b;
1232 emit_address_byte(0, dreg, 4);
1240 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1242 emit_rex(1,(reg),0,(dreg));
1243 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1244 emit_reg((reg),(dreg));
1248 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1250 emit_rex(0,(reg),0,(dreg));
1251 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1252 emit_reg((reg),(dreg));
1256 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1258 emit_rex(1,(reg),0,(basereg));
1259 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1260 emit_membase(cd, (basereg),(disp),(reg));
1264 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1266 emit_rex(0,(reg),0,(basereg));
1267 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1268 emit_membase(cd, (basereg),(disp),(reg));
1272 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1274 emit_rex(1,(reg),0,(basereg));
1275 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1276 emit_membase(cd, (basereg),(disp),(reg));
1280 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1282 emit_rex(0,(reg),0,(basereg));
1283 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1284 emit_membase(cd, (basereg),(disp),(reg));
1288 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1290 emit_rex(1,0,0,(dreg));
1291 *(cd->mcodeptr++) = 0x83;
1292 emit_reg((opc),(dreg));
1295 emit_rex(1,0,0,(dreg));
1296 *(cd->mcodeptr++) = 0x81;
1297 emit_reg((opc),(dreg));
1303 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1305 emit_rex(1,0,0,(dreg));
1306 *(cd->mcodeptr++) = 0x81;
1307 emit_reg((opc),(dreg));
1312 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1314 emit_rex(0,0,0,(dreg));
1315 *(cd->mcodeptr++) = 0x81;
1316 emit_reg((opc),(dreg));
1321 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1323 emit_rex(0,0,0,(dreg));
1324 *(cd->mcodeptr++) = 0x83;
1325 emit_reg((opc),(dreg));
1328 emit_rex(0,0,0,(dreg));
1329 *(cd->mcodeptr++) = 0x81;
1330 emit_reg((opc),(dreg));
1336 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1338 emit_rex(1,(basereg),0,0);
1339 *(cd->mcodeptr++) = 0x83;
1340 emit_membase(cd, (basereg),(disp),(opc));
1343 emit_rex(1,(basereg),0,0);
1344 *(cd->mcodeptr++) = 0x81;
1345 emit_membase(cd, (basereg),(disp),(opc));
1351 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1353 emit_rex(0,(basereg),0,0);
1354 *(cd->mcodeptr++) = 0x83;
1355 emit_membase(cd, (basereg),(disp),(opc));
1358 emit_rex(0,(basereg),0,0);
1359 *(cd->mcodeptr++) = 0x81;
1360 emit_membase(cd, (basereg),(disp),(opc));
1366 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1367 emit_rex(1,(reg),0,(dreg));
1368 *(cd->mcodeptr++) = 0x85;
1369 emit_reg((reg),(dreg));
1373 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1374 emit_rex(0,(reg),0,(dreg));
1375 *(cd->mcodeptr++) = 0x85;
1376 emit_reg((reg),(dreg));
1380 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1381 *(cd->mcodeptr++) = 0xf7;
1387 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1388 *(cd->mcodeptr++) = 0x66;
1389 *(cd->mcodeptr++) = 0xf7;
1395 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1396 *(cd->mcodeptr++) = 0xf6;
1402 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1403 emit_rex(1,(reg),0,(basereg));
1404 *(cd->mcodeptr++) = 0x8d;
1405 emit_membase(cd, (basereg),(disp),(reg));
1409 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1410 emit_rex(0,(reg),0,(basereg));
1411 *(cd->mcodeptr++) = 0x8d;
1412 emit_membase(cd, (basereg),(disp),(reg));
1417 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1419 emit_rex(0,0,0,(basereg));
1420 *(cd->mcodeptr++) = 0xff;
1421 emit_membase(cd, (basereg),(disp),0);
1426 void emit_cltd(codegendata *cd) {
1427 *(cd->mcodeptr++) = 0x99;
1431 void emit_cqto(codegendata *cd) {
1433 *(cd->mcodeptr++) = 0x99;
1438 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1439 emit_rex(1,(dreg),0,(reg));
1440 *(cd->mcodeptr++) = 0x0f;
1441 *(cd->mcodeptr++) = 0xaf;
1442 emit_reg((dreg),(reg));
1446 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1447 emit_rex(0,(dreg),0,(reg));
1448 *(cd->mcodeptr++) = 0x0f;
1449 *(cd->mcodeptr++) = 0xaf;
1450 emit_reg((dreg),(reg));
1454 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1455 emit_rex(1,(dreg),0,(basereg));
1456 *(cd->mcodeptr++) = 0x0f;
1457 *(cd->mcodeptr++) = 0xaf;
1458 emit_membase(cd, (basereg),(disp),(dreg));
1462 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1463 emit_rex(0,(dreg),0,(basereg));
1464 *(cd->mcodeptr++) = 0x0f;
1465 *(cd->mcodeptr++) = 0xaf;
1466 emit_membase(cd, (basereg),(disp),(dreg));
1470 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1471 if (IS_IMM8((imm))) {
1472 emit_rex(1,0,0,(dreg));
1473 *(cd->mcodeptr++) = 0x6b;
1477 emit_rex(1,0,0,(dreg));
1478 *(cd->mcodeptr++) = 0x69;
1485 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1486 if (IS_IMM8((imm))) {
1487 emit_rex(1,(dreg),0,(reg));
1488 *(cd->mcodeptr++) = 0x6b;
1489 emit_reg((dreg),(reg));
1492 emit_rex(1,(dreg),0,(reg));
1493 *(cd->mcodeptr++) = 0x69;
1494 emit_reg((dreg),(reg));
1500 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1501 if (IS_IMM8((imm))) {
1502 emit_rex(0,(dreg),0,(reg));
1503 *(cd->mcodeptr++) = 0x6b;
1504 emit_reg((dreg),(reg));
1507 emit_rex(0,(dreg),0,(reg));
1508 *(cd->mcodeptr++) = 0x69;
1509 emit_reg((dreg),(reg));
1515 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1516 if (IS_IMM8((imm))) {
1517 emit_rex(1,(dreg),0,(basereg));
1518 *(cd->mcodeptr++) = 0x6b;
1519 emit_membase(cd, (basereg),(disp),(dreg));
1522 emit_rex(1,(dreg),0,(basereg));
1523 *(cd->mcodeptr++) = 0x69;
1524 emit_membase(cd, (basereg),(disp),(dreg));
1530 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1531 if (IS_IMM8((imm))) {
1532 emit_rex(0,(dreg),0,(basereg));
1533 *(cd->mcodeptr++) = 0x6b;
1534 emit_membase(cd, (basereg),(disp),(dreg));
1537 emit_rex(0,(dreg),0,(basereg));
1538 *(cd->mcodeptr++) = 0x69;
1539 emit_membase(cd, (basereg),(disp),(dreg));
1545 void emit_idiv_reg(codegendata *cd, s8 reg) {
1546 emit_rex(1,0,0,(reg));
1547 *(cd->mcodeptr++) = 0xf7;
1552 void emit_idivl_reg(codegendata *cd, s8 reg) {
1553 emit_rex(0,0,0,(reg));
1554 *(cd->mcodeptr++) = 0xf7;
1563 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1564 emit_rex(1,0,0,(reg));
1565 *(cd->mcodeptr++) = 0xd3;
1566 emit_reg((opc),(reg));
1570 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1571 emit_rex(0,0,0,(reg));
1572 *(cd->mcodeptr++) = 0xd3;
1573 emit_reg((opc),(reg));
1577 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1578 emit_rex(1,0,0,(basereg));
1579 *(cd->mcodeptr++) = 0xd3;
1580 emit_membase(cd, (basereg),(disp),(opc));
1584 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1585 emit_rex(0,0,0,(basereg));
1586 *(cd->mcodeptr++) = 0xd3;
1587 emit_membase(cd, (basereg),(disp),(opc));
1591 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1593 emit_rex(1,0,0,(dreg));
1594 *(cd->mcodeptr++) = 0xd1;
1595 emit_reg((opc),(dreg));
1597 emit_rex(1,0,0,(dreg));
1598 *(cd->mcodeptr++) = 0xc1;
1599 emit_reg((opc),(dreg));
1605 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1607 emit_rex(0,0,0,(dreg));
1608 *(cd->mcodeptr++) = 0xd1;
1609 emit_reg((opc),(dreg));
1611 emit_rex(0,0,0,(dreg));
1612 *(cd->mcodeptr++) = 0xc1;
1613 emit_reg((opc),(dreg));
1619 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1621 emit_rex(1,0,0,(basereg));
1622 *(cd->mcodeptr++) = 0xd1;
1623 emit_membase(cd, (basereg),(disp),(opc));
1625 emit_rex(1,0,0,(basereg));
1626 *(cd->mcodeptr++) = 0xc1;
1627 emit_membase(cd, (basereg),(disp),(opc));
1633 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1635 emit_rex(0,0,0,(basereg));
1636 *(cd->mcodeptr++) = 0xd1;
1637 emit_membase(cd, (basereg),(disp),(opc));
1639 emit_rex(0,0,0,(basereg));
1640 *(cd->mcodeptr++) = 0xc1;
1641 emit_membase(cd, (basereg),(disp),(opc));
1651 void emit_jmp_imm(codegendata *cd, s8 imm) {
1652 *(cd->mcodeptr++) = 0xe9;
1657 void emit_jmp_reg(codegendata *cd, s8 reg) {
1658 emit_rex(0,0,0,(reg));
1659 *(cd->mcodeptr++) = 0xff;
1664 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1665 *(cd->mcodeptr++) = 0x0f;
1666 *(cd->mcodeptr++) = (0x80 + (opc));
1673 * conditional set and move operations
1676 /* we need the rex byte to get all low bytes */
1677 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1679 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1680 *(cd->mcodeptr++) = 0x0f;
1681 *(cd->mcodeptr++) = (0x90 + (opc));
1686 /* we need the rex byte to get all low bytes */
1687 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1689 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1690 *(cd->mcodeptr++) = 0x0f;
1691 *(cd->mcodeptr++) = (0x90 + (opc));
1692 emit_membase(cd, (basereg),(disp),0);
1696 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1698 emit_rex(1,(dreg),0,(reg));
1699 *(cd->mcodeptr++) = 0x0f;
1700 *(cd->mcodeptr++) = (0x40 + (opc));
1701 emit_reg((dreg),(reg));
1705 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1707 emit_rex(0,(dreg),0,(reg));
1708 *(cd->mcodeptr++) = 0x0f;
1709 *(cd->mcodeptr++) = (0x40 + (opc));
1710 emit_reg((dreg),(reg));
1714 void emit_neg_reg(codegendata *cd, s8 reg)
1716 emit_rex(1,0,0,(reg));
1717 *(cd->mcodeptr++) = 0xf7;
1722 void emit_negl_reg(codegendata *cd, s8 reg)
1724 emit_rex(0,0,0,(reg));
1725 *(cd->mcodeptr++) = 0xf7;
1730 void emit_push_reg(codegendata *cd, s8 reg) {
1731 emit_rex(0,0,0,(reg));
1732 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1736 void emit_push_imm(codegendata *cd, s8 imm) {
1737 *(cd->mcodeptr++) = 0x68;
1742 void emit_pop_reg(codegendata *cd, s8 reg) {
1743 emit_rex(0,0,0,(reg));
1744 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1748 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1749 emit_rex(1,(reg),0,(dreg));
1750 *(cd->mcodeptr++) = 0x87;
1751 emit_reg((reg),(dreg));
1759 void emit_call_reg(codegendata *cd, s8 reg)
1761 emit_rex(0,0,0,(reg));
1762 *(cd->mcodeptr++) = 0xff;
1767 void emit_call_imm(codegendata *cd, s8 imm)
1769 *(cd->mcodeptr++) = 0xe8;
1774 void emit_call_mem(codegendata *cd, ptrint mem)
1776 *(cd->mcodeptr++) = 0xff;
1783 * floating point instructions (SSE2)
1785 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1786 *(cd->mcodeptr++) = 0xf2;
1787 emit_rex(0,(dreg),0,(reg));
1788 *(cd->mcodeptr++) = 0x0f;
1789 *(cd->mcodeptr++) = 0x58;
1790 emit_reg((dreg),(reg));
1794 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1795 *(cd->mcodeptr++) = 0xf3;
1796 emit_rex(0,(dreg),0,(reg));
1797 *(cd->mcodeptr++) = 0x0f;
1798 *(cd->mcodeptr++) = 0x58;
1799 emit_reg((dreg),(reg));
1803 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1804 *(cd->mcodeptr++) = 0xf3;
1805 emit_rex(1,(dreg),0,(reg));
1806 *(cd->mcodeptr++) = 0x0f;
1807 *(cd->mcodeptr++) = 0x2a;
1808 emit_reg((dreg),(reg));
1812 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1813 *(cd->mcodeptr++) = 0xf3;
1814 emit_rex(0,(dreg),0,(reg));
1815 *(cd->mcodeptr++) = 0x0f;
1816 *(cd->mcodeptr++) = 0x2a;
1817 emit_reg((dreg),(reg));
1821 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1822 *(cd->mcodeptr++) = 0xf2;
1823 emit_rex(1,(dreg),0,(reg));
1824 *(cd->mcodeptr++) = 0x0f;
1825 *(cd->mcodeptr++) = 0x2a;
1826 emit_reg((dreg),(reg));
1830 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1831 *(cd->mcodeptr++) = 0xf2;
1832 emit_rex(0,(dreg),0,(reg));
1833 *(cd->mcodeptr++) = 0x0f;
1834 *(cd->mcodeptr++) = 0x2a;
1835 emit_reg((dreg),(reg));
1839 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1840 *(cd->mcodeptr++) = 0xf3;
1841 emit_rex(0,(dreg),0,(reg));
1842 *(cd->mcodeptr++) = 0x0f;
1843 *(cd->mcodeptr++) = 0x5a;
1844 emit_reg((dreg),(reg));
1848 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1849 *(cd->mcodeptr++) = 0xf2;
1850 emit_rex(0,(dreg),0,(reg));
1851 *(cd->mcodeptr++) = 0x0f;
1852 *(cd->mcodeptr++) = 0x5a;
1853 emit_reg((dreg),(reg));
1857 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1858 *(cd->mcodeptr++) = 0xf3;
1859 emit_rex(1,(dreg),0,(reg));
1860 *(cd->mcodeptr++) = 0x0f;
1861 *(cd->mcodeptr++) = 0x2c;
1862 emit_reg((dreg),(reg));
1866 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1867 *(cd->mcodeptr++) = 0xf3;
1868 emit_rex(0,(dreg),0,(reg));
1869 *(cd->mcodeptr++) = 0x0f;
1870 *(cd->mcodeptr++) = 0x2c;
1871 emit_reg((dreg),(reg));
1875 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1876 *(cd->mcodeptr++) = 0xf2;
1877 emit_rex(1,(dreg),0,(reg));
1878 *(cd->mcodeptr++) = 0x0f;
1879 *(cd->mcodeptr++) = 0x2c;
1880 emit_reg((dreg),(reg));
1884 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1885 *(cd->mcodeptr++) = 0xf2;
1886 emit_rex(0,(dreg),0,(reg));
1887 *(cd->mcodeptr++) = 0x0f;
1888 *(cd->mcodeptr++) = 0x2c;
1889 emit_reg((dreg),(reg));
1893 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1894 *(cd->mcodeptr++) = 0xf3;
1895 emit_rex(0,(dreg),0,(reg));
1896 *(cd->mcodeptr++) = 0x0f;
1897 *(cd->mcodeptr++) = 0x5e;
1898 emit_reg((dreg),(reg));
1902 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1903 *(cd->mcodeptr++) = 0xf2;
1904 emit_rex(0,(dreg),0,(reg));
1905 *(cd->mcodeptr++) = 0x0f;
1906 *(cd->mcodeptr++) = 0x5e;
1907 emit_reg((dreg),(reg));
1911 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1912 *(cd->mcodeptr++) = 0x66;
1913 emit_rex(1,(freg),0,(reg));
1914 *(cd->mcodeptr++) = 0x0f;
1915 *(cd->mcodeptr++) = 0x6e;
1916 emit_reg((freg),(reg));
1920 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1921 *(cd->mcodeptr++) = 0x66;
1922 emit_rex(1,(freg),0,(reg));
1923 *(cd->mcodeptr++) = 0x0f;
1924 *(cd->mcodeptr++) = 0x7e;
1925 emit_reg((freg),(reg));
1929 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1930 *(cd->mcodeptr++) = 0x66;
1931 emit_rex(0,(reg),0,(basereg));
1932 *(cd->mcodeptr++) = 0x0f;
1933 *(cd->mcodeptr++) = 0x7e;
1934 emit_membase(cd, (basereg),(disp),(reg));
1938 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1939 *(cd->mcodeptr++) = 0x66;
1940 emit_rex(0,(reg),(indexreg),(basereg));
1941 *(cd->mcodeptr++) = 0x0f;
1942 *(cd->mcodeptr++) = 0x7e;
1943 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1947 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1948 *(cd->mcodeptr++) = 0x66;
1949 emit_rex(1,(dreg),0,(basereg));
1950 *(cd->mcodeptr++) = 0x0f;
1951 *(cd->mcodeptr++) = 0x6e;
1952 emit_membase(cd, (basereg),(disp),(dreg));
1956 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1957 *(cd->mcodeptr++) = 0x66;
1958 emit_rex(0,(dreg),0,(basereg));
1959 *(cd->mcodeptr++) = 0x0f;
1960 *(cd->mcodeptr++) = 0x6e;
1961 emit_membase(cd, (basereg),(disp),(dreg));
1965 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
1966 *(cd->mcodeptr++) = 0x66;
1967 emit_rex(0,(dreg),(indexreg),(basereg));
1968 *(cd->mcodeptr++) = 0x0f;
1969 *(cd->mcodeptr++) = 0x6e;
1970 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
1974 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1975 *(cd->mcodeptr++) = 0xf3;
1976 emit_rex(0,(dreg),0,(reg));
1977 *(cd->mcodeptr++) = 0x0f;
1978 *(cd->mcodeptr++) = 0x7e;
1979 emit_reg((dreg),(reg));
1983 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1984 *(cd->mcodeptr++) = 0x66;
1985 emit_rex(0,(reg),0,(basereg));
1986 *(cd->mcodeptr++) = 0x0f;
1987 *(cd->mcodeptr++) = 0xd6;
1988 emit_membase(cd, (basereg),(disp),(reg));
1992 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1993 *(cd->mcodeptr++) = 0xf3;
1994 emit_rex(0,(dreg),0,(basereg));
1995 *(cd->mcodeptr++) = 0x0f;
1996 *(cd->mcodeptr++) = 0x7e;
1997 emit_membase(cd, (basereg),(disp),(dreg));
2001 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2002 *(cd->mcodeptr++) = 0xf3;
2003 emit_rex(0,(reg),0,(dreg));
2004 *(cd->mcodeptr++) = 0x0f;
2005 *(cd->mcodeptr++) = 0x10;
2006 emit_reg((reg),(dreg));
2010 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2011 *(cd->mcodeptr++) = 0xf2;
2012 emit_rex(0,(reg),0,(dreg));
2013 *(cd->mcodeptr++) = 0x0f;
2014 *(cd->mcodeptr++) = 0x10;
2015 emit_reg((reg),(dreg));
2019 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2020 *(cd->mcodeptr++) = 0xf3;
2021 emit_rex(0,(reg),0,(basereg));
2022 *(cd->mcodeptr++) = 0x0f;
2023 *(cd->mcodeptr++) = 0x11;
2024 emit_membase(cd, (basereg),(disp),(reg));
2028 /* Always emit a REX byte, because the instruction size can be smaller when */
2029 /* all register indexes are smaller than 7. */
2030 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2031 *(cd->mcodeptr++) = 0xf3;
2032 emit_byte_rex((reg),0,(basereg));
2033 *(cd->mcodeptr++) = 0x0f;
2034 *(cd->mcodeptr++) = 0x11;
2035 emit_membase32(cd, (basereg),(disp),(reg));
2039 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2040 *(cd->mcodeptr++) = 0xf2;
2041 emit_rex(0,(reg),0,(basereg));
2042 *(cd->mcodeptr++) = 0x0f;
2043 *(cd->mcodeptr++) = 0x11;
2044 emit_membase(cd, (basereg),(disp),(reg));
2048 /* Always emit a REX byte, because the instruction size can be smaller when */
2049 /* all register indexes are smaller than 7. */
2050 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2051 *(cd->mcodeptr++) = 0xf2;
2052 emit_byte_rex((reg),0,(basereg));
2053 *(cd->mcodeptr++) = 0x0f;
2054 *(cd->mcodeptr++) = 0x11;
2055 emit_membase32(cd, (basereg),(disp),(reg));
2059 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2060 *(cd->mcodeptr++) = 0xf3;
2061 emit_rex(0,(dreg),0,(basereg));
2062 *(cd->mcodeptr++) = 0x0f;
2063 *(cd->mcodeptr++) = 0x10;
2064 emit_membase(cd, (basereg),(disp),(dreg));
2068 /* Always emit a REX byte, because the instruction size can be smaller when */
2069 /* all register indexes are smaller than 7. */
2070 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2071 *(cd->mcodeptr++) = 0xf3;
2072 emit_byte_rex((dreg),0,(basereg));
2073 *(cd->mcodeptr++) = 0x0f;
2074 *(cd->mcodeptr++) = 0x10;
2075 emit_membase32(cd, (basereg),(disp),(dreg));
2079 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2081 emit_rex(0,(dreg),0,(basereg));
2082 *(cd->mcodeptr++) = 0x0f;
2083 *(cd->mcodeptr++) = 0x12;
2084 emit_membase(cd, (basereg),(disp),(dreg));
2088 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2090 emit_rex(0,(reg),0,(basereg));
2091 *(cd->mcodeptr++) = 0x0f;
2092 *(cd->mcodeptr++) = 0x13;
2093 emit_membase(cd, (basereg),(disp),(reg));
2097 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2098 *(cd->mcodeptr++) = 0xf2;
2099 emit_rex(0,(dreg),0,(basereg));
2100 *(cd->mcodeptr++) = 0x0f;
2101 *(cd->mcodeptr++) = 0x10;
2102 emit_membase(cd, (basereg),(disp),(dreg));
2106 /* Always emit a REX byte, because the instruction size can be smaller when */
2107 /* all register indexes are smaller than 7. */
2108 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2109 *(cd->mcodeptr++) = 0xf2;
2110 emit_byte_rex((dreg),0,(basereg));
2111 *(cd->mcodeptr++) = 0x0f;
2112 *(cd->mcodeptr++) = 0x10;
2113 emit_membase32(cd, (basereg),(disp),(dreg));
2117 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2119 *(cd->mcodeptr++) = 0x66;
2120 emit_rex(0,(dreg),0,(basereg));
2121 *(cd->mcodeptr++) = 0x0f;
2122 *(cd->mcodeptr++) = 0x12;
2123 emit_membase(cd, (basereg),(disp),(dreg));
2127 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2129 *(cd->mcodeptr++) = 0x66;
2130 emit_rex(0,(reg),0,(basereg));
2131 *(cd->mcodeptr++) = 0x0f;
2132 *(cd->mcodeptr++) = 0x13;
2133 emit_membase(cd, (basereg),(disp),(reg));
2137 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2138 *(cd->mcodeptr++) = 0xf3;
2139 emit_rex(0,(reg),(indexreg),(basereg));
2140 *(cd->mcodeptr++) = 0x0f;
2141 *(cd->mcodeptr++) = 0x11;
2142 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2146 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2147 *(cd->mcodeptr++) = 0xf2;
2148 emit_rex(0,(reg),(indexreg),(basereg));
2149 *(cd->mcodeptr++) = 0x0f;
2150 *(cd->mcodeptr++) = 0x11;
2151 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2155 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2156 *(cd->mcodeptr++) = 0xf3;
2157 emit_rex(0,(dreg),(indexreg),(basereg));
2158 *(cd->mcodeptr++) = 0x0f;
2159 *(cd->mcodeptr++) = 0x10;
2160 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2164 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2165 *(cd->mcodeptr++) = 0xf2;
2166 emit_rex(0,(dreg),(indexreg),(basereg));
2167 *(cd->mcodeptr++) = 0x0f;
2168 *(cd->mcodeptr++) = 0x10;
2169 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2173 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2174 *(cd->mcodeptr++) = 0xf3;
2175 emit_rex(0,(dreg),0,(reg));
2176 *(cd->mcodeptr++) = 0x0f;
2177 *(cd->mcodeptr++) = 0x59;
2178 emit_reg((dreg),(reg));
2182 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2183 *(cd->mcodeptr++) = 0xf2;
2184 emit_rex(0,(dreg),0,(reg));
2185 *(cd->mcodeptr++) = 0x0f;
2186 *(cd->mcodeptr++) = 0x59;
2187 emit_reg((dreg),(reg));
2191 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2192 *(cd->mcodeptr++) = 0xf3;
2193 emit_rex(0,(dreg),0,(reg));
2194 *(cd->mcodeptr++) = 0x0f;
2195 *(cd->mcodeptr++) = 0x5c;
2196 emit_reg((dreg),(reg));
2200 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2201 *(cd->mcodeptr++) = 0xf2;
2202 emit_rex(0,(dreg),0,(reg));
2203 *(cd->mcodeptr++) = 0x0f;
2204 *(cd->mcodeptr++) = 0x5c;
2205 emit_reg((dreg),(reg));
2209 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2210 emit_rex(0,(dreg),0,(reg));
2211 *(cd->mcodeptr++) = 0x0f;
2212 *(cd->mcodeptr++) = 0x2e;
2213 emit_reg((dreg),(reg));
2217 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2218 *(cd->mcodeptr++) = 0x66;
2219 emit_rex(0,(dreg),0,(reg));
2220 *(cd->mcodeptr++) = 0x0f;
2221 *(cd->mcodeptr++) = 0x2e;
2222 emit_reg((dreg),(reg));
2226 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2227 emit_rex(0,(dreg),0,(reg));
2228 *(cd->mcodeptr++) = 0x0f;
2229 *(cd->mcodeptr++) = 0x57;
2230 emit_reg((dreg),(reg));
2234 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2235 emit_rex(0,(dreg),0,(basereg));
2236 *(cd->mcodeptr++) = 0x0f;
2237 *(cd->mcodeptr++) = 0x57;
2238 emit_membase(cd, (basereg),(disp),(dreg));
2242 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2243 *(cd->mcodeptr++) = 0x66;
2244 emit_rex(0,(dreg),0,(reg));
2245 *(cd->mcodeptr++) = 0x0f;
2246 *(cd->mcodeptr++) = 0x57;
2247 emit_reg((dreg),(reg));
2251 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2252 *(cd->mcodeptr++) = 0x66;
2253 emit_rex(0,(dreg),0,(basereg));
2254 *(cd->mcodeptr++) = 0x0f;
2255 *(cd->mcodeptr++) = 0x57;
2256 emit_membase(cd, (basereg),(disp),(dreg));
2260 /* system instructions ********************************************************/
2262 void emit_rdtsc(codegendata *cd)
2264 *(cd->mcodeptr++) = 0x0f;
2265 *(cd->mcodeptr++) = 0x31;
2270 * These are local overrides for various environment variables in Emacs.
2271 * Please do not remove this and leave it at the end of the file, where
2272 * Emacs will automagically detect them.
2273 * ---------------------------------------------------------------------
2276 * indent-tabs-mode: t