1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
35 #include "vm/jit/x86_64/codegen.h"
36 #include "vm/jit/x86_64/emit.h"
38 #include "mm/memory.h"
40 #include "threads/lock-common.h"
42 #include "vm/builtin.h"
43 #include "vm/exceptions.h"
45 #include "vm/jit/abi.h"
46 #include "vm/jit/abi-asm.h"
47 #include "vm/jit/asmpart.h"
48 #include "vm/jit/codegen-common.h"
49 #include "vm/jit/emit-common.h"
50 #include "vm/jit/jit.h"
51 #include "vm/jit/replace.h"
53 #include "vmcore/options.h"
56 /* emit_load *******************************************************************
58 Emits a possible load of an operand.
60 *******************************************************************************/
62 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
68 /* get required compiler data */
72 if (IS_INMEMORY(src->flags)) {
75 disp = src->vv.regoff;
79 M_ILD(tempreg, REG_SP, disp);
83 M_LLD(tempreg, REG_SP, disp);
86 M_FLD(tempreg, REG_SP, disp);
89 M_DLD(tempreg, REG_SP, disp);
92 vm_abort("emit_load: unknown type %d", src->type);
104 /* emit_store ******************************************************************
106 This function generates the code to store the result of an
107 operation back into a spilled pseudo-variable. If the
108 pseudo-variable has not been spilled in the first place, this
109 function will generate nothing.
111 *******************************************************************************/
113 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
122 /* get required compiler data */
127 /* do we have to generate a conditional move? */
129 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
130 /* the passed register d is actually the source register */
134 /* Only pass the opcode to codegen_reg_of_var to get the real
135 destination register. */
137 opcode = iptr->opc & ICMD_OPCODE_MASK;
139 /* get the real destination register */
141 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
143 /* and emit the conditional move */
145 emit_cmovxx(cd, iptr, s, d);
149 if (IS_INMEMORY(dst->flags)) {
152 disp = dst->vv.regoff;
158 M_LST(d, REG_SP, disp);
161 M_FST(d, REG_SP, disp);
164 M_DST(d, REG_SP, disp);
167 vm_abort("emit_store: unknown type %d", dst->type);
173 /* emit_copy *******************************************************************
175 Generates a register/memory to register/memory copy.
177 *******************************************************************************/
179 void emit_copy(jitdata *jd, instruction *iptr)
186 /* get required compiler data */
190 /* get source and destination variables */
192 src = VAROP(iptr->s1);
193 dst = VAROP(iptr->dst);
195 if ((src->vv.regoff != dst->vv.regoff) ||
196 ((src->flags ^ dst->flags) & INMEMORY)) {
198 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
199 /* emit nothing, as the value won't be used anyway */
203 /* If one of the variables resides in memory, we can eliminate
204 the register move from/to the temporary register with the
205 order of getting the destination register and the load. */
207 if (IS_INMEMORY(src->flags)) {
208 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
209 s1 = emit_load(jd, iptr, src, d);
212 s1 = emit_load(jd, iptr, src, REG_IFTMP);
213 d = codegen_reg_of_var(iptr->opc, dst, s1);
228 vm_abort("emit_copy: unknown type %d", src->type);
232 emit_store(jd, iptr, dst, d);
237 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
240 switch (iptr->flags.fields.condition) {
264 /* emit_branch *****************************************************************
266 Emits the code for conditional and unconditional branchs.
268 *******************************************************************************/
270 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
274 /* NOTE: A displacement overflow cannot happen. */
276 /* check which branch to generate */
278 if (condition == BRANCH_UNCONDITIONAL) {
280 /* calculate the different displacements */
282 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
284 M_JMP_IMM(branchdisp);
287 /* calculate the different displacements */
289 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
323 vm_abort("emit_branch: unknown condition %d", condition);
329 /* emit_arithmetic_check *******************************************************
331 Emit an ArithmeticException check.
333 *******************************************************************************/
335 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
337 if (INSTRUCTION_MUST_CHECK(iptr)) {
340 M_ALD_MEM(reg, EXCEPTION_HARDWARE_ARITHMETIC);
345 /* emit_arrayindexoutofbounds_check ********************************************
347 Emit a ArrayIndexOutOfBoundsException check.
349 *******************************************************************************/
351 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
353 if (INSTRUCTION_MUST_CHECK(iptr)) {
354 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
355 M_ICMP(REG_ITMP3, s2);
357 M_ALD_MEM(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
362 /* emit_classcast_check ********************************************************
364 Emit a ClassCastException check.
366 *******************************************************************************/
368 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
370 if (INSTRUCTION_MUST_CHECK(iptr)) {
382 vm_abort("emit_classcast_check: unknown condition %d", condition);
384 M_ALD_MEM(s1, EXCEPTION_HARDWARE_CLASSCAST);
389 /* emit_nullpointer_check ******************************************************
391 Emit a NullPointerException check.
393 *******************************************************************************/
395 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
397 if (INSTRUCTION_MUST_CHECK(iptr)) {
400 M_ALD_MEM(reg, EXCEPTION_HARDWARE_NULLPOINTER);
405 /* emit_exception_check ********************************************************
407 Emit an Exception check.
409 *******************************************************************************/
411 void emit_exception_check(codegendata *cd, instruction *iptr)
413 if (INSTRUCTION_MUST_CHECK(iptr)) {
416 M_ALD_MEM(REG_RESULT, EXCEPTION_HARDWARE_EXCEPTION);
421 /* emit_patcher_stubs **********************************************************
423 Generates the code for the patcher stubs.
425 *******************************************************************************/
427 void emit_patcher_stubs(jitdata *jd)
437 /* get required compiler data */
441 /* generate code patching stub call code */
445 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
446 /* check size of code segment */
450 /* Get machine code which is patched back in later. A
451 `call rel32' is 5 bytes long (but read 8 bytes). */
453 savedmcodeptr = cd->mcodebase + pref->branchpos;
454 mcode = *((u8 *) savedmcodeptr);
456 /* patch in `call rel32' to call the following code */
458 tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
459 cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
461 M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE));
463 cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
465 /* move pointer to java_objectheader onto stack */
467 #if defined(ENABLE_THREADS)
468 /* create a virtual java_objectheader */
470 (void) dseg_add_unique_address(cd, NULL); /* flcword */
471 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
472 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
474 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase) + disp, REG_ITMP3);
480 /* move machine code bytes and classinfo pointer into registers */
482 M_MOV_IMM(mcode, REG_ITMP3);
485 M_MOV_IMM(pref->ref, REG_ITMP3);
488 M_MOV_IMM(pref->disp, REG_ITMP3);
491 M_MOV_IMM(pref->patcher, REG_ITMP3);
494 if (targetdisp == 0) {
495 targetdisp = cd->mcodeptr - cd->mcodebase;
497 M_MOV_IMM(asm_patcher_wrapper, REG_ITMP3);
501 M_JMP_IMM((cd->mcodebase + targetdisp) -
502 (cd->mcodeptr + PATCHER_CALL_SIZE));
508 /* emit_trap *******************************************************************
510 Emit a trap instruction and return the original machine code.
512 *******************************************************************************/
514 uint32_t emit_trap(codegendata *cd)
518 /* Get machine code which is patched back in later. The
519 trap is 1 instruction word long. */
521 mcode = *((uint32_t *) cd->mcodeptr);
529 /* emit_verbosecall_enter ******************************************************
531 Generates the code for the call trace.
533 *******************************************************************************/
536 void emit_verbosecall_enter(jitdata *jd)
544 /* get required compiler data */
552 /* mark trace code */
556 /* additional +1 is for 16-byte stack alignment */
558 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
560 /* save argument registers */
562 for (i = 0; i < INT_ARG_CNT; i++)
563 M_LST(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
565 for (i = 0; i < FLT_ARG_CNT; i++)
566 M_DST(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
568 /* save temporary registers for leaf methods */
570 if (jd->isleafmethod) {
571 for (i = 0; i < INT_TMP_CNT; i++)
572 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
574 for (i = 0; i < FLT_TMP_CNT; i++)
575 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
578 /* show integer hex code for float arguments */
580 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
581 /* If the paramtype is a float, we have to right shift all
582 following integer registers. */
584 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
585 for (k = INT_ARG_CNT - 2; k >= i; k--)
586 M_MOV(abi_registers_integer_argument[k],
587 abi_registers_integer_argument[k + 1]);
589 emit_movd_freg_reg(cd, abi_registers_float_argument[j],
590 abi_registers_integer_argument[i]);
595 M_MOV_IMM(m, REG_ITMP2);
596 M_AST(REG_ITMP2, REG_SP, 0 * 8);
597 M_MOV_IMM(builtin_verbosecall_enter, REG_ITMP1);
600 /* restore argument registers */
602 for (i = 0; i < INT_ARG_CNT; i++)
603 M_LLD(abi_registers_integer_argument[i], REG_SP, (1 + i) * 8);
605 for (i = 0; i < FLT_ARG_CNT; i++)
606 M_DLD(abi_registers_float_argument[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
608 /* restore temporary registers for leaf methods */
610 if (jd->isleafmethod) {
611 for (i = 0; i < INT_TMP_CNT; i++)
612 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
614 for (i = 0; i < FLT_TMP_CNT; i++)
615 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
618 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
620 /* mark trace code */
624 #endif /* !defined(NDEBUG) */
627 /* emit_verbosecall_exit *******************************************************
629 Generates the code for the call trace.
631 *******************************************************************************/
634 void emit_verbosecall_exit(jitdata *jd)
640 /* get required compiler data */
646 /* mark trace code */
650 M_ASUB_IMM(2 * 8, REG_SP);
652 M_LST(REG_RESULT, REG_SP, 0 * 8);
653 M_DST(REG_FRESULT, REG_SP, 1 * 8);
655 M_INTMOVE(REG_RESULT, REG_A0);
656 M_FLTMOVE(REG_FRESULT, REG_FA0);
657 M_FLTMOVE(REG_FRESULT, REG_FA1);
658 M_MOV_IMM(m, REG_A1);
660 M_MOV_IMM(builtin_verbosecall_exit, REG_ITMP1);
663 M_LLD(REG_RESULT, REG_SP, 0 * 8);
664 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
666 M_AADD_IMM(2 * 8, REG_SP);
668 /* mark trace code */
672 #endif /* !defined(NDEBUG) */
675 /* code generation functions **************************************************/
677 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
679 if ((basereg == REG_SP) || (basereg == R12)) {
681 emit_address_byte(0, dreg, REG_SP);
682 emit_address_byte(0, REG_SP, REG_SP);
684 } else if (IS_IMM8(disp)) {
685 emit_address_byte(1, dreg, REG_SP);
686 emit_address_byte(0, REG_SP, REG_SP);
690 emit_address_byte(2, dreg, REG_SP);
691 emit_address_byte(0, REG_SP, REG_SP);
695 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
696 emit_address_byte(0,(dreg),(basereg));
698 } else if ((basereg) == RIP) {
699 emit_address_byte(0, dreg, RBP);
704 emit_address_byte(1, dreg, basereg);
708 emit_address_byte(2, dreg, basereg);
715 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
717 if ((basereg == REG_SP) || (basereg == R12)) {
718 emit_address_byte(2, dreg, REG_SP);
719 emit_address_byte(0, REG_SP, REG_SP);
723 emit_address_byte(2, dreg, basereg);
729 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
732 emit_address_byte(0, reg, 4);
733 emit_address_byte(scale, indexreg, 5);
736 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
737 emit_address_byte(0, reg, 4);
738 emit_address_byte(scale, indexreg, basereg);
740 else if (IS_IMM8(disp)) {
741 emit_address_byte(1, reg, 4);
742 emit_address_byte(scale, indexreg, basereg);
746 emit_address_byte(2, reg, 4);
747 emit_address_byte(scale, indexreg, basereg);
753 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
756 varinfo *v_s1,*v_s2,*v_dst;
759 /* get required compiler data */
763 v_s1 = VAROP(iptr->s1);
764 v_s2 = VAROP(iptr->sx.s23.s2);
765 v_dst = VAROP(iptr->dst);
767 s1 = v_s1->vv.regoff;
768 s2 = v_s2->vv.regoff;
769 d = v_dst->vv.regoff;
771 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
773 if (IS_INMEMORY(v_dst->flags)) {
774 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
776 M_ILD(RCX, REG_SP, s2);
777 emit_shiftl_membase(cd, shift_op, REG_SP, d);
780 M_ILD(RCX, REG_SP, s2);
781 M_ILD(REG_ITMP2, REG_SP, s1);
782 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
783 M_IST(REG_ITMP2, REG_SP, d);
786 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
787 /* s1 may be equal to RCX */
790 M_ILD(REG_ITMP1, REG_SP, s2);
791 M_IST(s1, REG_SP, d);
792 M_INTMOVE(REG_ITMP1, RCX);
795 M_IST(s1, REG_SP, d);
796 M_ILD(RCX, REG_SP, s2);
800 M_ILD(RCX, REG_SP, s2);
801 M_IST(s1, REG_SP, d);
804 emit_shiftl_membase(cd, shift_op, REG_SP, d);
806 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
809 emit_shiftl_membase(cd, shift_op, REG_SP, d);
813 M_ILD(REG_ITMP2, REG_SP, s1);
814 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
815 M_IST(REG_ITMP2, REG_SP, d);
819 /* s1 may be equal to RCX */
820 M_IST(s1, REG_SP, d);
822 emit_shiftl_membase(cd, shift_op, REG_SP, d);
825 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
833 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
834 M_ILD(RCX, REG_SP, s2);
835 M_ILD(d, REG_SP, s1);
836 emit_shiftl_reg(cd, shift_op, d);
838 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
839 /* s1 may be equal to RCX */
841 M_ILD(RCX, REG_SP, s2);
842 emit_shiftl_reg(cd, shift_op, d);
844 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
846 M_ILD(d, REG_SP, s1);
847 emit_shiftl_reg(cd, shift_op, d);
850 /* s1 may be equal to RCX */
853 /* d cannot be used to backup s1 since this would
855 M_INTMOVE(s1, REG_ITMP3);
857 M_INTMOVE(REG_ITMP3, d);
865 /* d may be equal to s2 */
869 emit_shiftl_reg(cd, shift_op, d);
873 M_INTMOVE(REG_ITMP3, RCX);
875 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
880 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
883 varinfo *v_s1,*v_s2,*v_dst;
886 /* get required compiler data */
890 v_s1 = VAROP(iptr->s1);
891 v_s2 = VAROP(iptr->sx.s23.s2);
892 v_dst = VAROP(iptr->dst);
894 s1 = v_s1->vv.regoff;
895 s2 = v_s2->vv.regoff;
896 d = v_dst->vv.regoff;
898 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
900 if (IS_INMEMORY(v_dst->flags)) {
901 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
903 M_ILD(RCX, REG_SP, s2);
904 emit_shift_membase(cd, shift_op, REG_SP, d);
907 M_ILD(RCX, REG_SP, s2);
908 M_LLD(REG_ITMP2, REG_SP, s1);
909 emit_shift_reg(cd, shift_op, REG_ITMP2);
910 M_LST(REG_ITMP2, REG_SP, d);
913 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
914 /* s1 may be equal to RCX */
917 M_ILD(REG_ITMP1, REG_SP, s2);
918 M_LST(s1, REG_SP, d);
919 M_INTMOVE(REG_ITMP1, RCX);
922 M_LST(s1, REG_SP, d);
923 M_ILD(RCX, REG_SP, s2);
927 M_ILD(RCX, REG_SP, s2);
928 M_LST(s1, REG_SP, d);
931 emit_shift_membase(cd, shift_op, REG_SP, d);
933 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
936 emit_shift_membase(cd, shift_op, REG_SP, d);
940 M_LLD(REG_ITMP2, REG_SP, s1);
941 emit_shift_reg(cd, shift_op, REG_ITMP2);
942 M_LST(REG_ITMP2, REG_SP, d);
946 /* s1 may be equal to RCX */
947 M_LST(s1, REG_SP, d);
949 emit_shift_membase(cd, shift_op, REG_SP, d);
952 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
960 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
961 M_ILD(RCX, REG_SP, s2);
962 M_LLD(d, REG_SP, s1);
963 emit_shift_reg(cd, shift_op, d);
965 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
966 /* s1 may be equal to RCX */
968 M_ILD(RCX, REG_SP, s2);
969 emit_shift_reg(cd, shift_op, d);
971 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
973 M_LLD(d, REG_SP, s1);
974 emit_shift_reg(cd, shift_op, d);
977 /* s1 may be equal to RCX */
980 /* d cannot be used to backup s1 since this would
982 M_INTMOVE(s1, REG_ITMP3);
984 M_INTMOVE(REG_ITMP3, d);
992 /* d may be equal to s2 */
996 emit_shift_reg(cd, shift_op, d);
1000 M_INTMOVE(REG_ITMP3, RCX);
1002 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1007 /* low-level code emitter functions *******************************************/
1009 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1011 emit_rex(1,(reg),0,(dreg));
1012 *(cd->mcodeptr++) = 0x89;
1013 emit_reg((reg),(dreg));
1017 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1019 emit_rex(1,0,0,(reg));
1020 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1025 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1027 emit_rex(0,(reg),0,(dreg));
1028 *(cd->mcodeptr++) = 0x89;
1029 emit_reg((reg),(dreg));
1033 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1034 emit_rex(0,0,0,(reg));
1035 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1040 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1041 emit_rex(1,(reg),0,(basereg));
1042 *(cd->mcodeptr++) = 0x8b;
1043 emit_membase(cd, (basereg),(disp),(reg));
1048 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1049 * constant membase immediate length of 32bit
1051 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1052 emit_rex(1,(reg),0,(basereg));
1053 *(cd->mcodeptr++) = 0x8b;
1054 emit_membase32(cd, (basereg),(disp),(reg));
1058 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1060 emit_rex(0,(reg),0,(basereg));
1061 *(cd->mcodeptr++) = 0x8b;
1062 emit_membase(cd, (basereg),(disp),(reg));
1066 /* ATTENTION: Always emit a REX byte, because the instruction size can
1067 be smaller when all register indexes are smaller than 7. */
1068 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1070 emit_byte_rex((reg),0,(basereg));
1071 *(cd->mcodeptr++) = 0x8b;
1072 emit_membase32(cd, (basereg),(disp),(reg));
1076 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1077 emit_rex(1,(reg),0,(basereg));
1078 *(cd->mcodeptr++) = 0x89;
1079 emit_membase(cd, (basereg),(disp),(reg));
1083 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1084 emit_rex(1,(reg),0,(basereg));
1085 *(cd->mcodeptr++) = 0x89;
1086 emit_membase32(cd, (basereg),(disp),(reg));
1090 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1091 emit_rex(0,(reg),0,(basereg));
1092 *(cd->mcodeptr++) = 0x89;
1093 emit_membase(cd, (basereg),(disp),(reg));
1097 /* Always emit a REX byte, because the instruction size can be smaller when */
1098 /* all register indexes are smaller than 7. */
1099 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1100 emit_byte_rex((reg),0,(basereg));
1101 *(cd->mcodeptr++) = 0x89;
1102 emit_membase32(cd, (basereg),(disp),(reg));
1106 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1107 emit_rex(1,(reg),(indexreg),(basereg));
1108 *(cd->mcodeptr++) = 0x8b;
1109 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1113 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1114 emit_rex(0,(reg),(indexreg),(basereg));
1115 *(cd->mcodeptr++) = 0x8b;
1116 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1120 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1121 emit_rex(1,(reg),(indexreg),(basereg));
1122 *(cd->mcodeptr++) = 0x89;
1123 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1127 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1128 emit_rex(0,(reg),(indexreg),(basereg));
1129 *(cd->mcodeptr++) = 0x89;
1130 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1134 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1135 *(cd->mcodeptr++) = 0x66;
1136 emit_rex(0,(reg),(indexreg),(basereg));
1137 *(cd->mcodeptr++) = 0x89;
1138 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1142 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1143 emit_byte_rex((reg),(indexreg),(basereg));
1144 *(cd->mcodeptr++) = 0x88;
1145 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1149 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1150 emit_rex(1,0,0,(basereg));
1151 *(cd->mcodeptr++) = 0xc7;
1152 emit_membase(cd, (basereg),(disp),0);
1157 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1158 emit_rex(1,0,0,(basereg));
1159 *(cd->mcodeptr++) = 0xc7;
1160 emit_membase32(cd, (basereg),(disp),0);
1165 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1166 emit_rex(0,0,0,(basereg));
1167 *(cd->mcodeptr++) = 0xc7;
1168 emit_membase(cd, (basereg),(disp),0);
1173 /* Always emit a REX byte, because the instruction size can be smaller when */
1174 /* all register indexes are smaller than 7. */
1175 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1176 emit_byte_rex(0,0,(basereg));
1177 *(cd->mcodeptr++) = 0xc7;
1178 emit_membase32(cd, (basereg),(disp),0);
1183 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1185 emit_rex(1,(dreg),0,(reg));
1186 *(cd->mcodeptr++) = 0x0f;
1187 *(cd->mcodeptr++) = 0xbe;
1188 /* XXX: why do reg and dreg have to be exchanged */
1189 emit_reg((dreg),(reg));
1193 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1195 emit_rex(1,(dreg),0,(reg));
1196 *(cd->mcodeptr++) = 0x0f;
1197 *(cd->mcodeptr++) = 0xbf;
1198 /* XXX: why do reg and dreg have to be exchanged */
1199 emit_reg((dreg),(reg));
1203 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1205 emit_rex(1,(dreg),0,(reg));
1206 *(cd->mcodeptr++) = 0x63;
1207 /* XXX: why do reg and dreg have to be exchanged */
1208 emit_reg((dreg),(reg));
1212 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1214 emit_rex(1,(dreg),0,(reg));
1215 *(cd->mcodeptr++) = 0x0f;
1216 *(cd->mcodeptr++) = 0xb7;
1217 /* XXX: why do reg and dreg have to be exchanged */
1218 emit_reg((dreg),(reg));
1222 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1223 emit_rex(1,(reg),(indexreg),(basereg));
1224 *(cd->mcodeptr++) = 0x0f;
1225 *(cd->mcodeptr++) = 0xbf;
1226 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1230 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1231 emit_rex(1,(reg),(indexreg),(basereg));
1232 *(cd->mcodeptr++) = 0x0f;
1233 *(cd->mcodeptr++) = 0xbe;
1234 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1238 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1239 emit_rex(1,(reg),(indexreg),(basereg));
1240 *(cd->mcodeptr++) = 0x0f;
1241 *(cd->mcodeptr++) = 0xb7;
1242 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1246 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1248 emit_rex(1,0,(indexreg),(basereg));
1249 *(cd->mcodeptr++) = 0xc7;
1250 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1255 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1257 emit_rex(0,0,(indexreg),(basereg));
1258 *(cd->mcodeptr++) = 0xc7;
1259 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1264 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1266 *(cd->mcodeptr++) = 0x66;
1267 emit_rex(0,0,(indexreg),(basereg));
1268 *(cd->mcodeptr++) = 0xc7;
1269 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1274 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1276 emit_rex(0,0,(indexreg),(basereg));
1277 *(cd->mcodeptr++) = 0xc6;
1278 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1283 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1285 emit_rex(1, dreg, 0, 0);
1286 *(cd->mcodeptr++) = 0x8b;
1287 emit_address_byte(0, dreg, 4);
1295 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1297 emit_rex(1,(reg),0,(dreg));
1298 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1299 emit_reg((reg),(dreg));
1303 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1305 emit_rex(0,(reg),0,(dreg));
1306 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1307 emit_reg((reg),(dreg));
1311 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1313 emit_rex(1,(reg),0,(basereg));
1314 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1315 emit_membase(cd, (basereg),(disp),(reg));
1319 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1321 emit_rex(0,(reg),0,(basereg));
1322 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1323 emit_membase(cd, (basereg),(disp),(reg));
1327 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1329 emit_rex(1,(reg),0,(basereg));
1330 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1331 emit_membase(cd, (basereg),(disp),(reg));
1335 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1337 emit_rex(0,(reg),0,(basereg));
1338 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1339 emit_membase(cd, (basereg),(disp),(reg));
1343 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1345 emit_rex(1,0,0,(dreg));
1346 *(cd->mcodeptr++) = 0x83;
1347 emit_reg((opc),(dreg));
1350 emit_rex(1,0,0,(dreg));
1351 *(cd->mcodeptr++) = 0x81;
1352 emit_reg((opc),(dreg));
1358 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1360 emit_rex(1,0,0,(dreg));
1361 *(cd->mcodeptr++) = 0x81;
1362 emit_reg((opc),(dreg));
1367 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1369 emit_rex(0,0,0,(dreg));
1370 *(cd->mcodeptr++) = 0x81;
1371 emit_reg((opc),(dreg));
1376 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1378 emit_rex(0,0,0,(dreg));
1379 *(cd->mcodeptr++) = 0x83;
1380 emit_reg((opc),(dreg));
1383 emit_rex(0,0,0,(dreg));
1384 *(cd->mcodeptr++) = 0x81;
1385 emit_reg((opc),(dreg));
1391 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1393 emit_rex(1,(basereg),0,0);
1394 *(cd->mcodeptr++) = 0x83;
1395 emit_membase(cd, (basereg),(disp),(opc));
1398 emit_rex(1,(basereg),0,0);
1399 *(cd->mcodeptr++) = 0x81;
1400 emit_membase(cd, (basereg),(disp),(opc));
1406 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1408 emit_rex(0,(basereg),0,0);
1409 *(cd->mcodeptr++) = 0x83;
1410 emit_membase(cd, (basereg),(disp),(opc));
1413 emit_rex(0,(basereg),0,0);
1414 *(cd->mcodeptr++) = 0x81;
1415 emit_membase(cd, (basereg),(disp),(opc));
1421 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1422 emit_rex(1,(reg),0,(dreg));
1423 *(cd->mcodeptr++) = 0x85;
1424 emit_reg((reg),(dreg));
1428 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1429 emit_rex(0,(reg),0,(dreg));
1430 *(cd->mcodeptr++) = 0x85;
1431 emit_reg((reg),(dreg));
1435 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1436 *(cd->mcodeptr++) = 0xf7;
1442 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1443 *(cd->mcodeptr++) = 0x66;
1444 *(cd->mcodeptr++) = 0xf7;
1450 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1451 *(cd->mcodeptr++) = 0xf6;
1457 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1458 emit_rex(1,(reg),0,(basereg));
1459 *(cd->mcodeptr++) = 0x8d;
1460 emit_membase(cd, (basereg),(disp),(reg));
1464 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1465 emit_rex(0,(reg),0,(basereg));
1466 *(cd->mcodeptr++) = 0x8d;
1467 emit_membase(cd, (basereg),(disp),(reg));
1472 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1474 emit_rex(0,0,0,(basereg));
1475 *(cd->mcodeptr++) = 0xff;
1476 emit_membase(cd, (basereg),(disp),0);
1481 void emit_cltd(codegendata *cd) {
1482 *(cd->mcodeptr++) = 0x99;
1486 void emit_cqto(codegendata *cd) {
1488 *(cd->mcodeptr++) = 0x99;
1493 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1494 emit_rex(1,(dreg),0,(reg));
1495 *(cd->mcodeptr++) = 0x0f;
1496 *(cd->mcodeptr++) = 0xaf;
1497 emit_reg((dreg),(reg));
1501 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1502 emit_rex(0,(dreg),0,(reg));
1503 *(cd->mcodeptr++) = 0x0f;
1504 *(cd->mcodeptr++) = 0xaf;
1505 emit_reg((dreg),(reg));
1509 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1510 emit_rex(1,(dreg),0,(basereg));
1511 *(cd->mcodeptr++) = 0x0f;
1512 *(cd->mcodeptr++) = 0xaf;
1513 emit_membase(cd, (basereg),(disp),(dreg));
1517 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1518 emit_rex(0,(dreg),0,(basereg));
1519 *(cd->mcodeptr++) = 0x0f;
1520 *(cd->mcodeptr++) = 0xaf;
1521 emit_membase(cd, (basereg),(disp),(dreg));
1525 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1526 if (IS_IMM8((imm))) {
1527 emit_rex(1,0,0,(dreg));
1528 *(cd->mcodeptr++) = 0x6b;
1532 emit_rex(1,0,0,(dreg));
1533 *(cd->mcodeptr++) = 0x69;
1540 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1541 if (IS_IMM8((imm))) {
1542 emit_rex(1,(dreg),0,(reg));
1543 *(cd->mcodeptr++) = 0x6b;
1544 emit_reg((dreg),(reg));
1547 emit_rex(1,(dreg),0,(reg));
1548 *(cd->mcodeptr++) = 0x69;
1549 emit_reg((dreg),(reg));
1555 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1556 if (IS_IMM8((imm))) {
1557 emit_rex(0,(dreg),0,(reg));
1558 *(cd->mcodeptr++) = 0x6b;
1559 emit_reg((dreg),(reg));
1562 emit_rex(0,(dreg),0,(reg));
1563 *(cd->mcodeptr++) = 0x69;
1564 emit_reg((dreg),(reg));
1570 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1571 if (IS_IMM8((imm))) {
1572 emit_rex(1,(dreg),0,(basereg));
1573 *(cd->mcodeptr++) = 0x6b;
1574 emit_membase(cd, (basereg),(disp),(dreg));
1577 emit_rex(1,(dreg),0,(basereg));
1578 *(cd->mcodeptr++) = 0x69;
1579 emit_membase(cd, (basereg),(disp),(dreg));
1585 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1586 if (IS_IMM8((imm))) {
1587 emit_rex(0,(dreg),0,(basereg));
1588 *(cd->mcodeptr++) = 0x6b;
1589 emit_membase(cd, (basereg),(disp),(dreg));
1592 emit_rex(0,(dreg),0,(basereg));
1593 *(cd->mcodeptr++) = 0x69;
1594 emit_membase(cd, (basereg),(disp),(dreg));
1600 void emit_idiv_reg(codegendata *cd, s8 reg) {
1601 emit_rex(1,0,0,(reg));
1602 *(cd->mcodeptr++) = 0xf7;
1607 void emit_idivl_reg(codegendata *cd, s8 reg) {
1608 emit_rex(0,0,0,(reg));
1609 *(cd->mcodeptr++) = 0xf7;
1615 void emit_ret(codegendata *cd) {
1616 *(cd->mcodeptr++) = 0xc3;
1624 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1625 emit_rex(1,0,0,(reg));
1626 *(cd->mcodeptr++) = 0xd3;
1627 emit_reg((opc),(reg));
1631 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1632 emit_rex(0,0,0,(reg));
1633 *(cd->mcodeptr++) = 0xd3;
1634 emit_reg((opc),(reg));
1638 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1639 emit_rex(1,0,0,(basereg));
1640 *(cd->mcodeptr++) = 0xd3;
1641 emit_membase(cd, (basereg),(disp),(opc));
1645 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1646 emit_rex(0,0,0,(basereg));
1647 *(cd->mcodeptr++) = 0xd3;
1648 emit_membase(cd, (basereg),(disp),(opc));
1652 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1654 emit_rex(1,0,0,(dreg));
1655 *(cd->mcodeptr++) = 0xd1;
1656 emit_reg((opc),(dreg));
1658 emit_rex(1,0,0,(dreg));
1659 *(cd->mcodeptr++) = 0xc1;
1660 emit_reg((opc),(dreg));
1666 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1668 emit_rex(0,0,0,(dreg));
1669 *(cd->mcodeptr++) = 0xd1;
1670 emit_reg((opc),(dreg));
1672 emit_rex(0,0,0,(dreg));
1673 *(cd->mcodeptr++) = 0xc1;
1674 emit_reg((opc),(dreg));
1680 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1682 emit_rex(1,0,0,(basereg));
1683 *(cd->mcodeptr++) = 0xd1;
1684 emit_membase(cd, (basereg),(disp),(opc));
1686 emit_rex(1,0,0,(basereg));
1687 *(cd->mcodeptr++) = 0xc1;
1688 emit_membase(cd, (basereg),(disp),(opc));
1694 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1696 emit_rex(0,0,0,(basereg));
1697 *(cd->mcodeptr++) = 0xd1;
1698 emit_membase(cd, (basereg),(disp),(opc));
1700 emit_rex(0,0,0,(basereg));
1701 *(cd->mcodeptr++) = 0xc1;
1702 emit_membase(cd, (basereg),(disp),(opc));
1712 void emit_jmp_imm(codegendata *cd, s8 imm) {
1713 *(cd->mcodeptr++) = 0xe9;
1718 void emit_jmp_reg(codegendata *cd, s8 reg) {
1719 emit_rex(0,0,0,(reg));
1720 *(cd->mcodeptr++) = 0xff;
1725 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1726 *(cd->mcodeptr++) = 0x0f;
1727 *(cd->mcodeptr++) = (0x80 + (opc));
1734 * conditional set and move operations
1737 /* we need the rex byte to get all low bytes */
1738 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1740 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1741 *(cd->mcodeptr++) = 0x0f;
1742 *(cd->mcodeptr++) = (0x90 + (opc));
1747 /* we need the rex byte to get all low bytes */
1748 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1750 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1751 *(cd->mcodeptr++) = 0x0f;
1752 *(cd->mcodeptr++) = (0x90 + (opc));
1753 emit_membase(cd, (basereg),(disp),0);
1757 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1759 emit_rex(1,(dreg),0,(reg));
1760 *(cd->mcodeptr++) = 0x0f;
1761 *(cd->mcodeptr++) = (0x40 + (opc));
1762 emit_reg((dreg),(reg));
1766 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1768 emit_rex(0,(dreg),0,(reg));
1769 *(cd->mcodeptr++) = 0x0f;
1770 *(cd->mcodeptr++) = (0x40 + (opc));
1771 emit_reg((dreg),(reg));
1775 void emit_neg_reg(codegendata *cd, s8 reg)
1777 emit_rex(1,0,0,(reg));
1778 *(cd->mcodeptr++) = 0xf7;
1783 void emit_negl_reg(codegendata *cd, s8 reg)
1785 emit_rex(0,0,0,(reg));
1786 *(cd->mcodeptr++) = 0xf7;
1791 void emit_push_reg(codegendata *cd, s8 reg) {
1792 emit_rex(0,0,0,(reg));
1793 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1797 void emit_push_imm(codegendata *cd, s8 imm) {
1798 *(cd->mcodeptr++) = 0x68;
1803 void emit_pop_reg(codegendata *cd, s8 reg) {
1804 emit_rex(0,0,0,(reg));
1805 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1809 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1810 emit_rex(1,(reg),0,(dreg));
1811 *(cd->mcodeptr++) = 0x87;
1812 emit_reg((reg),(dreg));
1816 void emit_nop(codegendata *cd) {
1817 *(cd->mcodeptr++) = 0x90;
1825 void emit_call_reg(codegendata *cd, s8 reg)
1827 emit_rex(0,0,0,(reg));
1828 *(cd->mcodeptr++) = 0xff;
1833 void emit_call_imm(codegendata *cd, s8 imm)
1835 *(cd->mcodeptr++) = 0xe8;
1840 void emit_call_mem(codegendata *cd, ptrint mem)
1842 *(cd->mcodeptr++) = 0xff;
1849 * floating point instructions (SSE2)
1851 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1852 *(cd->mcodeptr++) = 0xf2;
1853 emit_rex(0,(dreg),0,(reg));
1854 *(cd->mcodeptr++) = 0x0f;
1855 *(cd->mcodeptr++) = 0x58;
1856 emit_reg((dreg),(reg));
1860 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1861 *(cd->mcodeptr++) = 0xf3;
1862 emit_rex(0,(dreg),0,(reg));
1863 *(cd->mcodeptr++) = 0x0f;
1864 *(cd->mcodeptr++) = 0x58;
1865 emit_reg((dreg),(reg));
1869 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1870 *(cd->mcodeptr++) = 0xf3;
1871 emit_rex(1,(dreg),0,(reg));
1872 *(cd->mcodeptr++) = 0x0f;
1873 *(cd->mcodeptr++) = 0x2a;
1874 emit_reg((dreg),(reg));
1878 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1879 *(cd->mcodeptr++) = 0xf3;
1880 emit_rex(0,(dreg),0,(reg));
1881 *(cd->mcodeptr++) = 0x0f;
1882 *(cd->mcodeptr++) = 0x2a;
1883 emit_reg((dreg),(reg));
1887 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1888 *(cd->mcodeptr++) = 0xf2;
1889 emit_rex(1,(dreg),0,(reg));
1890 *(cd->mcodeptr++) = 0x0f;
1891 *(cd->mcodeptr++) = 0x2a;
1892 emit_reg((dreg),(reg));
1896 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1897 *(cd->mcodeptr++) = 0xf2;
1898 emit_rex(0,(dreg),0,(reg));
1899 *(cd->mcodeptr++) = 0x0f;
1900 *(cd->mcodeptr++) = 0x2a;
1901 emit_reg((dreg),(reg));
1905 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1906 *(cd->mcodeptr++) = 0xf3;
1907 emit_rex(0,(dreg),0,(reg));
1908 *(cd->mcodeptr++) = 0x0f;
1909 *(cd->mcodeptr++) = 0x5a;
1910 emit_reg((dreg),(reg));
1914 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1915 *(cd->mcodeptr++) = 0xf2;
1916 emit_rex(0,(dreg),0,(reg));
1917 *(cd->mcodeptr++) = 0x0f;
1918 *(cd->mcodeptr++) = 0x5a;
1919 emit_reg((dreg),(reg));
1923 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1924 *(cd->mcodeptr++) = 0xf3;
1925 emit_rex(1,(dreg),0,(reg));
1926 *(cd->mcodeptr++) = 0x0f;
1927 *(cd->mcodeptr++) = 0x2c;
1928 emit_reg((dreg),(reg));
1932 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1933 *(cd->mcodeptr++) = 0xf3;
1934 emit_rex(0,(dreg),0,(reg));
1935 *(cd->mcodeptr++) = 0x0f;
1936 *(cd->mcodeptr++) = 0x2c;
1937 emit_reg((dreg),(reg));
1941 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1942 *(cd->mcodeptr++) = 0xf2;
1943 emit_rex(1,(dreg),0,(reg));
1944 *(cd->mcodeptr++) = 0x0f;
1945 *(cd->mcodeptr++) = 0x2c;
1946 emit_reg((dreg),(reg));
1950 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1951 *(cd->mcodeptr++) = 0xf2;
1952 emit_rex(0,(dreg),0,(reg));
1953 *(cd->mcodeptr++) = 0x0f;
1954 *(cd->mcodeptr++) = 0x2c;
1955 emit_reg((dreg),(reg));
1959 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1960 *(cd->mcodeptr++) = 0xf3;
1961 emit_rex(0,(dreg),0,(reg));
1962 *(cd->mcodeptr++) = 0x0f;
1963 *(cd->mcodeptr++) = 0x5e;
1964 emit_reg((dreg),(reg));
1968 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1969 *(cd->mcodeptr++) = 0xf2;
1970 emit_rex(0,(dreg),0,(reg));
1971 *(cd->mcodeptr++) = 0x0f;
1972 *(cd->mcodeptr++) = 0x5e;
1973 emit_reg((dreg),(reg));
1977 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1978 *(cd->mcodeptr++) = 0x66;
1979 emit_rex(1,(freg),0,(reg));
1980 *(cd->mcodeptr++) = 0x0f;
1981 *(cd->mcodeptr++) = 0x6e;
1982 emit_reg((freg),(reg));
1986 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1987 *(cd->mcodeptr++) = 0x66;
1988 emit_rex(1,(freg),0,(reg));
1989 *(cd->mcodeptr++) = 0x0f;
1990 *(cd->mcodeptr++) = 0x7e;
1991 emit_reg((freg),(reg));
1995 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1996 *(cd->mcodeptr++) = 0x66;
1997 emit_rex(0,(reg),0,(basereg));
1998 *(cd->mcodeptr++) = 0x0f;
1999 *(cd->mcodeptr++) = 0x7e;
2000 emit_membase(cd, (basereg),(disp),(reg));
2004 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2005 *(cd->mcodeptr++) = 0x66;
2006 emit_rex(0,(reg),(indexreg),(basereg));
2007 *(cd->mcodeptr++) = 0x0f;
2008 *(cd->mcodeptr++) = 0x7e;
2009 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2013 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2014 *(cd->mcodeptr++) = 0x66;
2015 emit_rex(1,(dreg),0,(basereg));
2016 *(cd->mcodeptr++) = 0x0f;
2017 *(cd->mcodeptr++) = 0x6e;
2018 emit_membase(cd, (basereg),(disp),(dreg));
2022 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2023 *(cd->mcodeptr++) = 0x66;
2024 emit_rex(0,(dreg),0,(basereg));
2025 *(cd->mcodeptr++) = 0x0f;
2026 *(cd->mcodeptr++) = 0x6e;
2027 emit_membase(cd, (basereg),(disp),(dreg));
2031 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2032 *(cd->mcodeptr++) = 0x66;
2033 emit_rex(0,(dreg),(indexreg),(basereg));
2034 *(cd->mcodeptr++) = 0x0f;
2035 *(cd->mcodeptr++) = 0x6e;
2036 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2040 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2041 *(cd->mcodeptr++) = 0xf3;
2042 emit_rex(0,(dreg),0,(reg));
2043 *(cd->mcodeptr++) = 0x0f;
2044 *(cd->mcodeptr++) = 0x7e;
2045 emit_reg((dreg),(reg));
2049 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2050 *(cd->mcodeptr++) = 0x66;
2051 emit_rex(0,(reg),0,(basereg));
2052 *(cd->mcodeptr++) = 0x0f;
2053 *(cd->mcodeptr++) = 0xd6;
2054 emit_membase(cd, (basereg),(disp),(reg));
2058 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2059 *(cd->mcodeptr++) = 0xf3;
2060 emit_rex(0,(dreg),0,(basereg));
2061 *(cd->mcodeptr++) = 0x0f;
2062 *(cd->mcodeptr++) = 0x7e;
2063 emit_membase(cd, (basereg),(disp),(dreg));
2067 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2068 *(cd->mcodeptr++) = 0xf3;
2069 emit_rex(0,(reg),0,(dreg));
2070 *(cd->mcodeptr++) = 0x0f;
2071 *(cd->mcodeptr++) = 0x10;
2072 emit_reg((reg),(dreg));
2076 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2077 *(cd->mcodeptr++) = 0xf2;
2078 emit_rex(0,(reg),0,(dreg));
2079 *(cd->mcodeptr++) = 0x0f;
2080 *(cd->mcodeptr++) = 0x10;
2081 emit_reg((reg),(dreg));
2085 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2086 *(cd->mcodeptr++) = 0xf3;
2087 emit_rex(0,(reg),0,(basereg));
2088 *(cd->mcodeptr++) = 0x0f;
2089 *(cd->mcodeptr++) = 0x11;
2090 emit_membase(cd, (basereg),(disp),(reg));
2094 /* Always emit a REX byte, because the instruction size can be smaller when */
2095 /* all register indexes are smaller than 7. */
2096 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2097 *(cd->mcodeptr++) = 0xf3;
2098 emit_byte_rex((reg),0,(basereg));
2099 *(cd->mcodeptr++) = 0x0f;
2100 *(cd->mcodeptr++) = 0x11;
2101 emit_membase32(cd, (basereg),(disp),(reg));
2105 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2106 *(cd->mcodeptr++) = 0xf2;
2107 emit_rex(0,(reg),0,(basereg));
2108 *(cd->mcodeptr++) = 0x0f;
2109 *(cd->mcodeptr++) = 0x11;
2110 emit_membase(cd, (basereg),(disp),(reg));
2114 /* Always emit a REX byte, because the instruction size can be smaller when */
2115 /* all register indexes are smaller than 7. */
2116 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2117 *(cd->mcodeptr++) = 0xf2;
2118 emit_byte_rex((reg),0,(basereg));
2119 *(cd->mcodeptr++) = 0x0f;
2120 *(cd->mcodeptr++) = 0x11;
2121 emit_membase32(cd, (basereg),(disp),(reg));
2125 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2126 *(cd->mcodeptr++) = 0xf3;
2127 emit_rex(0,(dreg),0,(basereg));
2128 *(cd->mcodeptr++) = 0x0f;
2129 *(cd->mcodeptr++) = 0x10;
2130 emit_membase(cd, (basereg),(disp),(dreg));
2134 /* Always emit a REX byte, because the instruction size can be smaller when */
2135 /* all register indexes are smaller than 7. */
2136 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2137 *(cd->mcodeptr++) = 0xf3;
2138 emit_byte_rex((dreg),0,(basereg));
2139 *(cd->mcodeptr++) = 0x0f;
2140 *(cd->mcodeptr++) = 0x10;
2141 emit_membase32(cd, (basereg),(disp),(dreg));
2145 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2147 emit_rex(0,(dreg),0,(basereg));
2148 *(cd->mcodeptr++) = 0x0f;
2149 *(cd->mcodeptr++) = 0x12;
2150 emit_membase(cd, (basereg),(disp),(dreg));
2154 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2156 emit_rex(0,(reg),0,(basereg));
2157 *(cd->mcodeptr++) = 0x0f;
2158 *(cd->mcodeptr++) = 0x13;
2159 emit_membase(cd, (basereg),(disp),(reg));
2163 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2164 *(cd->mcodeptr++) = 0xf2;
2165 emit_rex(0,(dreg),0,(basereg));
2166 *(cd->mcodeptr++) = 0x0f;
2167 *(cd->mcodeptr++) = 0x10;
2168 emit_membase(cd, (basereg),(disp),(dreg));
2172 /* Always emit a REX byte, because the instruction size can be smaller when */
2173 /* all register indexes are smaller than 7. */
2174 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2175 *(cd->mcodeptr++) = 0xf2;
2176 emit_byte_rex((dreg),0,(basereg));
2177 *(cd->mcodeptr++) = 0x0f;
2178 *(cd->mcodeptr++) = 0x10;
2179 emit_membase32(cd, (basereg),(disp),(dreg));
2183 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2185 *(cd->mcodeptr++) = 0x66;
2186 emit_rex(0,(dreg),0,(basereg));
2187 *(cd->mcodeptr++) = 0x0f;
2188 *(cd->mcodeptr++) = 0x12;
2189 emit_membase(cd, (basereg),(disp),(dreg));
2193 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2195 *(cd->mcodeptr++) = 0x66;
2196 emit_rex(0,(reg),0,(basereg));
2197 *(cd->mcodeptr++) = 0x0f;
2198 *(cd->mcodeptr++) = 0x13;
2199 emit_membase(cd, (basereg),(disp),(reg));
2203 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2204 *(cd->mcodeptr++) = 0xf3;
2205 emit_rex(0,(reg),(indexreg),(basereg));
2206 *(cd->mcodeptr++) = 0x0f;
2207 *(cd->mcodeptr++) = 0x11;
2208 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2212 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2213 *(cd->mcodeptr++) = 0xf2;
2214 emit_rex(0,(reg),(indexreg),(basereg));
2215 *(cd->mcodeptr++) = 0x0f;
2216 *(cd->mcodeptr++) = 0x11;
2217 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2221 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2222 *(cd->mcodeptr++) = 0xf3;
2223 emit_rex(0,(dreg),(indexreg),(basereg));
2224 *(cd->mcodeptr++) = 0x0f;
2225 *(cd->mcodeptr++) = 0x10;
2226 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2230 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2231 *(cd->mcodeptr++) = 0xf2;
2232 emit_rex(0,(dreg),(indexreg),(basereg));
2233 *(cd->mcodeptr++) = 0x0f;
2234 *(cd->mcodeptr++) = 0x10;
2235 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2239 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2240 *(cd->mcodeptr++) = 0xf3;
2241 emit_rex(0,(dreg),0,(reg));
2242 *(cd->mcodeptr++) = 0x0f;
2243 *(cd->mcodeptr++) = 0x59;
2244 emit_reg((dreg),(reg));
2248 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2249 *(cd->mcodeptr++) = 0xf2;
2250 emit_rex(0,(dreg),0,(reg));
2251 *(cd->mcodeptr++) = 0x0f;
2252 *(cd->mcodeptr++) = 0x59;
2253 emit_reg((dreg),(reg));
2257 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2258 *(cd->mcodeptr++) = 0xf3;
2259 emit_rex(0,(dreg),0,(reg));
2260 *(cd->mcodeptr++) = 0x0f;
2261 *(cd->mcodeptr++) = 0x5c;
2262 emit_reg((dreg),(reg));
2266 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2267 *(cd->mcodeptr++) = 0xf2;
2268 emit_rex(0,(dreg),0,(reg));
2269 *(cd->mcodeptr++) = 0x0f;
2270 *(cd->mcodeptr++) = 0x5c;
2271 emit_reg((dreg),(reg));
2275 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2276 emit_rex(0,(dreg),0,(reg));
2277 *(cd->mcodeptr++) = 0x0f;
2278 *(cd->mcodeptr++) = 0x2e;
2279 emit_reg((dreg),(reg));
2283 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2284 *(cd->mcodeptr++) = 0x66;
2285 emit_rex(0,(dreg),0,(reg));
2286 *(cd->mcodeptr++) = 0x0f;
2287 *(cd->mcodeptr++) = 0x2e;
2288 emit_reg((dreg),(reg));
2292 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2293 emit_rex(0,(dreg),0,(reg));
2294 *(cd->mcodeptr++) = 0x0f;
2295 *(cd->mcodeptr++) = 0x57;
2296 emit_reg((dreg),(reg));
2300 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2301 emit_rex(0,(dreg),0,(basereg));
2302 *(cd->mcodeptr++) = 0x0f;
2303 *(cd->mcodeptr++) = 0x57;
2304 emit_membase(cd, (basereg),(disp),(dreg));
2308 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2309 *(cd->mcodeptr++) = 0x66;
2310 emit_rex(0,(dreg),0,(reg));
2311 *(cd->mcodeptr++) = 0x0f;
2312 *(cd->mcodeptr++) = 0x57;
2313 emit_reg((dreg),(reg));
2317 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2318 *(cd->mcodeptr++) = 0x66;
2319 emit_rex(0,(dreg),0,(basereg));
2320 *(cd->mcodeptr++) = 0x0f;
2321 *(cd->mcodeptr++) = 0x57;
2322 emit_membase(cd, (basereg),(disp),(dreg));
2326 /* system instructions ********************************************************/
2328 void emit_rdtsc(codegendata *cd)
2330 *(cd->mcodeptr++) = 0x0f;
2331 *(cd->mcodeptr++) = 0x31;
2336 * These are local overrides for various environment variables in Emacs.
2337 * Please do not remove this and leave it at the end of the file, where
2338 * Emacs will automagically detect them.
2339 * ---------------------------------------------------------------------
2342 * indent-tabs-mode: t