1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 7449 2007-03-04 18:07:55Z twisti $
37 #include "vm/jit/x86_64/codegen.h"
38 #include "vm/jit/x86_64/emit.h"
40 #include "mm/memory.h"
42 #if defined(ENABLE_THREADS)
43 # include "threads/native/lock.h"
46 #include "vm/builtin.h"
48 #include "vm/jit/abi-asm.h"
49 #include "vm/jit/asmpart.h"
50 #include "vm/jit/codegen-common.h"
51 #include "vm/jit/emit-common.h"
52 #include "vm/jit/jit.h"
53 #include "vm/jit/replace.h"
55 #include "vmcore/options.h"
58 /* emit_load *******************************************************************
60 Emits a possible load of an operand.
62 *******************************************************************************/
64 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
70 /* get required compiler data */
74 if (IS_INMEMORY(src->flags)) {
77 disp = src->vv.regoff * 8;
81 M_ILD(tempreg, REG_SP, disp);
85 M_LLD(tempreg, REG_SP, disp);
88 M_FLD(tempreg, REG_SP, disp);
91 M_DLD(tempreg, REG_SP, disp);
94 vm_abort("emit_load: unknown type %d", src->type);
100 reg = src->vv.regoff;
106 /* emit_store ******************************************************************
108 This function generates the code to store the result of an
109 operation back into a spilled pseudo-variable. If the
110 pseudo-variable has not been spilled in the first place, this
111 function will generate nothing.
113 *******************************************************************************/
115 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
124 /* get required compiler data */
129 /* do we have to generate a conditional move? */
131 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
132 /* the passed register d is actually the source register */
136 /* Only pass the opcode to codegen_reg_of_var to get the real
137 destination register. */
139 opcode = iptr->opc & ICMD_OPCODE_MASK;
141 /* get the real destination register */
143 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
145 /* and emit the conditional move */
147 emit_cmovxx(cd, iptr, s, d);
151 if (IS_INMEMORY(dst->flags)) {
154 disp = dst->vv.regoff * 8;
160 M_LST(d, REG_SP, disp);
163 M_FST(d, REG_SP, disp);
166 M_DST(d, REG_SP, disp);
169 vm_abort("emit_store: unknown type %d", dst->type);
175 /* emit_copy *******************************************************************
177 Generates a register/memory to register/memory copy.
179 *******************************************************************************/
181 void emit_copy(jitdata *jd, instruction *iptr, varinfo *src, varinfo *dst)
186 /* get required compiler data */
190 if ((src->vv.regoff != dst->vv.regoff) ||
191 ((src->flags ^ dst->flags) & INMEMORY)) {
193 /* If one of the variables resides in memory, we can eliminate
194 the register move from/to the temporary register with the
195 order of getting the destination register and the load. */
197 if (IS_INMEMORY(src->flags)) {
198 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
199 s1 = emit_load(jd, iptr, src, d);
202 s1 = emit_load(jd, iptr, src, REG_IFTMP);
203 d = codegen_reg_of_var(iptr->opc, dst, s1);
218 vm_abort("emit_copy: unknown type %d", src->type);
222 emit_store(jd, iptr, dst, d);
227 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
230 switch (iptr->flags.fields.condition) {
254 /* emit_arithmetic_check *******************************************************
256 Emit an ArithmeticException check.
258 *******************************************************************************/
260 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
262 if (INSTRUCTION_MUST_CHECK(iptr)) {
265 codegen_add_arithmeticexception_ref(cd);
270 /* emit_arrayindexoutofbounds_check ********************************************
272 Emit a ArrayIndexOutOfBoundsException check.
274 *******************************************************************************/
276 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
278 if (INSTRUCTION_MUST_CHECK(iptr)) {
279 M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));
280 M_ICMP(REG_ITMP3, s2);
282 codegen_add_arrayindexoutofboundsexception_ref(cd, s2);
287 /* emit_classcast_check ********************************************************
289 Emit a ClassCastException check.
291 *******************************************************************************/
293 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
295 vm_abort("IMPLEMENT ME!");
299 /* emit_nullpointer_check ******************************************************
301 Emit a NullPointerException check.
303 *******************************************************************************/
305 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
307 if (INSTRUCTION_MUST_CHECK(iptr)) {
310 codegen_add_nullpointerexception_ref(cd);
315 /* emit_exception_stubs ********************************************************
317 Generates the code for the exception stubs.
319 *******************************************************************************/
321 void emit_exception_stubs(jitdata *jd)
330 /* get required compiler data */
335 /* generate exception stubs */
339 for (er = cd->exceptionrefs; er != NULL; er = er->next) {
340 /* back-patch the branch to this exception code */
342 branchmpc = er->branchpos;
343 targetmpc = cd->mcodeptr - cd->mcodebase;
345 md_codegen_patch_branch(cd, branchmpc, targetmpc);
349 /* Check if the exception is an
350 ArrayIndexOutOfBoundsException. If so, move index register
354 M_MOV(er->reg, rd->argintregs[4]);
356 /* calcuate exception address */
358 M_MOV_IMM(0, rd->argintregs[3]);
360 M_AADD_IMM32(er->branchpos - 6, rd->argintregs[3]);
362 /* move function to call into REG_ITMP3 */
364 M_MOV_IMM(er->function, REG_ITMP3);
366 if (targetdisp == 0) {
367 targetdisp = cd->mcodeptr - cd->mcodebase;
369 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase), rd->argintregs[0]);
370 M_MOV(REG_SP, rd->argintregs[1]);
371 M_ALD(rd->argintregs[2], REG_SP, cd->stackframesize * 8);
373 M_ASUB_IMM(2 * 8, REG_SP);
374 M_AST(rd->argintregs[3], REG_SP, 0 * 8); /* store XPC */
378 M_ALD(REG_ITMP2_XPC, REG_SP, 0 * 8);
379 M_AADD_IMM(2 * 8, REG_SP);
381 M_MOV_IMM(asm_handle_exception, REG_ITMP3);
385 M_JMP_IMM((cd->mcodebase + targetdisp) -
386 (cd->mcodeptr + PATCHER_CALL_SIZE));
392 /* emit_patcher_stubs **********************************************************
394 Generates the code for the patcher stubs.
396 *******************************************************************************/
398 void emit_patcher_stubs(jitdata *jd)
408 /* get required compiler data */
412 /* generate code patching stub call code */
416 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
417 /* check size of code segment */
421 /* Get machine code which is patched back in later. A
422 `call rel32' is 5 bytes long (but read 8 bytes). */
424 savedmcodeptr = cd->mcodebase + pref->branchpos;
425 mcode = *((u8 *) savedmcodeptr);
427 /* patch in `call rel32' to call the following code */
429 tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
430 cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
432 M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE));
434 cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
436 /* move pointer to java_objectheader onto stack */
438 #if defined(ENABLE_THREADS)
439 /* create a virtual java_objectheader */
441 (void) dseg_add_unique_address(cd, NULL); /* flcword */
442 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
443 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
445 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase) + disp, REG_ITMP3);
451 /* move machine code bytes and classinfo pointer into registers */
453 M_MOV_IMM(mcode, REG_ITMP3);
456 M_MOV_IMM(pref->ref, REG_ITMP3);
459 M_MOV_IMM(pref->disp, REG_ITMP3);
462 M_MOV_IMM(pref->patcher, REG_ITMP3);
465 if (targetdisp == 0) {
466 targetdisp = cd->mcodeptr - cd->mcodebase;
468 M_MOV_IMM(asm_patcher_wrapper, REG_ITMP3);
472 M_JMP_IMM((cd->mcodebase + targetdisp) -
473 (cd->mcodeptr + PATCHER_CALL_SIZE));
479 /* emit_replacement_stubs ******************************************************
481 Generates the code for the replacement stubs.
483 *******************************************************************************/
485 #if defined(ENABLE_REPLACEMENT)
486 void emit_replacement_stubs(jitdata *jd)
497 /* get required compiler data */
502 rplp = code->rplpoints;
504 /* store beginning of replacement stubs */
506 code->replacementstubs = (u1*) (cd->mcodeptr - cd->mcodebase);
508 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
509 /* do not generate stubs for non-trappable points */
511 if (rplp->flags & RPLPOINT_FLAG_NOTRAP)
514 /* check code segment size */
518 /* note start of stub code */
521 savedmcodeptr = cd->mcodeptr;
524 /* push address of `rplpoint` struct */
526 M_MOV_IMM(rplp, REG_ITMP3);
529 /* jump to replacement function */
531 M_MOV_IMM(asm_replacement_out, REG_ITMP3);
535 assert((cd->mcodeptr - savedmcodeptr) == REPLACEMENT_STUB_SIZE);
538 #endif /* defined(ENABLE_REPLACEMENT) */
541 /* emit_verbosecall_enter ******************************************************
543 Generates the code for the call trace.
545 *******************************************************************************/
548 void emit_verbosecall_enter(jitdata *jd)
556 /* get required compiler data */
564 /* mark trace code */
568 /* additional +1 is for 16-byte stack alignment */
570 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
572 /* save argument registers */
574 for (i = 0; i < INT_ARG_CNT; i++)
575 M_LST(rd->argintregs[i], REG_SP, (1 + i) * 8);
577 for (i = 0; i < FLT_ARG_CNT; i++)
578 M_DST(rd->argfltregs[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
580 /* save temporary registers for leaf methods */
582 if (jd->isleafmethod) {
583 for (i = 0; i < INT_TMP_CNT; i++)
584 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
586 for (i = 0; i < FLT_TMP_CNT; i++)
587 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
590 /* show integer hex code for float arguments */
592 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
593 /* If the paramtype is a float, we have to right shift all
594 following integer registers. */
596 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
597 for (k = INT_ARG_CNT - 2; k >= i; k--)
598 M_MOV(rd->argintregs[k], rd->argintregs[k + 1]);
600 emit_movd_freg_reg(cd, rd->argfltregs[j], rd->argintregs[i]);
605 M_MOV_IMM(m, REG_ITMP2);
606 M_AST(REG_ITMP2, REG_SP, 0 * 8);
607 M_MOV_IMM(builtin_verbosecall_enter, REG_ITMP1);
610 /* restore argument registers */
612 for (i = 0; i < INT_ARG_CNT; i++)
613 M_LLD(rd->argintregs[i], REG_SP, (1 + i) * 8);
615 for (i = 0; i < FLT_ARG_CNT; i++)
616 M_DLD(rd->argfltregs[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
618 /* restore temporary registers for leaf methods */
620 if (jd->isleafmethod) {
621 for (i = 0; i < INT_TMP_CNT; i++)
622 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
624 for (i = 0; i < FLT_TMP_CNT; i++)
625 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
628 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
630 /* mark trace code */
634 #endif /* !defined(NDEBUG) */
637 /* emit_verbosecall_exit *******************************************************
639 Generates the code for the call trace.
641 *******************************************************************************/
644 void emit_verbosecall_exit(jitdata *jd)
650 /* get required compiler data */
656 /* mark trace code */
660 M_ASUB_IMM(2 * 8, REG_SP);
662 M_LST(REG_RESULT, REG_SP, 0 * 8);
663 M_DST(REG_FRESULT, REG_SP, 1 * 8);
665 M_INTMOVE(REG_RESULT, REG_A0);
666 M_FLTMOVE(REG_FRESULT, REG_FA0);
667 M_FLTMOVE(REG_FRESULT, REG_FA1);
668 M_MOV_IMM(m, REG_A1);
670 M_MOV_IMM(builtin_verbosecall_exit, REG_ITMP1);
673 M_LLD(REG_RESULT, REG_SP, 0 * 8);
674 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
676 M_AADD_IMM(2 * 8, REG_SP);
678 /* mark trace code */
682 #endif /* !defined(NDEBUG) */
685 /* code generation functions **************************************************/
687 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
689 if ((basereg == REG_SP) || (basereg == R12)) {
691 emit_address_byte(0, dreg, REG_SP);
692 emit_address_byte(0, REG_SP, REG_SP);
694 } else if (IS_IMM8(disp)) {
695 emit_address_byte(1, dreg, REG_SP);
696 emit_address_byte(0, REG_SP, REG_SP);
700 emit_address_byte(2, dreg, REG_SP);
701 emit_address_byte(0, REG_SP, REG_SP);
705 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
706 emit_address_byte(0,(dreg),(basereg));
708 } else if ((basereg) == RIP) {
709 emit_address_byte(0, dreg, RBP);
714 emit_address_byte(1, dreg, basereg);
718 emit_address_byte(2, dreg, basereg);
725 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
727 if ((basereg == REG_SP) || (basereg == R12)) {
728 emit_address_byte(2, dreg, REG_SP);
729 emit_address_byte(0, REG_SP, REG_SP);
733 emit_address_byte(2, dreg, basereg);
739 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
742 emit_address_byte(0, reg, 4);
743 emit_address_byte(scale, indexreg, 5);
746 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
747 emit_address_byte(0, reg, 4);
748 emit_address_byte(scale, indexreg, basereg);
750 else if (IS_IMM8(disp)) {
751 emit_address_byte(1, reg, 4);
752 emit_address_byte(scale, indexreg, basereg);
756 emit_address_byte(2, reg, 4);
757 emit_address_byte(scale, indexreg, basereg);
763 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
766 varinfo *v_s1,*v_s2,*v_dst;
769 /* get required compiler data */
773 v_s1 = VAROP(iptr->s1);
774 v_s2 = VAROP(iptr->sx.s23.s2);
775 v_dst = VAROP(iptr->dst);
777 s1 = v_s1->vv.regoff;
778 s2 = v_s2->vv.regoff;
779 d = v_dst->vv.regoff;
781 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
783 if (IS_INMEMORY(v_dst->flags)) {
784 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
786 M_ILD(RCX, REG_SP, s2 * 8);
787 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
790 M_ILD(RCX, REG_SP, s2 * 8);
791 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
792 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
793 M_IST(REG_ITMP2, REG_SP, d * 8);
796 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
797 /* s1 may be equal to RCX */
800 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
801 M_IST(s1, REG_SP, d * 8);
802 M_INTMOVE(REG_ITMP1, RCX);
805 M_IST(s1, REG_SP, d * 8);
806 M_ILD(RCX, REG_SP, s2 * 8);
810 M_ILD(RCX, REG_SP, s2 * 8);
811 M_IST(s1, REG_SP, d * 8);
814 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
816 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
819 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
823 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
824 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
825 M_IST(REG_ITMP2, REG_SP, d * 8);
829 /* s1 may be equal to RCX */
830 M_IST(s1, REG_SP, d * 8);
832 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
835 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
843 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
844 M_ILD(RCX, REG_SP, s2 * 8);
845 M_ILD(d, REG_SP, s1 * 8);
846 emit_shiftl_reg(cd, shift_op, d);
848 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
849 /* s1 may be equal to RCX */
851 M_ILD(RCX, REG_SP, s2 * 8);
852 emit_shiftl_reg(cd, shift_op, d);
854 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
856 M_ILD(d, REG_SP, s1 * 8);
857 emit_shiftl_reg(cd, shift_op, d);
860 /* s1 may be equal to RCX */
863 /* d cannot be used to backup s1 since this would
865 M_INTMOVE(s1, REG_ITMP3);
867 M_INTMOVE(REG_ITMP3, d);
875 /* d may be equal to s2 */
879 emit_shiftl_reg(cd, shift_op, d);
883 M_INTMOVE(REG_ITMP3, RCX);
885 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
890 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
893 varinfo *v_s1,*v_s2,*v_dst;
896 /* get required compiler data */
900 v_s1 = VAROP(iptr->s1);
901 v_s2 = VAROP(iptr->sx.s23.s2);
902 v_dst = VAROP(iptr->dst);
904 s1 = v_s1->vv.regoff;
905 s2 = v_s2->vv.regoff;
906 d = v_dst->vv.regoff;
908 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
910 if (IS_INMEMORY(v_dst->flags)) {
911 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
913 M_ILD(RCX, REG_SP, s2 * 8);
914 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
917 M_ILD(RCX, REG_SP, s2 * 8);
918 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
919 emit_shift_reg(cd, shift_op, REG_ITMP2);
920 M_LST(REG_ITMP2, REG_SP, d * 8);
923 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
924 /* s1 may be equal to RCX */
927 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
928 M_LST(s1, REG_SP, d * 8);
929 M_INTMOVE(REG_ITMP1, RCX);
932 M_LST(s1, REG_SP, d * 8);
933 M_ILD(RCX, REG_SP, s2 * 8);
937 M_ILD(RCX, REG_SP, s2 * 8);
938 M_LST(s1, REG_SP, d * 8);
941 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
943 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
946 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
950 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
951 emit_shift_reg(cd, shift_op, REG_ITMP2);
952 M_LST(REG_ITMP2, REG_SP, d * 8);
956 /* s1 may be equal to RCX */
957 M_LST(s1, REG_SP, d * 8);
959 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
962 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
970 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
971 M_ILD(RCX, REG_SP, s2 * 8);
972 M_LLD(d, REG_SP, s1 * 8);
973 emit_shift_reg(cd, shift_op, d);
975 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
976 /* s1 may be equal to RCX */
978 M_ILD(RCX, REG_SP, s2 * 8);
979 emit_shift_reg(cd, shift_op, d);
981 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
983 M_LLD(d, REG_SP, s1 * 8);
984 emit_shift_reg(cd, shift_op, d);
987 /* s1 may be equal to RCX */
990 /* d cannot be used to backup s1 since this would
992 M_INTMOVE(s1, REG_ITMP3);
994 M_INTMOVE(REG_ITMP3, d);
1002 /* d may be equal to s2 */
1006 emit_shift_reg(cd, shift_op, d);
1010 M_INTMOVE(REG_ITMP3, RCX);
1012 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1017 /* low-level code emitter functions *******************************************/
1019 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1021 emit_rex(1,(reg),0,(dreg));
1022 *(cd->mcodeptr++) = 0x89;
1023 emit_reg((reg),(dreg));
1027 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1029 emit_rex(1,0,0,(reg));
1030 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1035 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1037 emit_rex(0,(reg),0,(dreg));
1038 *(cd->mcodeptr++) = 0x89;
1039 emit_reg((reg),(dreg));
1043 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1044 emit_rex(0,0,0,(reg));
1045 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1050 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1051 emit_rex(1,(reg),0,(basereg));
1052 *(cd->mcodeptr++) = 0x8b;
1053 emit_membase(cd, (basereg),(disp),(reg));
1058 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1059 * constant membase immediate length of 32bit
1061 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1062 emit_rex(1,(reg),0,(basereg));
1063 *(cd->mcodeptr++) = 0x8b;
1064 emit_membase32(cd, (basereg),(disp),(reg));
1068 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1070 emit_rex(0,(reg),0,(basereg));
1071 *(cd->mcodeptr++) = 0x8b;
1072 emit_membase(cd, (basereg),(disp),(reg));
1076 /* ATTENTION: Always emit a REX byte, because the instruction size can
1077 be smaller when all register indexes are smaller than 7. */
1078 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1080 emit_byte_rex((reg),0,(basereg));
1081 *(cd->mcodeptr++) = 0x8b;
1082 emit_membase32(cd, (basereg),(disp),(reg));
1086 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1087 emit_rex(1,(reg),0,(basereg));
1088 *(cd->mcodeptr++) = 0x89;
1089 emit_membase(cd, (basereg),(disp),(reg));
1093 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1094 emit_rex(1,(reg),0,(basereg));
1095 *(cd->mcodeptr++) = 0x89;
1096 emit_membase32(cd, (basereg),(disp),(reg));
1100 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1101 emit_rex(0,(reg),0,(basereg));
1102 *(cd->mcodeptr++) = 0x89;
1103 emit_membase(cd, (basereg),(disp),(reg));
1107 /* Always emit a REX byte, because the instruction size can be smaller when */
1108 /* all register indexes are smaller than 7. */
1109 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1110 emit_byte_rex((reg),0,(basereg));
1111 *(cd->mcodeptr++) = 0x89;
1112 emit_membase32(cd, (basereg),(disp),(reg));
1116 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1117 emit_rex(1,(reg),(indexreg),(basereg));
1118 *(cd->mcodeptr++) = 0x8b;
1119 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1123 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1124 emit_rex(0,(reg),(indexreg),(basereg));
1125 *(cd->mcodeptr++) = 0x8b;
1126 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1130 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1131 emit_rex(1,(reg),(indexreg),(basereg));
1132 *(cd->mcodeptr++) = 0x89;
1133 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1137 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1138 emit_rex(0,(reg),(indexreg),(basereg));
1139 *(cd->mcodeptr++) = 0x89;
1140 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1144 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1145 *(cd->mcodeptr++) = 0x66;
1146 emit_rex(0,(reg),(indexreg),(basereg));
1147 *(cd->mcodeptr++) = 0x89;
1148 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1152 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1153 emit_byte_rex((reg),(indexreg),(basereg));
1154 *(cd->mcodeptr++) = 0x88;
1155 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1159 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1160 emit_rex(1,0,0,(basereg));
1161 *(cd->mcodeptr++) = 0xc7;
1162 emit_membase(cd, (basereg),(disp),0);
1167 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1168 emit_rex(1,0,0,(basereg));
1169 *(cd->mcodeptr++) = 0xc7;
1170 emit_membase32(cd, (basereg),(disp),0);
1175 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1176 emit_rex(0,0,0,(basereg));
1177 *(cd->mcodeptr++) = 0xc7;
1178 emit_membase(cd, (basereg),(disp),0);
1183 /* Always emit a REX byte, because the instruction size can be smaller when */
1184 /* all register indexes are smaller than 7. */
1185 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1186 emit_byte_rex(0,0,(basereg));
1187 *(cd->mcodeptr++) = 0xc7;
1188 emit_membase32(cd, (basereg),(disp),0);
1193 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1195 emit_rex(1,(dreg),0,(reg));
1196 *(cd->mcodeptr++) = 0x0f;
1197 *(cd->mcodeptr++) = 0xbe;
1198 /* XXX: why do reg and dreg have to be exchanged */
1199 emit_reg((dreg),(reg));
1203 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1205 emit_rex(1,(dreg),0,(reg));
1206 *(cd->mcodeptr++) = 0x0f;
1207 *(cd->mcodeptr++) = 0xbf;
1208 /* XXX: why do reg and dreg have to be exchanged */
1209 emit_reg((dreg),(reg));
1213 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1215 emit_rex(1,(dreg),0,(reg));
1216 *(cd->mcodeptr++) = 0x63;
1217 /* XXX: why do reg and dreg have to be exchanged */
1218 emit_reg((dreg),(reg));
1222 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1224 emit_rex(1,(dreg),0,(reg));
1225 *(cd->mcodeptr++) = 0x0f;
1226 *(cd->mcodeptr++) = 0xb7;
1227 /* XXX: why do reg and dreg have to be exchanged */
1228 emit_reg((dreg),(reg));
1232 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1233 emit_rex(1,(reg),(indexreg),(basereg));
1234 *(cd->mcodeptr++) = 0x0f;
1235 *(cd->mcodeptr++) = 0xbf;
1236 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1240 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1241 emit_rex(1,(reg),(indexreg),(basereg));
1242 *(cd->mcodeptr++) = 0x0f;
1243 *(cd->mcodeptr++) = 0xbe;
1244 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1248 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1249 emit_rex(1,(reg),(indexreg),(basereg));
1250 *(cd->mcodeptr++) = 0x0f;
1251 *(cd->mcodeptr++) = 0xb7;
1252 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1256 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1258 emit_rex(1,0,(indexreg),(basereg));
1259 *(cd->mcodeptr++) = 0xc7;
1260 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1265 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1267 emit_rex(0,0,(indexreg),(basereg));
1268 *(cd->mcodeptr++) = 0xc7;
1269 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1274 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1276 *(cd->mcodeptr++) = 0x66;
1277 emit_rex(0,0,(indexreg),(basereg));
1278 *(cd->mcodeptr++) = 0xc7;
1279 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1284 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1286 emit_rex(0,0,(indexreg),(basereg));
1287 *(cd->mcodeptr++) = 0xc6;
1288 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1296 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1298 emit_rex(1,(reg),0,(dreg));
1299 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1300 emit_reg((reg),(dreg));
1304 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1306 emit_rex(0,(reg),0,(dreg));
1307 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1308 emit_reg((reg),(dreg));
1312 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1314 emit_rex(1,(reg),0,(basereg));
1315 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1316 emit_membase(cd, (basereg),(disp),(reg));
1320 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1322 emit_rex(0,(reg),0,(basereg));
1323 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1324 emit_membase(cd, (basereg),(disp),(reg));
1328 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1330 emit_rex(1,(reg),0,(basereg));
1331 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1332 emit_membase(cd, (basereg),(disp),(reg));
1336 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1338 emit_rex(0,(reg),0,(basereg));
1339 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1340 emit_membase(cd, (basereg),(disp),(reg));
1344 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1346 emit_rex(1,0,0,(dreg));
1347 *(cd->mcodeptr++) = 0x83;
1348 emit_reg((opc),(dreg));
1351 emit_rex(1,0,0,(dreg));
1352 *(cd->mcodeptr++) = 0x81;
1353 emit_reg((opc),(dreg));
1359 void emit_alu_imm32_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1360 emit_rex(1,0,0,(dreg));
1361 *(cd->mcodeptr++) = 0x81;
1362 emit_reg((opc),(dreg));
1367 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1369 emit_rex(0,0,0,(dreg));
1370 *(cd->mcodeptr++) = 0x83;
1371 emit_reg((opc),(dreg));
1374 emit_rex(0,0,0,(dreg));
1375 *(cd->mcodeptr++) = 0x81;
1376 emit_reg((opc),(dreg));
1382 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1384 emit_rex(1,(basereg),0,0);
1385 *(cd->mcodeptr++) = 0x83;
1386 emit_membase(cd, (basereg),(disp),(opc));
1389 emit_rex(1,(basereg),0,0);
1390 *(cd->mcodeptr++) = 0x81;
1391 emit_membase(cd, (basereg),(disp),(opc));
1397 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1399 emit_rex(0,(basereg),0,0);
1400 *(cd->mcodeptr++) = 0x83;
1401 emit_membase(cd, (basereg),(disp),(opc));
1404 emit_rex(0,(basereg),0,0);
1405 *(cd->mcodeptr++) = 0x81;
1406 emit_membase(cd, (basereg),(disp),(opc));
1412 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1413 emit_rex(1,(reg),0,(dreg));
1414 *(cd->mcodeptr++) = 0x85;
1415 emit_reg((reg),(dreg));
1419 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1420 emit_rex(0,(reg),0,(dreg));
1421 *(cd->mcodeptr++) = 0x85;
1422 emit_reg((reg),(dreg));
1426 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1427 *(cd->mcodeptr++) = 0xf7;
1433 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1434 *(cd->mcodeptr++) = 0x66;
1435 *(cd->mcodeptr++) = 0xf7;
1441 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1442 *(cd->mcodeptr++) = 0xf6;
1448 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1449 emit_rex(1,(reg),0,(basereg));
1450 *(cd->mcodeptr++) = 0x8d;
1451 emit_membase(cd, (basereg),(disp),(reg));
1455 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1456 emit_rex(0,(reg),0,(basereg));
1457 *(cd->mcodeptr++) = 0x8d;
1458 emit_membase(cd, (basereg),(disp),(reg));
1463 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1465 emit_rex(0,0,0,(basereg));
1466 *(cd->mcodeptr++) = 0xff;
1467 emit_membase(cd, (basereg),(disp),0);
1472 void emit_cltd(codegendata *cd) {
1473 *(cd->mcodeptr++) = 0x99;
1477 void emit_cqto(codegendata *cd) {
1479 *(cd->mcodeptr++) = 0x99;
1484 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1485 emit_rex(1,(dreg),0,(reg));
1486 *(cd->mcodeptr++) = 0x0f;
1487 *(cd->mcodeptr++) = 0xaf;
1488 emit_reg((dreg),(reg));
1492 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1493 emit_rex(0,(dreg),0,(reg));
1494 *(cd->mcodeptr++) = 0x0f;
1495 *(cd->mcodeptr++) = 0xaf;
1496 emit_reg((dreg),(reg));
1500 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1501 emit_rex(1,(dreg),0,(basereg));
1502 *(cd->mcodeptr++) = 0x0f;
1503 *(cd->mcodeptr++) = 0xaf;
1504 emit_membase(cd, (basereg),(disp),(dreg));
1508 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1509 emit_rex(0,(dreg),0,(basereg));
1510 *(cd->mcodeptr++) = 0x0f;
1511 *(cd->mcodeptr++) = 0xaf;
1512 emit_membase(cd, (basereg),(disp),(dreg));
1516 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1517 if (IS_IMM8((imm))) {
1518 emit_rex(1,0,0,(dreg));
1519 *(cd->mcodeptr++) = 0x6b;
1523 emit_rex(1,0,0,(dreg));
1524 *(cd->mcodeptr++) = 0x69;
1531 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1532 if (IS_IMM8((imm))) {
1533 emit_rex(1,(dreg),0,(reg));
1534 *(cd->mcodeptr++) = 0x6b;
1535 emit_reg((dreg),(reg));
1538 emit_rex(1,(dreg),0,(reg));
1539 *(cd->mcodeptr++) = 0x69;
1540 emit_reg((dreg),(reg));
1546 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1547 if (IS_IMM8((imm))) {
1548 emit_rex(0,(dreg),0,(reg));
1549 *(cd->mcodeptr++) = 0x6b;
1550 emit_reg((dreg),(reg));
1553 emit_rex(0,(dreg),0,(reg));
1554 *(cd->mcodeptr++) = 0x69;
1555 emit_reg((dreg),(reg));
1561 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1562 if (IS_IMM8((imm))) {
1563 emit_rex(1,(dreg),0,(basereg));
1564 *(cd->mcodeptr++) = 0x6b;
1565 emit_membase(cd, (basereg),(disp),(dreg));
1568 emit_rex(1,(dreg),0,(basereg));
1569 *(cd->mcodeptr++) = 0x69;
1570 emit_membase(cd, (basereg),(disp),(dreg));
1576 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1577 if (IS_IMM8((imm))) {
1578 emit_rex(0,(dreg),0,(basereg));
1579 *(cd->mcodeptr++) = 0x6b;
1580 emit_membase(cd, (basereg),(disp),(dreg));
1583 emit_rex(0,(dreg),0,(basereg));
1584 *(cd->mcodeptr++) = 0x69;
1585 emit_membase(cd, (basereg),(disp),(dreg));
1591 void emit_idiv_reg(codegendata *cd, s8 reg) {
1592 emit_rex(1,0,0,(reg));
1593 *(cd->mcodeptr++) = 0xf7;
1598 void emit_idivl_reg(codegendata *cd, s8 reg) {
1599 emit_rex(0,0,0,(reg));
1600 *(cd->mcodeptr++) = 0xf7;
1606 void emit_ret(codegendata *cd) {
1607 *(cd->mcodeptr++) = 0xc3;
1615 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1616 emit_rex(1,0,0,(reg));
1617 *(cd->mcodeptr++) = 0xd3;
1618 emit_reg((opc),(reg));
1622 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1623 emit_rex(0,0,0,(reg));
1624 *(cd->mcodeptr++) = 0xd3;
1625 emit_reg((opc),(reg));
1629 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1630 emit_rex(1,0,0,(basereg));
1631 *(cd->mcodeptr++) = 0xd3;
1632 emit_membase(cd, (basereg),(disp),(opc));
1636 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1637 emit_rex(0,0,0,(basereg));
1638 *(cd->mcodeptr++) = 0xd3;
1639 emit_membase(cd, (basereg),(disp),(opc));
1643 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1645 emit_rex(1,0,0,(dreg));
1646 *(cd->mcodeptr++) = 0xd1;
1647 emit_reg((opc),(dreg));
1649 emit_rex(1,0,0,(dreg));
1650 *(cd->mcodeptr++) = 0xc1;
1651 emit_reg((opc),(dreg));
1657 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1659 emit_rex(0,0,0,(dreg));
1660 *(cd->mcodeptr++) = 0xd1;
1661 emit_reg((opc),(dreg));
1663 emit_rex(0,0,0,(dreg));
1664 *(cd->mcodeptr++) = 0xc1;
1665 emit_reg((opc),(dreg));
1671 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1673 emit_rex(1,0,0,(basereg));
1674 *(cd->mcodeptr++) = 0xd1;
1675 emit_membase(cd, (basereg),(disp),(opc));
1677 emit_rex(1,0,0,(basereg));
1678 *(cd->mcodeptr++) = 0xc1;
1679 emit_membase(cd, (basereg),(disp),(opc));
1685 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1687 emit_rex(0,0,0,(basereg));
1688 *(cd->mcodeptr++) = 0xd1;
1689 emit_membase(cd, (basereg),(disp),(opc));
1691 emit_rex(0,0,0,(basereg));
1692 *(cd->mcodeptr++) = 0xc1;
1693 emit_membase(cd, (basereg),(disp),(opc));
1703 void emit_jmp_imm(codegendata *cd, s8 imm) {
1704 *(cd->mcodeptr++) = 0xe9;
1709 void emit_jmp_reg(codegendata *cd, s8 reg) {
1710 emit_rex(0,0,0,(reg));
1711 *(cd->mcodeptr++) = 0xff;
1716 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1717 *(cd->mcodeptr++) = 0x0f;
1718 *(cd->mcodeptr++) = (0x80 + (opc));
1725 * conditional set and move operations
1728 /* we need the rex byte to get all low bytes */
1729 void emit_setcc_reg(codegendata *cd, s8 opc, s8 reg) {
1730 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1731 *(cd->mcodeptr++) = 0x0f;
1732 *(cd->mcodeptr++) = (0x90 + (opc));
1737 /* we need the rex byte to get all low bytes */
1738 void emit_setcc_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1739 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1740 *(cd->mcodeptr++) = 0x0f;
1741 *(cd->mcodeptr++) = (0x90 + (opc));
1742 emit_membase(cd, (basereg),(disp),0);
1746 void emit_cmovcc_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1748 emit_rex(1,(dreg),0,(reg));
1749 *(cd->mcodeptr++) = 0x0f;
1750 *(cd->mcodeptr++) = (0x40 + (opc));
1751 emit_reg((dreg),(reg));
1755 void emit_cmovccl_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1757 emit_rex(0,(dreg),0,(reg));
1758 *(cd->mcodeptr++) = 0x0f;
1759 *(cd->mcodeptr++) = (0x40 + (opc));
1760 emit_reg((dreg),(reg));
1765 void emit_neg_reg(codegendata *cd, s8 reg)
1767 emit_rex(1,0,0,(reg));
1768 *(cd->mcodeptr++) = 0xf7;
1773 void emit_negl_reg(codegendata *cd, s8 reg)
1775 emit_rex(0,0,0,(reg));
1776 *(cd->mcodeptr++) = 0xf7;
1781 void emit_push_reg(codegendata *cd, s8 reg) {
1782 emit_rex(0,0,0,(reg));
1783 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1787 void emit_push_imm(codegendata *cd, s8 imm) {
1788 *(cd->mcodeptr++) = 0x68;
1793 void emit_pop_reg(codegendata *cd, s8 reg) {
1794 emit_rex(0,0,0,(reg));
1795 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1799 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1800 emit_rex(1,(reg),0,(dreg));
1801 *(cd->mcodeptr++) = 0x87;
1802 emit_reg((reg),(dreg));
1806 void emit_nop(codegendata *cd) {
1807 *(cd->mcodeptr++) = 0x90;
1815 void emit_call_reg(codegendata *cd, s8 reg) {
1816 emit_rex(1,0,0,(reg));
1817 *(cd->mcodeptr++) = 0xff;
1822 void emit_call_imm(codegendata *cd, s8 imm) {
1823 *(cd->mcodeptr++) = 0xe8;
1828 void emit_call_mem(codegendata *cd, ptrint mem)
1830 *(cd->mcodeptr++) = 0xff;
1837 * floating point instructions (SSE2)
1839 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1840 *(cd->mcodeptr++) = 0xf2;
1841 emit_rex(0,(dreg),0,(reg));
1842 *(cd->mcodeptr++) = 0x0f;
1843 *(cd->mcodeptr++) = 0x58;
1844 emit_reg((dreg),(reg));
1848 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1849 *(cd->mcodeptr++) = 0xf3;
1850 emit_rex(0,(dreg),0,(reg));
1851 *(cd->mcodeptr++) = 0x0f;
1852 *(cd->mcodeptr++) = 0x58;
1853 emit_reg((dreg),(reg));
1857 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1858 *(cd->mcodeptr++) = 0xf3;
1859 emit_rex(1,(dreg),0,(reg));
1860 *(cd->mcodeptr++) = 0x0f;
1861 *(cd->mcodeptr++) = 0x2a;
1862 emit_reg((dreg),(reg));
1866 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1867 *(cd->mcodeptr++) = 0xf3;
1868 emit_rex(0,(dreg),0,(reg));
1869 *(cd->mcodeptr++) = 0x0f;
1870 *(cd->mcodeptr++) = 0x2a;
1871 emit_reg((dreg),(reg));
1875 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1876 *(cd->mcodeptr++) = 0xf2;
1877 emit_rex(1,(dreg),0,(reg));
1878 *(cd->mcodeptr++) = 0x0f;
1879 *(cd->mcodeptr++) = 0x2a;
1880 emit_reg((dreg),(reg));
1884 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1885 *(cd->mcodeptr++) = 0xf2;
1886 emit_rex(0,(dreg),0,(reg));
1887 *(cd->mcodeptr++) = 0x0f;
1888 *(cd->mcodeptr++) = 0x2a;
1889 emit_reg((dreg),(reg));
1893 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1894 *(cd->mcodeptr++) = 0xf3;
1895 emit_rex(0,(dreg),0,(reg));
1896 *(cd->mcodeptr++) = 0x0f;
1897 *(cd->mcodeptr++) = 0x5a;
1898 emit_reg((dreg),(reg));
1902 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1903 *(cd->mcodeptr++) = 0xf2;
1904 emit_rex(0,(dreg),0,(reg));
1905 *(cd->mcodeptr++) = 0x0f;
1906 *(cd->mcodeptr++) = 0x5a;
1907 emit_reg((dreg),(reg));
1911 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1912 *(cd->mcodeptr++) = 0xf3;
1913 emit_rex(1,(dreg),0,(reg));
1914 *(cd->mcodeptr++) = 0x0f;
1915 *(cd->mcodeptr++) = 0x2c;
1916 emit_reg((dreg),(reg));
1920 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1921 *(cd->mcodeptr++) = 0xf3;
1922 emit_rex(0,(dreg),0,(reg));
1923 *(cd->mcodeptr++) = 0x0f;
1924 *(cd->mcodeptr++) = 0x2c;
1925 emit_reg((dreg),(reg));
1929 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1930 *(cd->mcodeptr++) = 0xf2;
1931 emit_rex(1,(dreg),0,(reg));
1932 *(cd->mcodeptr++) = 0x0f;
1933 *(cd->mcodeptr++) = 0x2c;
1934 emit_reg((dreg),(reg));
1938 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1939 *(cd->mcodeptr++) = 0xf2;
1940 emit_rex(0,(dreg),0,(reg));
1941 *(cd->mcodeptr++) = 0x0f;
1942 *(cd->mcodeptr++) = 0x2c;
1943 emit_reg((dreg),(reg));
1947 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1948 *(cd->mcodeptr++) = 0xf3;
1949 emit_rex(0,(dreg),0,(reg));
1950 *(cd->mcodeptr++) = 0x0f;
1951 *(cd->mcodeptr++) = 0x5e;
1952 emit_reg((dreg),(reg));
1956 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1957 *(cd->mcodeptr++) = 0xf2;
1958 emit_rex(0,(dreg),0,(reg));
1959 *(cd->mcodeptr++) = 0x0f;
1960 *(cd->mcodeptr++) = 0x5e;
1961 emit_reg((dreg),(reg));
1965 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1966 *(cd->mcodeptr++) = 0x66;
1967 emit_rex(1,(freg),0,(reg));
1968 *(cd->mcodeptr++) = 0x0f;
1969 *(cd->mcodeptr++) = 0x6e;
1970 emit_reg((freg),(reg));
1974 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1975 *(cd->mcodeptr++) = 0x66;
1976 emit_rex(1,(freg),0,(reg));
1977 *(cd->mcodeptr++) = 0x0f;
1978 *(cd->mcodeptr++) = 0x7e;
1979 emit_reg((freg),(reg));
1983 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1984 *(cd->mcodeptr++) = 0x66;
1985 emit_rex(0,(reg),0,(basereg));
1986 *(cd->mcodeptr++) = 0x0f;
1987 *(cd->mcodeptr++) = 0x7e;
1988 emit_membase(cd, (basereg),(disp),(reg));
1992 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1993 *(cd->mcodeptr++) = 0x66;
1994 emit_rex(0,(reg),(indexreg),(basereg));
1995 *(cd->mcodeptr++) = 0x0f;
1996 *(cd->mcodeptr++) = 0x7e;
1997 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2001 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2002 *(cd->mcodeptr++) = 0x66;
2003 emit_rex(1,(dreg),0,(basereg));
2004 *(cd->mcodeptr++) = 0x0f;
2005 *(cd->mcodeptr++) = 0x6e;
2006 emit_membase(cd, (basereg),(disp),(dreg));
2010 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2011 *(cd->mcodeptr++) = 0x66;
2012 emit_rex(0,(dreg),0,(basereg));
2013 *(cd->mcodeptr++) = 0x0f;
2014 *(cd->mcodeptr++) = 0x6e;
2015 emit_membase(cd, (basereg),(disp),(dreg));
2019 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2020 *(cd->mcodeptr++) = 0x66;
2021 emit_rex(0,(dreg),(indexreg),(basereg));
2022 *(cd->mcodeptr++) = 0x0f;
2023 *(cd->mcodeptr++) = 0x6e;
2024 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2028 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2029 *(cd->mcodeptr++) = 0xf3;
2030 emit_rex(0,(dreg),0,(reg));
2031 *(cd->mcodeptr++) = 0x0f;
2032 *(cd->mcodeptr++) = 0x7e;
2033 emit_reg((dreg),(reg));
2037 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2038 *(cd->mcodeptr++) = 0x66;
2039 emit_rex(0,(reg),0,(basereg));
2040 *(cd->mcodeptr++) = 0x0f;
2041 *(cd->mcodeptr++) = 0xd6;
2042 emit_membase(cd, (basereg),(disp),(reg));
2046 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2047 *(cd->mcodeptr++) = 0xf3;
2048 emit_rex(0,(dreg),0,(basereg));
2049 *(cd->mcodeptr++) = 0x0f;
2050 *(cd->mcodeptr++) = 0x7e;
2051 emit_membase(cd, (basereg),(disp),(dreg));
2055 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2056 *(cd->mcodeptr++) = 0xf3;
2057 emit_rex(0,(reg),0,(dreg));
2058 *(cd->mcodeptr++) = 0x0f;
2059 *(cd->mcodeptr++) = 0x10;
2060 emit_reg((reg),(dreg));
2064 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2065 *(cd->mcodeptr++) = 0xf2;
2066 emit_rex(0,(reg),0,(dreg));
2067 *(cd->mcodeptr++) = 0x0f;
2068 *(cd->mcodeptr++) = 0x10;
2069 emit_reg((reg),(dreg));
2073 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2074 *(cd->mcodeptr++) = 0xf3;
2075 emit_rex(0,(reg),0,(basereg));
2076 *(cd->mcodeptr++) = 0x0f;
2077 *(cd->mcodeptr++) = 0x11;
2078 emit_membase(cd, (basereg),(disp),(reg));
2082 /* Always emit a REX byte, because the instruction size can be smaller when */
2083 /* all register indexes are smaller than 7. */
2084 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2085 *(cd->mcodeptr++) = 0xf3;
2086 emit_byte_rex((reg),0,(basereg));
2087 *(cd->mcodeptr++) = 0x0f;
2088 *(cd->mcodeptr++) = 0x11;
2089 emit_membase32(cd, (basereg),(disp),(reg));
2093 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2094 *(cd->mcodeptr++) = 0xf2;
2095 emit_rex(0,(reg),0,(basereg));
2096 *(cd->mcodeptr++) = 0x0f;
2097 *(cd->mcodeptr++) = 0x11;
2098 emit_membase(cd, (basereg),(disp),(reg));
2102 /* Always emit a REX byte, because the instruction size can be smaller when */
2103 /* all register indexes are smaller than 7. */
2104 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2105 *(cd->mcodeptr++) = 0xf2;
2106 emit_byte_rex((reg),0,(basereg));
2107 *(cd->mcodeptr++) = 0x0f;
2108 *(cd->mcodeptr++) = 0x11;
2109 emit_membase32(cd, (basereg),(disp),(reg));
2113 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2114 *(cd->mcodeptr++) = 0xf3;
2115 emit_rex(0,(dreg),0,(basereg));
2116 *(cd->mcodeptr++) = 0x0f;
2117 *(cd->mcodeptr++) = 0x10;
2118 emit_membase(cd, (basereg),(disp),(dreg));
2122 /* Always emit a REX byte, because the instruction size can be smaller when */
2123 /* all register indexes are smaller than 7. */
2124 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2125 *(cd->mcodeptr++) = 0xf3;
2126 emit_byte_rex((dreg),0,(basereg));
2127 *(cd->mcodeptr++) = 0x0f;
2128 *(cd->mcodeptr++) = 0x10;
2129 emit_membase32(cd, (basereg),(disp),(dreg));
2133 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2135 emit_rex(0,(dreg),0,(basereg));
2136 *(cd->mcodeptr++) = 0x0f;
2137 *(cd->mcodeptr++) = 0x12;
2138 emit_membase(cd, (basereg),(disp),(dreg));
2142 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2144 emit_rex(0,(reg),0,(basereg));
2145 *(cd->mcodeptr++) = 0x0f;
2146 *(cd->mcodeptr++) = 0x13;
2147 emit_membase(cd, (basereg),(disp),(reg));
2151 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2152 *(cd->mcodeptr++) = 0xf2;
2153 emit_rex(0,(dreg),0,(basereg));
2154 *(cd->mcodeptr++) = 0x0f;
2155 *(cd->mcodeptr++) = 0x10;
2156 emit_membase(cd, (basereg),(disp),(dreg));
2160 /* Always emit a REX byte, because the instruction size can be smaller when */
2161 /* all register indexes are smaller than 7. */
2162 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2163 *(cd->mcodeptr++) = 0xf2;
2164 emit_byte_rex((dreg),0,(basereg));
2165 *(cd->mcodeptr++) = 0x0f;
2166 *(cd->mcodeptr++) = 0x10;
2167 emit_membase32(cd, (basereg),(disp),(dreg));
2171 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2173 *(cd->mcodeptr++) = 0x66;
2174 emit_rex(0,(dreg),0,(basereg));
2175 *(cd->mcodeptr++) = 0x0f;
2176 *(cd->mcodeptr++) = 0x12;
2177 emit_membase(cd, (basereg),(disp),(dreg));
2181 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2183 *(cd->mcodeptr++) = 0x66;
2184 emit_rex(0,(reg),0,(basereg));
2185 *(cd->mcodeptr++) = 0x0f;
2186 *(cd->mcodeptr++) = 0x13;
2187 emit_membase(cd, (basereg),(disp),(reg));
2191 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2192 *(cd->mcodeptr++) = 0xf3;
2193 emit_rex(0,(reg),(indexreg),(basereg));
2194 *(cd->mcodeptr++) = 0x0f;
2195 *(cd->mcodeptr++) = 0x11;
2196 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2200 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2201 *(cd->mcodeptr++) = 0xf2;
2202 emit_rex(0,(reg),(indexreg),(basereg));
2203 *(cd->mcodeptr++) = 0x0f;
2204 *(cd->mcodeptr++) = 0x11;
2205 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2209 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2210 *(cd->mcodeptr++) = 0xf3;
2211 emit_rex(0,(dreg),(indexreg),(basereg));
2212 *(cd->mcodeptr++) = 0x0f;
2213 *(cd->mcodeptr++) = 0x10;
2214 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2218 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2219 *(cd->mcodeptr++) = 0xf2;
2220 emit_rex(0,(dreg),(indexreg),(basereg));
2221 *(cd->mcodeptr++) = 0x0f;
2222 *(cd->mcodeptr++) = 0x10;
2223 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2227 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2228 *(cd->mcodeptr++) = 0xf3;
2229 emit_rex(0,(dreg),0,(reg));
2230 *(cd->mcodeptr++) = 0x0f;
2231 *(cd->mcodeptr++) = 0x59;
2232 emit_reg((dreg),(reg));
2236 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2237 *(cd->mcodeptr++) = 0xf2;
2238 emit_rex(0,(dreg),0,(reg));
2239 *(cd->mcodeptr++) = 0x0f;
2240 *(cd->mcodeptr++) = 0x59;
2241 emit_reg((dreg),(reg));
2245 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2246 *(cd->mcodeptr++) = 0xf3;
2247 emit_rex(0,(dreg),0,(reg));
2248 *(cd->mcodeptr++) = 0x0f;
2249 *(cd->mcodeptr++) = 0x5c;
2250 emit_reg((dreg),(reg));
2254 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2255 *(cd->mcodeptr++) = 0xf2;
2256 emit_rex(0,(dreg),0,(reg));
2257 *(cd->mcodeptr++) = 0x0f;
2258 *(cd->mcodeptr++) = 0x5c;
2259 emit_reg((dreg),(reg));
2263 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2264 emit_rex(0,(dreg),0,(reg));
2265 *(cd->mcodeptr++) = 0x0f;
2266 *(cd->mcodeptr++) = 0x2e;
2267 emit_reg((dreg),(reg));
2271 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2272 *(cd->mcodeptr++) = 0x66;
2273 emit_rex(0,(dreg),0,(reg));
2274 *(cd->mcodeptr++) = 0x0f;
2275 *(cd->mcodeptr++) = 0x2e;
2276 emit_reg((dreg),(reg));
2280 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2281 emit_rex(0,(dreg),0,(reg));
2282 *(cd->mcodeptr++) = 0x0f;
2283 *(cd->mcodeptr++) = 0x57;
2284 emit_reg((dreg),(reg));
2288 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2289 emit_rex(0,(dreg),0,(basereg));
2290 *(cd->mcodeptr++) = 0x0f;
2291 *(cd->mcodeptr++) = 0x57;
2292 emit_membase(cd, (basereg),(disp),(dreg));
2296 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2297 *(cd->mcodeptr++) = 0x66;
2298 emit_rex(0,(dreg),0,(reg));
2299 *(cd->mcodeptr++) = 0x0f;
2300 *(cd->mcodeptr++) = 0x57;
2301 emit_reg((dreg),(reg));
2305 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2306 *(cd->mcodeptr++) = 0x66;
2307 emit_rex(0,(dreg),0,(basereg));
2308 *(cd->mcodeptr++) = 0x0f;
2309 *(cd->mcodeptr++) = 0x57;
2310 emit_membase(cd, (basereg),(disp),(dreg));
2314 /* system instructions ********************************************************/
2316 void emit_rdtsc(codegendata *cd)
2318 *(cd->mcodeptr++) = 0x0f;
2319 *(cd->mcodeptr++) = 0x31;
2324 * These are local overrides for various environment variables in Emacs.
2325 * Please do not remove this and leave it at the end of the file, where
2326 * Emacs will automagically detect them.
2327 * ---------------------------------------------------------------------
2330 * indent-tabs-mode: t