1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 Contact: cacao@cacaojvm.org
27 Authors: Christian Thalinger
29 $Id: emit.c 6132 2006-12-07 10:59:01Z twisti $
39 #include "vm/jit/x86_64/codegen.h"
40 #include "vm/jit/x86_64/emit.h"
42 #if defined(ENABLE_THREADS)
43 # include "threads/native/lock.h"
46 #include "vm/builtin.h"
47 #include "vm/options.h"
48 #include "vm/jit/abi-asm.h"
49 #include "vm/jit/asmpart.h"
50 #include "vm/jit/codegen-common.h"
51 #include "vm/jit/emit-common.h"
52 #include "vm/jit/jit.h"
53 #include "vm/jit/replace.h"
56 /* emit_load *******************************************************************
58 Emits a possible load of an operand.
60 *******************************************************************************/
62 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
68 /* get required compiler data */
72 if (IS_INMEMORY(src->flags)) {
75 disp = src->vv.regoff * 8;
77 if (IS_FLT_DBL_TYPE(src->type)) {
78 if (IS_2_WORD_TYPE(src->type))
79 M_DLD(tempreg, REG_SP, disp);
81 M_FLD(tempreg, REG_SP, disp);
84 if (IS_INT_TYPE(src->type))
85 M_ILD(tempreg, REG_SP, disp);
87 M_LLD(tempreg, REG_SP, disp);
99 /* emit_store ******************************************************************
101 This function generates the code to store the result of an
102 operation back into a spilled pseudo-variable. If the
103 pseudo-variable has not been spilled in the first place, this
104 function will generate nothing.
106 *******************************************************************************/
108 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
117 /* get required compiler data */
122 /* do we have to generate a conditional move? */
124 if ((iptr != NULL) && (iptr->opc & ICMD_CONDITION_MASK)) {
125 /* the passed register d is actually the source register */
129 /* Only pass the opcode to codegen_reg_of_var to get the real
130 destination register. */
132 opcode = iptr->opc & ICMD_OPCODE_MASK;
134 /* get the real destination register */
136 d = codegen_reg_of_var(rd, opcode, dst, REG_ITMP1);
138 /* and emit the conditional move */
140 emit_cmovxx(cd, iptr, s, d);
144 if (IS_INMEMORY(dst->flags)) {
147 disp = dst->vv.regoff * 8;
149 if (IS_FLT_DBL_TYPE(dst->type)) {
150 if (IS_2_WORD_TYPE(dst->type))
151 M_DST(d, REG_SP, disp);
153 M_FST(d, REG_SP, disp);
156 M_LST(d, REG_SP, disp);
161 /* emit_copy *******************************************************************
163 Generates a register/memory to register/memory copy.
165 *******************************************************************************/
167 void emit_copy(jitdata *jd, instruction *iptr, varinfo *src, varinfo *dst)
172 /* get required compiler data */
176 if ((src->vv.regoff != dst->vv.regoff) ||
177 ((src->flags ^ dst->flags) & INMEMORY)) {
179 /* If one of the variables resides in memory, we can eliminate
180 the register move from/to the temporary register with the
181 order of getting the destination register and the load. */
183 if (IS_INMEMORY(src->flags)) {
184 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
185 s1 = emit_load(jd, iptr, src, d);
188 s1 = emit_load(jd, iptr, src, REG_IFTMP);
189 d = codegen_reg_of_var(iptr->opc, dst, s1);
193 if (IS_FLT_DBL_TYPE(src->type))
199 emit_store(jd, iptr, dst, d);
204 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
207 switch (iptr->flags.fields.condition) {
231 /* emit_arithmetic_check *******************************************************
233 Emit an ArithmeticException check.
235 *******************************************************************************/
237 void emit_arithmetic_check(codegendata *cd, s4 reg)
242 codegen_add_arithmeticexception_ref(cd);
247 /* emit_arrayindexoutofbounds_check ********************************************
249 Emit a ArrayIndexOutOfBoundsException check.
251 *******************************************************************************/
253 void emit_arrayindexoutofbounds_check(codegendata *cd, s4 s1, s4 s2)
256 M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));
257 M_ICMP(REG_ITMP3, s2);
259 codegen_add_arrayindexoutofboundsexception_ref(cd, s2);
264 /* emit_classcast_check ********************************************************
266 Emit a ClassCastException check.
268 *******************************************************************************/
270 void emit_classcast_check(codegendata *cd, s4 condition, s4 reg, s4 s1)
272 vm_abort("IMPLEMENT ME!");
276 /* emit_nullpointer_check ******************************************************
278 Emit a NullPointerException check.
280 *******************************************************************************/
282 void emit_nullpointer_check(codegendata *cd, s4 reg)
287 codegen_add_nullpointerexception_ref(cd);
292 /* emit_exception_stubs ********************************************************
294 Generates the code for the exception stubs.
296 *******************************************************************************/
298 void emit_exception_stubs(jitdata *jd)
307 /* get required compiler data */
312 /* generate exception stubs */
316 for (er = cd->exceptionrefs; er != NULL; er = er->next) {
317 /* back-patch the branch to this exception code */
319 branchmpc = er->branchpos;
320 targetmpc = cd->mcodeptr - cd->mcodebase;
322 md_codegen_patch_branch(cd, branchmpc, targetmpc);
326 /* Check if the exception is an
327 ArrayIndexOutOfBoundsException. If so, move index register
331 M_MOV(er->reg, rd->argintregs[4]);
333 /* calcuate exception address */
335 M_MOV_IMM(0, rd->argintregs[3]);
337 M_AADD_IMM32(er->branchpos - 6, rd->argintregs[3]);
339 /* move function to call into REG_ITMP3 */
341 M_MOV_IMM(er->function, REG_ITMP3);
343 if (targetdisp == 0) {
344 targetdisp = cd->mcodeptr - cd->mcodebase;
346 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase), rd->argintregs[0]);
347 M_MOV(REG_SP, rd->argintregs[1]);
348 M_ALD(rd->argintregs[2], REG_SP, cd->stackframesize * 8);
350 M_ASUB_IMM(2 * 8, REG_SP);
351 M_AST(rd->argintregs[3], REG_SP, 0 * 8); /* store XPC */
355 M_ALD(REG_ITMP2_XPC, REG_SP, 0 * 8);
356 M_AADD_IMM(2 * 8, REG_SP);
358 M_MOV_IMM(asm_handle_exception, REG_ITMP3);
362 M_JMP_IMM((cd->mcodebase + targetdisp) -
363 (cd->mcodeptr + PATCHER_CALL_SIZE));
369 /* emit_patcher_stubs **********************************************************
371 Generates the code for the patcher stubs.
373 *******************************************************************************/
375 void emit_patcher_stubs(jitdata *jd)
385 /* get required compiler data */
389 /* generate code patching stub call code */
393 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
394 /* check size of code segment */
398 /* Get machine code which is patched back in later. A
399 `call rel32' is 5 bytes long (but read 8 bytes). */
401 savedmcodeptr = cd->mcodebase + pref->branchpos;
402 mcode = *((u8 *) savedmcodeptr);
404 /* patch in `call rel32' to call the following code */
406 tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
407 cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
409 M_CALL_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE));
411 cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
413 /* move pointer to java_objectheader onto stack */
415 #if defined(ENABLE_THREADS)
416 /* create a virtual java_objectheader */
418 (void) dseg_add_unique_address(cd, NULL); /* flcword */
419 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
420 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
422 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase) + disp, REG_ITMP3);
428 /* move machine code bytes and classinfo pointer into registers */
430 M_MOV_IMM(mcode, REG_ITMP3);
433 M_MOV_IMM(pref->ref, REG_ITMP3);
436 M_MOV_IMM(pref->disp, REG_ITMP3);
439 M_MOV_IMM(pref->patcher, REG_ITMP3);
442 if (targetdisp == 0) {
443 targetdisp = cd->mcodeptr - cd->mcodebase;
445 M_MOV_IMM(asm_patcher_wrapper, REG_ITMP3);
449 M_JMP_IMM((cd->mcodebase + targetdisp) -
450 (cd->mcodeptr + PATCHER_CALL_SIZE));
456 /* emit_replacement_stubs ******************************************************
458 Generates the code for the replacement stubs.
460 *******************************************************************************/
462 void emit_replacement_stubs(jitdata *jd)
470 /* get required compiler data */
475 rplp = code->rplpoints;
477 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
478 /* check code segment size */
482 /* note start of stub code */
484 rplp->outcode = (u1 *) (ptrint) (cd->mcodeptr - cd->mcodebase);
486 /* make machine code for patching */
488 disp = (ptrint) (rplp->outcode - rplp->pc) - 5;
490 rplp->mcode = 0xe9 | ((u8) disp << 8);
492 /* push address of `rplpoint` struct */
494 M_MOV_IMM(rplp, REG_ITMP3);
497 /* jump to replacement function */
499 M_MOV_IMM(asm_replacement_out, REG_ITMP3);
505 /* emit_verbosecall_enter ******************************************************
507 Generates the code for the call trace.
509 *******************************************************************************/
512 void emit_verbosecall_enter(jitdata *jd)
520 /* get required compiler data */
528 /* mark trace code */
532 /* additional +1 is for 16-byte stack alignment */
534 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
536 /* save argument registers */
538 for (i = 0; i < INT_ARG_CNT; i++)
539 M_LST(rd->argintregs[i], REG_SP, (1 + i) * 8);
541 for (i = 0; i < FLT_ARG_CNT; i++)
542 M_DST(rd->argfltregs[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
544 /* save temporary registers for leaf methods */
546 if (jd->isleafmethod) {
547 for (i = 0; i < INT_TMP_CNT; i++)
548 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
550 for (i = 0; i < FLT_TMP_CNT; i++)
551 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
554 /* show integer hex code for float arguments */
556 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
557 /* If the paramtype is a float, we have to right shift all
558 following integer registers. */
560 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
561 for (k = INT_ARG_CNT - 2; k >= i; k--)
562 M_MOV(rd->argintregs[k], rd->argintregs[k + 1]);
564 emit_movd_freg_reg(cd, rd->argfltregs[j], rd->argintregs[i]);
569 M_MOV_IMM(m, REG_ITMP2);
570 M_AST(REG_ITMP2, REG_SP, 0 * 8);
571 M_MOV_IMM(builtin_trace_args, REG_ITMP1);
574 /* restore argument registers */
576 for (i = 0; i < INT_ARG_CNT; i++)
577 M_LLD(rd->argintregs[i], REG_SP, (1 + i) * 8);
579 for (i = 0; i < FLT_ARG_CNT; i++)
580 M_DLD(rd->argfltregs[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
582 /* restore temporary registers for leaf methods */
584 if (jd->isleafmethod) {
585 for (i = 0; i < INT_TMP_CNT; i++)
586 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
588 for (i = 0; i < FLT_TMP_CNT; i++)
589 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
592 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
594 /* mark trace code */
598 #endif /* !defined(NDEBUG) */
601 /* emit_verbosecall_exit *******************************************************
603 Generates the code for the call trace.
605 *******************************************************************************/
608 void emit_verbosecall_exit(jitdata *jd)
614 /* get required compiler data */
620 /* mark trace code */
624 M_ASUB_IMM(2 * 8, REG_SP);
626 M_LST(REG_RESULT, REG_SP, 0 * 8);
627 M_DST(REG_FRESULT, REG_SP, 1 * 8);
629 M_MOV_IMM(m, rd->argintregs[0]);
630 M_MOV(REG_RESULT, rd->argintregs[1]);
631 M_FLTMOVE(REG_FRESULT, rd->argfltregs[0]);
632 M_FLTMOVE(REG_FRESULT, rd->argfltregs[1]);
634 M_MOV_IMM(builtin_displaymethodstop, REG_ITMP1);
637 M_LLD(REG_RESULT, REG_SP, 0 * 8);
638 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
640 M_AADD_IMM(2 * 8, REG_SP);
642 /* mark trace code */
646 #endif /* !defined(NDEBUG) */
649 /* code generation functions **************************************************/
651 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
653 if ((basereg == REG_SP) || (basereg == R12)) {
655 emit_address_byte(0, dreg, REG_SP);
656 emit_address_byte(0, REG_SP, REG_SP);
658 } else if (IS_IMM8(disp)) {
659 emit_address_byte(1, dreg, REG_SP);
660 emit_address_byte(0, REG_SP, REG_SP);
664 emit_address_byte(2, dreg, REG_SP);
665 emit_address_byte(0, REG_SP, REG_SP);
669 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
670 emit_address_byte(0,(dreg),(basereg));
672 } else if ((basereg) == RIP) {
673 emit_address_byte(0, dreg, RBP);
678 emit_address_byte(1, dreg, basereg);
682 emit_address_byte(2, dreg, basereg);
689 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
691 if ((basereg == REG_SP) || (basereg == R12)) {
692 emit_address_byte(2, dreg, REG_SP);
693 emit_address_byte(0, REG_SP, REG_SP);
697 emit_address_byte(2, dreg, basereg);
703 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
706 emit_address_byte(0, reg, 4);
707 emit_address_byte(scale, indexreg, 5);
710 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
711 emit_address_byte(0, reg, 4);
712 emit_address_byte(scale, indexreg, basereg);
714 else if (IS_IMM8(disp)) {
715 emit_address_byte(1, reg, 4);
716 emit_address_byte(scale, indexreg, basereg);
720 emit_address_byte(2, reg, 4);
721 emit_address_byte(scale, indexreg, basereg);
727 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
730 varinfo *v_s1,*v_s2,*v_dst;
733 /* get required compiler data */
737 v_s1 = VAROP(iptr->s1);
738 v_s2 = VAROP(iptr->sx.s23.s2);
739 v_dst = VAROP(iptr->dst);
741 s1 = v_s1->vv.regoff;
742 s2 = v_s2->vv.regoff;
743 d = v_dst->vv.regoff;
745 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
747 if (IS_INMEMORY(v_dst->flags)) {
748 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
750 M_ILD(RCX, REG_SP, s2 * 8);
751 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
754 M_ILD(RCX, REG_SP, s2 * 8);
755 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
756 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
757 M_IST(REG_ITMP2, REG_SP, d * 8);
760 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
761 /* s1 may be equal to RCX */
764 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
765 M_IST(s1, REG_SP, d * 8);
766 M_INTMOVE(REG_ITMP1, RCX);
769 M_IST(s1, REG_SP, d * 8);
770 M_ILD(RCX, REG_SP, s2 * 8);
774 M_ILD(RCX, REG_SP, s2 * 8);
775 M_IST(s1, REG_SP, d * 8);
778 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
780 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
783 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
787 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
788 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
789 M_IST(REG_ITMP2, REG_SP, d * 8);
793 /* s1 may be equal to RCX */
794 M_IST(s1, REG_SP, d * 8);
796 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
799 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
807 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
808 M_ILD(RCX, REG_SP, s2 * 8);
809 M_ILD(d, REG_SP, s1 * 8);
810 emit_shiftl_reg(cd, shift_op, d);
812 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
813 /* s1 may be equal to RCX */
815 M_ILD(RCX, REG_SP, s2 * 8);
816 emit_shiftl_reg(cd, shift_op, d);
818 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
820 M_ILD(d, REG_SP, s1 * 8);
821 emit_shiftl_reg(cd, shift_op, d);
824 /* s1 may be equal to RCX */
827 /* d cannot be used to backup s1 since this would
829 M_INTMOVE(s1, REG_ITMP3);
831 M_INTMOVE(REG_ITMP3, d);
839 /* d may be equal to s2 */
843 emit_shiftl_reg(cd, shift_op, d);
847 M_INTMOVE(REG_ITMP3, RCX);
849 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
854 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
857 varinfo *v_s1,*v_s2,*v_dst;
860 /* get required compiler data */
864 v_s1 = VAROP(iptr->s1);
865 v_s2 = VAROP(iptr->sx.s23.s2);
866 v_dst = VAROP(iptr->dst);
868 s1 = v_s1->vv.regoff;
869 s2 = v_s2->vv.regoff;
870 d = v_dst->vv.regoff;
872 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
874 if (IS_INMEMORY(v_dst->flags)) {
875 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
877 M_ILD(RCX, REG_SP, s2 * 8);
878 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
881 M_ILD(RCX, REG_SP, s2 * 8);
882 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
883 emit_shift_reg(cd, shift_op, REG_ITMP2);
884 M_LST(REG_ITMP2, REG_SP, d * 8);
887 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
888 /* s1 may be equal to RCX */
891 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
892 M_LST(s1, REG_SP, d * 8);
893 M_INTMOVE(REG_ITMP1, RCX);
896 M_LST(s1, REG_SP, d * 8);
897 M_ILD(RCX, REG_SP, s2 * 8);
901 M_ILD(RCX, REG_SP, s2 * 8);
902 M_LST(s1, REG_SP, d * 8);
905 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
907 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
910 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
914 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
915 emit_shift_reg(cd, shift_op, REG_ITMP2);
916 M_LST(REG_ITMP2, REG_SP, d * 8);
920 /* s1 may be equal to RCX */
921 M_LST(s1, REG_SP, d * 8);
923 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
926 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
934 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
935 M_ILD(RCX, REG_SP, s2 * 8);
936 M_LLD(d, REG_SP, s1 * 8);
937 emit_shift_reg(cd, shift_op, d);
939 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
940 /* s1 may be equal to RCX */
942 M_ILD(RCX, REG_SP, s2 * 8);
943 emit_shift_reg(cd, shift_op, d);
945 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
947 M_LLD(d, REG_SP, s1 * 8);
948 emit_shift_reg(cd, shift_op, d);
951 /* s1 may be equal to RCX */
954 /* d cannot be used to backup s1 since this would
956 M_INTMOVE(s1, REG_ITMP3);
958 M_INTMOVE(REG_ITMP3, d);
966 /* d may be equal to s2 */
970 emit_shift_reg(cd, shift_op, d);
974 M_INTMOVE(REG_ITMP3, RCX);
976 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
981 /* low-level code emitter functions *******************************************/
983 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
985 emit_rex(1,(reg),0,(dreg));
986 *(cd->mcodeptr++) = 0x89;
987 emit_reg((reg),(dreg));
991 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
993 emit_rex(1,0,0,(reg));
994 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
999 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1001 emit_rex(0,(reg),0,(dreg));
1002 *(cd->mcodeptr++) = 0x89;
1003 emit_reg((reg),(dreg));
1007 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1008 emit_rex(0,0,0,(reg));
1009 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1014 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1015 emit_rex(1,(reg),0,(basereg));
1016 *(cd->mcodeptr++) = 0x8b;
1017 emit_membase(cd, (basereg),(disp),(reg));
1022 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1023 * constant membase immediate length of 32bit
1025 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1026 emit_rex(1,(reg),0,(basereg));
1027 *(cd->mcodeptr++) = 0x8b;
1028 emit_membase32(cd, (basereg),(disp),(reg));
1032 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1034 emit_rex(0,(reg),0,(basereg));
1035 *(cd->mcodeptr++) = 0x8b;
1036 emit_membase(cd, (basereg),(disp),(reg));
1040 /* ATTENTION: Always emit a REX byte, because the instruction size can
1041 be smaller when all register indexes are smaller than 7. */
1042 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1044 emit_byte_rex((reg),0,(basereg));
1045 *(cd->mcodeptr++) = 0x8b;
1046 emit_membase32(cd, (basereg),(disp),(reg));
1050 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1051 emit_rex(1,(reg),0,(basereg));
1052 *(cd->mcodeptr++) = 0x89;
1053 emit_membase(cd, (basereg),(disp),(reg));
1057 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1058 emit_rex(1,(reg),0,(basereg));
1059 *(cd->mcodeptr++) = 0x89;
1060 emit_membase32(cd, (basereg),(disp),(reg));
1064 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1065 emit_rex(0,(reg),0,(basereg));
1066 *(cd->mcodeptr++) = 0x89;
1067 emit_membase(cd, (basereg),(disp),(reg));
1071 /* Always emit a REX byte, because the instruction size can be smaller when */
1072 /* all register indexes are smaller than 7. */
1073 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1074 emit_byte_rex((reg),0,(basereg));
1075 *(cd->mcodeptr++) = 0x89;
1076 emit_membase32(cd, (basereg),(disp),(reg));
1080 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1081 emit_rex(1,(reg),(indexreg),(basereg));
1082 *(cd->mcodeptr++) = 0x8b;
1083 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1087 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1088 emit_rex(0,(reg),(indexreg),(basereg));
1089 *(cd->mcodeptr++) = 0x8b;
1090 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1094 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1095 emit_rex(1,(reg),(indexreg),(basereg));
1096 *(cd->mcodeptr++) = 0x89;
1097 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1101 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1102 emit_rex(0,(reg),(indexreg),(basereg));
1103 *(cd->mcodeptr++) = 0x89;
1104 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1108 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1109 *(cd->mcodeptr++) = 0x66;
1110 emit_rex(0,(reg),(indexreg),(basereg));
1111 *(cd->mcodeptr++) = 0x89;
1112 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1116 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1117 emit_byte_rex((reg),(indexreg),(basereg));
1118 *(cd->mcodeptr++) = 0x88;
1119 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1123 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1124 emit_rex(1,0,0,(basereg));
1125 *(cd->mcodeptr++) = 0xc7;
1126 emit_membase(cd, (basereg),(disp),0);
1131 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1132 emit_rex(1,0,0,(basereg));
1133 *(cd->mcodeptr++) = 0xc7;
1134 emit_membase32(cd, (basereg),(disp),0);
1139 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1140 emit_rex(0,0,0,(basereg));
1141 *(cd->mcodeptr++) = 0xc7;
1142 emit_membase(cd, (basereg),(disp),0);
1147 /* Always emit a REX byte, because the instruction size can be smaller when */
1148 /* all register indexes are smaller than 7. */
1149 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1150 emit_byte_rex(0,0,(basereg));
1151 *(cd->mcodeptr++) = 0xc7;
1152 emit_membase32(cd, (basereg),(disp),0);
1157 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1159 emit_rex(1,(dreg),0,(reg));
1160 *(cd->mcodeptr++) = 0x0f;
1161 *(cd->mcodeptr++) = 0xbe;
1162 /* XXX: why do reg and dreg have to be exchanged */
1163 emit_reg((dreg),(reg));
1167 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1169 emit_rex(1,(dreg),0,(reg));
1170 *(cd->mcodeptr++) = 0x0f;
1171 *(cd->mcodeptr++) = 0xbf;
1172 /* XXX: why do reg and dreg have to be exchanged */
1173 emit_reg((dreg),(reg));
1177 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1179 emit_rex(1,(dreg),0,(reg));
1180 *(cd->mcodeptr++) = 0x63;
1181 /* XXX: why do reg and dreg have to be exchanged */
1182 emit_reg((dreg),(reg));
1186 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1188 emit_rex(1,(dreg),0,(reg));
1189 *(cd->mcodeptr++) = 0x0f;
1190 *(cd->mcodeptr++) = 0xb7;
1191 /* XXX: why do reg and dreg have to be exchanged */
1192 emit_reg((dreg),(reg));
1196 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1197 emit_rex(1,(reg),(indexreg),(basereg));
1198 *(cd->mcodeptr++) = 0x0f;
1199 *(cd->mcodeptr++) = 0xbf;
1200 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1204 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1205 emit_rex(1,(reg),(indexreg),(basereg));
1206 *(cd->mcodeptr++) = 0x0f;
1207 *(cd->mcodeptr++) = 0xbe;
1208 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1212 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1213 emit_rex(1,(reg),(indexreg),(basereg));
1214 *(cd->mcodeptr++) = 0x0f;
1215 *(cd->mcodeptr++) = 0xb7;
1216 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1220 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1222 emit_rex(1,0,(indexreg),(basereg));
1223 *(cd->mcodeptr++) = 0xc7;
1224 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1229 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1231 emit_rex(0,0,(indexreg),(basereg));
1232 *(cd->mcodeptr++) = 0xc7;
1233 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1238 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1240 *(cd->mcodeptr++) = 0x66;
1241 emit_rex(0,0,(indexreg),(basereg));
1242 *(cd->mcodeptr++) = 0xc7;
1243 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1248 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1250 emit_rex(0,0,(indexreg),(basereg));
1251 *(cd->mcodeptr++) = 0xc6;
1252 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1260 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1262 emit_rex(1,(reg),0,(dreg));
1263 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1264 emit_reg((reg),(dreg));
1268 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1270 emit_rex(0,(reg),0,(dreg));
1271 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1272 emit_reg((reg),(dreg));
1276 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1278 emit_rex(1,(reg),0,(basereg));
1279 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1280 emit_membase(cd, (basereg),(disp),(reg));
1284 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1286 emit_rex(0,(reg),0,(basereg));
1287 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1288 emit_membase(cd, (basereg),(disp),(reg));
1292 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1294 emit_rex(1,(reg),0,(basereg));
1295 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1296 emit_membase(cd, (basereg),(disp),(reg));
1300 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1302 emit_rex(0,(reg),0,(basereg));
1303 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1304 emit_membase(cd, (basereg),(disp),(reg));
1308 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1310 emit_rex(1,0,0,(dreg));
1311 *(cd->mcodeptr++) = 0x83;
1312 emit_reg((opc),(dreg));
1315 emit_rex(1,0,0,(dreg));
1316 *(cd->mcodeptr++) = 0x81;
1317 emit_reg((opc),(dreg));
1323 void emit_alu_imm32_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1324 emit_rex(1,0,0,(dreg));
1325 *(cd->mcodeptr++) = 0x81;
1326 emit_reg((opc),(dreg));
1331 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1333 emit_rex(0,0,0,(dreg));
1334 *(cd->mcodeptr++) = 0x83;
1335 emit_reg((opc),(dreg));
1338 emit_rex(0,0,0,(dreg));
1339 *(cd->mcodeptr++) = 0x81;
1340 emit_reg((opc),(dreg));
1346 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1348 emit_rex(1,(basereg),0,0);
1349 *(cd->mcodeptr++) = 0x83;
1350 emit_membase(cd, (basereg),(disp),(opc));
1353 emit_rex(1,(basereg),0,0);
1354 *(cd->mcodeptr++) = 0x81;
1355 emit_membase(cd, (basereg),(disp),(opc));
1361 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1363 emit_rex(0,(basereg),0,0);
1364 *(cd->mcodeptr++) = 0x83;
1365 emit_membase(cd, (basereg),(disp),(opc));
1368 emit_rex(0,(basereg),0,0);
1369 *(cd->mcodeptr++) = 0x81;
1370 emit_membase(cd, (basereg),(disp),(opc));
1376 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1377 emit_rex(1,(reg),0,(dreg));
1378 *(cd->mcodeptr++) = 0x85;
1379 emit_reg((reg),(dreg));
1383 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1384 emit_rex(0,(reg),0,(dreg));
1385 *(cd->mcodeptr++) = 0x85;
1386 emit_reg((reg),(dreg));
1390 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1391 *(cd->mcodeptr++) = 0xf7;
1397 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1398 *(cd->mcodeptr++) = 0x66;
1399 *(cd->mcodeptr++) = 0xf7;
1405 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1406 *(cd->mcodeptr++) = 0xf6;
1412 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1413 emit_rex(1,(reg),0,(basereg));
1414 *(cd->mcodeptr++) = 0x8d;
1415 emit_membase(cd, (basereg),(disp),(reg));
1419 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1420 emit_rex(0,(reg),0,(basereg));
1421 *(cd->mcodeptr++) = 0x8d;
1422 emit_membase(cd, (basereg),(disp),(reg));
1427 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1429 emit_rex(0,0,0,(basereg));
1430 *(cd->mcodeptr++) = 0xff;
1431 emit_membase(cd, (basereg),(disp),0);
1436 void emit_cltd(codegendata *cd) {
1437 *(cd->mcodeptr++) = 0x99;
1441 void emit_cqto(codegendata *cd) {
1443 *(cd->mcodeptr++) = 0x99;
1448 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1449 emit_rex(1,(dreg),0,(reg));
1450 *(cd->mcodeptr++) = 0x0f;
1451 *(cd->mcodeptr++) = 0xaf;
1452 emit_reg((dreg),(reg));
1456 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1457 emit_rex(0,(dreg),0,(reg));
1458 *(cd->mcodeptr++) = 0x0f;
1459 *(cd->mcodeptr++) = 0xaf;
1460 emit_reg((dreg),(reg));
1464 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1465 emit_rex(1,(dreg),0,(basereg));
1466 *(cd->mcodeptr++) = 0x0f;
1467 *(cd->mcodeptr++) = 0xaf;
1468 emit_membase(cd, (basereg),(disp),(dreg));
1472 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1473 emit_rex(0,(dreg),0,(basereg));
1474 *(cd->mcodeptr++) = 0x0f;
1475 *(cd->mcodeptr++) = 0xaf;
1476 emit_membase(cd, (basereg),(disp),(dreg));
1480 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1481 if (IS_IMM8((imm))) {
1482 emit_rex(1,0,0,(dreg));
1483 *(cd->mcodeptr++) = 0x6b;
1487 emit_rex(1,0,0,(dreg));
1488 *(cd->mcodeptr++) = 0x69;
1495 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1496 if (IS_IMM8((imm))) {
1497 emit_rex(1,(dreg),0,(reg));
1498 *(cd->mcodeptr++) = 0x6b;
1499 emit_reg((dreg),(reg));
1502 emit_rex(1,(dreg),0,(reg));
1503 *(cd->mcodeptr++) = 0x69;
1504 emit_reg((dreg),(reg));
1510 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1511 if (IS_IMM8((imm))) {
1512 emit_rex(0,(dreg),0,(reg));
1513 *(cd->mcodeptr++) = 0x6b;
1514 emit_reg((dreg),(reg));
1517 emit_rex(0,(dreg),0,(reg));
1518 *(cd->mcodeptr++) = 0x69;
1519 emit_reg((dreg),(reg));
1525 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1526 if (IS_IMM8((imm))) {
1527 emit_rex(1,(dreg),0,(basereg));
1528 *(cd->mcodeptr++) = 0x6b;
1529 emit_membase(cd, (basereg),(disp),(dreg));
1532 emit_rex(1,(dreg),0,(basereg));
1533 *(cd->mcodeptr++) = 0x69;
1534 emit_membase(cd, (basereg),(disp),(dreg));
1540 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1541 if (IS_IMM8((imm))) {
1542 emit_rex(0,(dreg),0,(basereg));
1543 *(cd->mcodeptr++) = 0x6b;
1544 emit_membase(cd, (basereg),(disp),(dreg));
1547 emit_rex(0,(dreg),0,(basereg));
1548 *(cd->mcodeptr++) = 0x69;
1549 emit_membase(cd, (basereg),(disp),(dreg));
1555 void emit_idiv_reg(codegendata *cd, s8 reg) {
1556 emit_rex(1,0,0,(reg));
1557 *(cd->mcodeptr++) = 0xf7;
1562 void emit_idivl_reg(codegendata *cd, s8 reg) {
1563 emit_rex(0,0,0,(reg));
1564 *(cd->mcodeptr++) = 0xf7;
1570 void emit_ret(codegendata *cd) {
1571 *(cd->mcodeptr++) = 0xc3;
1579 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1580 emit_rex(1,0,0,(reg));
1581 *(cd->mcodeptr++) = 0xd3;
1582 emit_reg((opc),(reg));
1586 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1587 emit_rex(0,0,0,(reg));
1588 *(cd->mcodeptr++) = 0xd3;
1589 emit_reg((opc),(reg));
1593 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1594 emit_rex(1,0,0,(basereg));
1595 *(cd->mcodeptr++) = 0xd3;
1596 emit_membase(cd, (basereg),(disp),(opc));
1600 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1601 emit_rex(0,0,0,(basereg));
1602 *(cd->mcodeptr++) = 0xd3;
1603 emit_membase(cd, (basereg),(disp),(opc));
1607 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1609 emit_rex(1,0,0,(dreg));
1610 *(cd->mcodeptr++) = 0xd1;
1611 emit_reg((opc),(dreg));
1613 emit_rex(1,0,0,(dreg));
1614 *(cd->mcodeptr++) = 0xc1;
1615 emit_reg((opc),(dreg));
1621 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1623 emit_rex(0,0,0,(dreg));
1624 *(cd->mcodeptr++) = 0xd1;
1625 emit_reg((opc),(dreg));
1627 emit_rex(0,0,0,(dreg));
1628 *(cd->mcodeptr++) = 0xc1;
1629 emit_reg((opc),(dreg));
1635 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1637 emit_rex(1,0,0,(basereg));
1638 *(cd->mcodeptr++) = 0xd1;
1639 emit_membase(cd, (basereg),(disp),(opc));
1641 emit_rex(1,0,0,(basereg));
1642 *(cd->mcodeptr++) = 0xc1;
1643 emit_membase(cd, (basereg),(disp),(opc));
1649 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1651 emit_rex(0,0,0,(basereg));
1652 *(cd->mcodeptr++) = 0xd1;
1653 emit_membase(cd, (basereg),(disp),(opc));
1655 emit_rex(0,0,0,(basereg));
1656 *(cd->mcodeptr++) = 0xc1;
1657 emit_membase(cd, (basereg),(disp),(opc));
1667 void emit_jmp_imm(codegendata *cd, s8 imm) {
1668 *(cd->mcodeptr++) = 0xe9;
1673 void emit_jmp_reg(codegendata *cd, s8 reg) {
1674 emit_rex(0,0,0,(reg));
1675 *(cd->mcodeptr++) = 0xff;
1680 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1681 *(cd->mcodeptr++) = 0x0f;
1682 *(cd->mcodeptr++) = (0x80 + (opc));
1689 * conditional set and move operations
1692 /* we need the rex byte to get all low bytes */
1693 void emit_setcc_reg(codegendata *cd, s8 opc, s8 reg) {
1694 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1695 *(cd->mcodeptr++) = 0x0f;
1696 *(cd->mcodeptr++) = (0x90 + (opc));
1701 /* we need the rex byte to get all low bytes */
1702 void emit_setcc_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1703 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1704 *(cd->mcodeptr++) = 0x0f;
1705 *(cd->mcodeptr++) = (0x90 + (opc));
1706 emit_membase(cd, (basereg),(disp),0);
1710 void emit_cmovcc_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1712 emit_rex(1,(dreg),0,(reg));
1713 *(cd->mcodeptr++) = 0x0f;
1714 *(cd->mcodeptr++) = (0x40 + (opc));
1715 emit_reg((dreg),(reg));
1719 void emit_cmovccl_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1721 emit_rex(0,(dreg),0,(reg));
1722 *(cd->mcodeptr++) = 0x0f;
1723 *(cd->mcodeptr++) = (0x40 + (opc));
1724 emit_reg((dreg),(reg));
1729 void emit_neg_reg(codegendata *cd, s8 reg)
1731 emit_rex(1,0,0,(reg));
1732 *(cd->mcodeptr++) = 0xf7;
1737 void emit_negl_reg(codegendata *cd, s8 reg)
1739 emit_rex(0,0,0,(reg));
1740 *(cd->mcodeptr++) = 0xf7;
1745 void emit_push_reg(codegendata *cd, s8 reg) {
1746 emit_rex(0,0,0,(reg));
1747 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1751 void emit_push_imm(codegendata *cd, s8 imm) {
1752 *(cd->mcodeptr++) = 0x68;
1757 void emit_pop_reg(codegendata *cd, s8 reg) {
1758 emit_rex(0,0,0,(reg));
1759 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1763 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1764 emit_rex(1,(reg),0,(dreg));
1765 *(cd->mcodeptr++) = 0x87;
1766 emit_reg((reg),(dreg));
1770 void emit_nop(codegendata *cd) {
1771 *(cd->mcodeptr++) = 0x90;
1779 void emit_call_reg(codegendata *cd, s8 reg) {
1780 emit_rex(1,0,0,(reg));
1781 *(cd->mcodeptr++) = 0xff;
1786 void emit_call_imm(codegendata *cd, s8 imm) {
1787 *(cd->mcodeptr++) = 0xe8;
1792 void emit_call_mem(codegendata *cd, ptrint mem)
1794 *(cd->mcodeptr++) = 0xff;
1801 * floating point instructions (SSE2)
1803 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1804 *(cd->mcodeptr++) = 0xf2;
1805 emit_rex(0,(dreg),0,(reg));
1806 *(cd->mcodeptr++) = 0x0f;
1807 *(cd->mcodeptr++) = 0x58;
1808 emit_reg((dreg),(reg));
1812 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1813 *(cd->mcodeptr++) = 0xf3;
1814 emit_rex(0,(dreg),0,(reg));
1815 *(cd->mcodeptr++) = 0x0f;
1816 *(cd->mcodeptr++) = 0x58;
1817 emit_reg((dreg),(reg));
1821 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1822 *(cd->mcodeptr++) = 0xf3;
1823 emit_rex(1,(dreg),0,(reg));
1824 *(cd->mcodeptr++) = 0x0f;
1825 *(cd->mcodeptr++) = 0x2a;
1826 emit_reg((dreg),(reg));
1830 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1831 *(cd->mcodeptr++) = 0xf3;
1832 emit_rex(0,(dreg),0,(reg));
1833 *(cd->mcodeptr++) = 0x0f;
1834 *(cd->mcodeptr++) = 0x2a;
1835 emit_reg((dreg),(reg));
1839 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1840 *(cd->mcodeptr++) = 0xf2;
1841 emit_rex(1,(dreg),0,(reg));
1842 *(cd->mcodeptr++) = 0x0f;
1843 *(cd->mcodeptr++) = 0x2a;
1844 emit_reg((dreg),(reg));
1848 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1849 *(cd->mcodeptr++) = 0xf2;
1850 emit_rex(0,(dreg),0,(reg));
1851 *(cd->mcodeptr++) = 0x0f;
1852 *(cd->mcodeptr++) = 0x2a;
1853 emit_reg((dreg),(reg));
1857 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1858 *(cd->mcodeptr++) = 0xf3;
1859 emit_rex(0,(dreg),0,(reg));
1860 *(cd->mcodeptr++) = 0x0f;
1861 *(cd->mcodeptr++) = 0x5a;
1862 emit_reg((dreg),(reg));
1866 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1867 *(cd->mcodeptr++) = 0xf2;
1868 emit_rex(0,(dreg),0,(reg));
1869 *(cd->mcodeptr++) = 0x0f;
1870 *(cd->mcodeptr++) = 0x5a;
1871 emit_reg((dreg),(reg));
1875 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1876 *(cd->mcodeptr++) = 0xf3;
1877 emit_rex(1,(dreg),0,(reg));
1878 *(cd->mcodeptr++) = 0x0f;
1879 *(cd->mcodeptr++) = 0x2c;
1880 emit_reg((dreg),(reg));
1884 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1885 *(cd->mcodeptr++) = 0xf3;
1886 emit_rex(0,(dreg),0,(reg));
1887 *(cd->mcodeptr++) = 0x0f;
1888 *(cd->mcodeptr++) = 0x2c;
1889 emit_reg((dreg),(reg));
1893 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1894 *(cd->mcodeptr++) = 0xf2;
1895 emit_rex(1,(dreg),0,(reg));
1896 *(cd->mcodeptr++) = 0x0f;
1897 *(cd->mcodeptr++) = 0x2c;
1898 emit_reg((dreg),(reg));
1902 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1903 *(cd->mcodeptr++) = 0xf2;
1904 emit_rex(0,(dreg),0,(reg));
1905 *(cd->mcodeptr++) = 0x0f;
1906 *(cd->mcodeptr++) = 0x2c;
1907 emit_reg((dreg),(reg));
1911 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1912 *(cd->mcodeptr++) = 0xf3;
1913 emit_rex(0,(dreg),0,(reg));
1914 *(cd->mcodeptr++) = 0x0f;
1915 *(cd->mcodeptr++) = 0x5e;
1916 emit_reg((dreg),(reg));
1920 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1921 *(cd->mcodeptr++) = 0xf2;
1922 emit_rex(0,(dreg),0,(reg));
1923 *(cd->mcodeptr++) = 0x0f;
1924 *(cd->mcodeptr++) = 0x5e;
1925 emit_reg((dreg),(reg));
1929 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1930 *(cd->mcodeptr++) = 0x66;
1931 emit_rex(1,(freg),0,(reg));
1932 *(cd->mcodeptr++) = 0x0f;
1933 *(cd->mcodeptr++) = 0x6e;
1934 emit_reg((freg),(reg));
1938 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1939 *(cd->mcodeptr++) = 0x66;
1940 emit_rex(1,(freg),0,(reg));
1941 *(cd->mcodeptr++) = 0x0f;
1942 *(cd->mcodeptr++) = 0x7e;
1943 emit_reg((freg),(reg));
1947 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1948 *(cd->mcodeptr++) = 0x66;
1949 emit_rex(0,(reg),0,(basereg));
1950 *(cd->mcodeptr++) = 0x0f;
1951 *(cd->mcodeptr++) = 0x7e;
1952 emit_membase(cd, (basereg),(disp),(reg));
1956 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1957 *(cd->mcodeptr++) = 0x66;
1958 emit_rex(0,(reg),(indexreg),(basereg));
1959 *(cd->mcodeptr++) = 0x0f;
1960 *(cd->mcodeptr++) = 0x7e;
1961 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1965 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1966 *(cd->mcodeptr++) = 0x66;
1967 emit_rex(1,(dreg),0,(basereg));
1968 *(cd->mcodeptr++) = 0x0f;
1969 *(cd->mcodeptr++) = 0x6e;
1970 emit_membase(cd, (basereg),(disp),(dreg));
1974 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1975 *(cd->mcodeptr++) = 0x66;
1976 emit_rex(0,(dreg),0,(basereg));
1977 *(cd->mcodeptr++) = 0x0f;
1978 *(cd->mcodeptr++) = 0x6e;
1979 emit_membase(cd, (basereg),(disp),(dreg));
1983 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
1984 *(cd->mcodeptr++) = 0x66;
1985 emit_rex(0,(dreg),(indexreg),(basereg));
1986 *(cd->mcodeptr++) = 0x0f;
1987 *(cd->mcodeptr++) = 0x6e;
1988 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
1992 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1993 *(cd->mcodeptr++) = 0xf3;
1994 emit_rex(0,(dreg),0,(reg));
1995 *(cd->mcodeptr++) = 0x0f;
1996 *(cd->mcodeptr++) = 0x7e;
1997 emit_reg((dreg),(reg));
2001 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2002 *(cd->mcodeptr++) = 0x66;
2003 emit_rex(0,(reg),0,(basereg));
2004 *(cd->mcodeptr++) = 0x0f;
2005 *(cd->mcodeptr++) = 0xd6;
2006 emit_membase(cd, (basereg),(disp),(reg));
2010 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2011 *(cd->mcodeptr++) = 0xf3;
2012 emit_rex(0,(dreg),0,(basereg));
2013 *(cd->mcodeptr++) = 0x0f;
2014 *(cd->mcodeptr++) = 0x7e;
2015 emit_membase(cd, (basereg),(disp),(dreg));
2019 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2020 *(cd->mcodeptr++) = 0xf3;
2021 emit_rex(0,(reg),0,(dreg));
2022 *(cd->mcodeptr++) = 0x0f;
2023 *(cd->mcodeptr++) = 0x10;
2024 emit_reg((reg),(dreg));
2028 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2029 *(cd->mcodeptr++) = 0xf2;
2030 emit_rex(0,(reg),0,(dreg));
2031 *(cd->mcodeptr++) = 0x0f;
2032 *(cd->mcodeptr++) = 0x10;
2033 emit_reg((reg),(dreg));
2037 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2038 *(cd->mcodeptr++) = 0xf3;
2039 emit_rex(0,(reg),0,(basereg));
2040 *(cd->mcodeptr++) = 0x0f;
2041 *(cd->mcodeptr++) = 0x11;
2042 emit_membase(cd, (basereg),(disp),(reg));
2046 /* Always emit a REX byte, because the instruction size can be smaller when */
2047 /* all register indexes are smaller than 7. */
2048 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2049 *(cd->mcodeptr++) = 0xf3;
2050 emit_byte_rex((reg),0,(basereg));
2051 *(cd->mcodeptr++) = 0x0f;
2052 *(cd->mcodeptr++) = 0x11;
2053 emit_membase32(cd, (basereg),(disp),(reg));
2057 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2058 *(cd->mcodeptr++) = 0xf2;
2059 emit_rex(0,(reg),0,(basereg));
2060 *(cd->mcodeptr++) = 0x0f;
2061 *(cd->mcodeptr++) = 0x11;
2062 emit_membase(cd, (basereg),(disp),(reg));
2066 /* Always emit a REX byte, because the instruction size can be smaller when */
2067 /* all register indexes are smaller than 7. */
2068 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2069 *(cd->mcodeptr++) = 0xf2;
2070 emit_byte_rex((reg),0,(basereg));
2071 *(cd->mcodeptr++) = 0x0f;
2072 *(cd->mcodeptr++) = 0x11;
2073 emit_membase32(cd, (basereg),(disp),(reg));
2077 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2078 *(cd->mcodeptr++) = 0xf3;
2079 emit_rex(0,(dreg),0,(basereg));
2080 *(cd->mcodeptr++) = 0x0f;
2081 *(cd->mcodeptr++) = 0x10;
2082 emit_membase(cd, (basereg),(disp),(dreg));
2086 /* Always emit a REX byte, because the instruction size can be smaller when */
2087 /* all register indexes are smaller than 7. */
2088 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2089 *(cd->mcodeptr++) = 0xf3;
2090 emit_byte_rex((dreg),0,(basereg));
2091 *(cd->mcodeptr++) = 0x0f;
2092 *(cd->mcodeptr++) = 0x10;
2093 emit_membase32(cd, (basereg),(disp),(dreg));
2097 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2099 emit_rex(0,(dreg),0,(basereg));
2100 *(cd->mcodeptr++) = 0x0f;
2101 *(cd->mcodeptr++) = 0x12;
2102 emit_membase(cd, (basereg),(disp),(dreg));
2106 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2108 emit_rex(0,(reg),0,(basereg));
2109 *(cd->mcodeptr++) = 0x0f;
2110 *(cd->mcodeptr++) = 0x13;
2111 emit_membase(cd, (basereg),(disp),(reg));
2115 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2116 *(cd->mcodeptr++) = 0xf2;
2117 emit_rex(0,(dreg),0,(basereg));
2118 *(cd->mcodeptr++) = 0x0f;
2119 *(cd->mcodeptr++) = 0x10;
2120 emit_membase(cd, (basereg),(disp),(dreg));
2124 /* Always emit a REX byte, because the instruction size can be smaller when */
2125 /* all register indexes are smaller than 7. */
2126 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2127 *(cd->mcodeptr++) = 0xf2;
2128 emit_byte_rex((dreg),0,(basereg));
2129 *(cd->mcodeptr++) = 0x0f;
2130 *(cd->mcodeptr++) = 0x10;
2131 emit_membase32(cd, (basereg),(disp),(dreg));
2135 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2137 *(cd->mcodeptr++) = 0x66;
2138 emit_rex(0,(dreg),0,(basereg));
2139 *(cd->mcodeptr++) = 0x0f;
2140 *(cd->mcodeptr++) = 0x12;
2141 emit_membase(cd, (basereg),(disp),(dreg));
2145 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2147 *(cd->mcodeptr++) = 0x66;
2148 emit_rex(0,(reg),0,(basereg));
2149 *(cd->mcodeptr++) = 0x0f;
2150 *(cd->mcodeptr++) = 0x13;
2151 emit_membase(cd, (basereg),(disp),(reg));
2155 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2156 *(cd->mcodeptr++) = 0xf3;
2157 emit_rex(0,(reg),(indexreg),(basereg));
2158 *(cd->mcodeptr++) = 0x0f;
2159 *(cd->mcodeptr++) = 0x11;
2160 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2164 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2165 *(cd->mcodeptr++) = 0xf2;
2166 emit_rex(0,(reg),(indexreg),(basereg));
2167 *(cd->mcodeptr++) = 0x0f;
2168 *(cd->mcodeptr++) = 0x11;
2169 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2173 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2174 *(cd->mcodeptr++) = 0xf3;
2175 emit_rex(0,(dreg),(indexreg),(basereg));
2176 *(cd->mcodeptr++) = 0x0f;
2177 *(cd->mcodeptr++) = 0x10;
2178 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2182 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2183 *(cd->mcodeptr++) = 0xf2;
2184 emit_rex(0,(dreg),(indexreg),(basereg));
2185 *(cd->mcodeptr++) = 0x0f;
2186 *(cd->mcodeptr++) = 0x10;
2187 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2191 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2192 *(cd->mcodeptr++) = 0xf3;
2193 emit_rex(0,(dreg),0,(reg));
2194 *(cd->mcodeptr++) = 0x0f;
2195 *(cd->mcodeptr++) = 0x59;
2196 emit_reg((dreg),(reg));
2200 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2201 *(cd->mcodeptr++) = 0xf2;
2202 emit_rex(0,(dreg),0,(reg));
2203 *(cd->mcodeptr++) = 0x0f;
2204 *(cd->mcodeptr++) = 0x59;
2205 emit_reg((dreg),(reg));
2209 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2210 *(cd->mcodeptr++) = 0xf3;
2211 emit_rex(0,(dreg),0,(reg));
2212 *(cd->mcodeptr++) = 0x0f;
2213 *(cd->mcodeptr++) = 0x5c;
2214 emit_reg((dreg),(reg));
2218 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2219 *(cd->mcodeptr++) = 0xf2;
2220 emit_rex(0,(dreg),0,(reg));
2221 *(cd->mcodeptr++) = 0x0f;
2222 *(cd->mcodeptr++) = 0x5c;
2223 emit_reg((dreg),(reg));
2227 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2228 emit_rex(0,(dreg),0,(reg));
2229 *(cd->mcodeptr++) = 0x0f;
2230 *(cd->mcodeptr++) = 0x2e;
2231 emit_reg((dreg),(reg));
2235 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2236 *(cd->mcodeptr++) = 0x66;
2237 emit_rex(0,(dreg),0,(reg));
2238 *(cd->mcodeptr++) = 0x0f;
2239 *(cd->mcodeptr++) = 0x2e;
2240 emit_reg((dreg),(reg));
2244 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2245 emit_rex(0,(dreg),0,(reg));
2246 *(cd->mcodeptr++) = 0x0f;
2247 *(cd->mcodeptr++) = 0x57;
2248 emit_reg((dreg),(reg));
2252 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2253 emit_rex(0,(dreg),0,(basereg));
2254 *(cd->mcodeptr++) = 0x0f;
2255 *(cd->mcodeptr++) = 0x57;
2256 emit_membase(cd, (basereg),(disp),(dreg));
2260 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2261 *(cd->mcodeptr++) = 0x66;
2262 emit_rex(0,(dreg),0,(reg));
2263 *(cd->mcodeptr++) = 0x0f;
2264 *(cd->mcodeptr++) = 0x57;
2265 emit_reg((dreg),(reg));
2269 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2270 *(cd->mcodeptr++) = 0x66;
2271 emit_rex(0,(dreg),0,(basereg));
2272 *(cd->mcodeptr++) = 0x0f;
2273 *(cd->mcodeptr++) = 0x57;
2274 emit_membase(cd, (basereg),(disp),(dreg));
2278 /* system instructions ********************************************************/
2280 void emit_rdtsc(codegendata *cd)
2282 *(cd->mcodeptr++) = 0x0f;
2283 *(cd->mcodeptr++) = 0x31;
2288 * These are local overrides for various environment variables in Emacs.
2289 * Please do not remove this and leave it at the end of the file, where
2290 * Emacs will automagically detect them.
2291 * ---------------------------------------------------------------------
2294 * indent-tabs-mode: t