1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
35 #include "vm/jit/x86_64/codegen.h"
36 #include "vm/jit/x86_64/emit.h"
38 #include "mm/memory.h"
40 #include "threads/lock-common.h"
42 #include "vm/jit/abi.h"
43 #include "vm/jit/abi-asm.h"
44 #include "vm/jit/asmpart.h"
45 #include "vm/jit/codegen-common.h"
46 #include "vm/jit/emit-common.h"
47 #include "vm/jit/jit.h"
48 #include "vm/jit/patcher-common.h"
49 #include "vm/jit/replace.h"
50 #include "vm/jit/trace.h"
51 #include "vm/jit/trap.h"
53 #include "vmcore/options.h"
56 /* emit_load *******************************************************************
58 Emits a possible load of an operand.
60 *******************************************************************************/
62 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
68 /* get required compiler data */
72 if (IS_INMEMORY(src->flags)) {
75 disp = src->vv.regoff;
79 M_ILD(tempreg, REG_SP, disp);
83 M_LLD(tempreg, REG_SP, disp);
86 M_FLD(tempreg, REG_SP, disp);
89 M_DLD(tempreg, REG_SP, disp);
92 vm_abort("emit_load: unknown type %d", src->type);
104 /* emit_store ******************************************************************
106 This function generates the code to store the result of an
107 operation back into a spilled pseudo-variable. If the
108 pseudo-variable has not been spilled in the first place, this
109 function will generate nothing.
111 *******************************************************************************/
113 void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
118 /* get required compiler data */
122 if (IS_INMEMORY(dst->flags)) {
125 disp = dst->vv.regoff;
131 M_LST(d, REG_SP, disp);
134 M_FST(d, REG_SP, disp);
137 M_DST(d, REG_SP, disp);
140 vm_abort("emit_store: unknown type %d", dst->type);
146 /* emit_copy *******************************************************************
148 Generates a register/memory to register/memory copy.
150 *******************************************************************************/
152 void emit_copy(jitdata *jd, instruction *iptr)
159 /* get required compiler data */
163 /* get source and destination variables */
165 src = VAROP(iptr->s1);
166 dst = VAROP(iptr->dst);
168 if ((src->vv.regoff != dst->vv.regoff) ||
169 ((src->flags ^ dst->flags) & INMEMORY)) {
171 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
172 /* emit nothing, as the value won't be used anyway */
176 /* If one of the variables resides in memory, we can eliminate
177 the register move from/to the temporary register with the
178 order of getting the destination register and the load. */
180 if (IS_INMEMORY(src->flags)) {
181 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
182 s1 = emit_load(jd, iptr, src, d);
185 s1 = emit_load(jd, iptr, src, REG_IFTMP);
186 d = codegen_reg_of_var(iptr->opc, dst, s1);
201 vm_abort("emit_copy: unknown type %d", src->type);
205 emit_store(jd, iptr, dst, d);
210 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
213 switch (iptr->flags.fields.condition) {
237 /* emit_branch *****************************************************************
239 Emits the code for conditional and unconditional branchs.
241 *******************************************************************************/
243 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
247 /* NOTE: A displacement overflow cannot happen. */
249 /* check which branch to generate */
251 if (condition == BRANCH_UNCONDITIONAL) {
253 /* calculate the different displacements */
255 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
257 M_JMP_IMM(branchdisp);
260 /* calculate the different displacements */
262 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
296 vm_abort("emit_branch: unknown condition %d", condition);
302 /* emit_arithmetic_check *******************************************************
304 Emit an ArithmeticException check.
306 *******************************************************************************/
308 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
310 if (INSTRUCTION_MUST_CHECK(iptr)) {
313 M_ALD_MEM(reg, TRAP_ArithmeticException);
318 /* emit_arrayindexoutofbounds_check ********************************************
320 Emit a ArrayIndexOutOfBoundsException check.
322 *******************************************************************************/
324 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
326 if (INSTRUCTION_MUST_CHECK(iptr)) {
327 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
328 M_ICMP(REG_ITMP3, s2);
330 M_ALD_MEM(s2, TRAP_ArrayIndexOutOfBoundsException);
335 /* emit_arraystore_check *******************************************************
337 Emit an ArrayStoreException check.
339 *******************************************************************************/
341 void emit_arraystore_check(codegendata *cd, instruction *iptr)
343 if (INSTRUCTION_MUST_CHECK(iptr)) {
346 M_ALD_MEM(REG_RESULT, TRAP_ArrayStoreException);
351 /* emit_classcast_check ********************************************************
353 Emit a ClassCastException check.
355 *******************************************************************************/
357 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
359 if (INSTRUCTION_MUST_CHECK(iptr)) {
371 vm_abort("emit_classcast_check: unknown condition %d", condition);
373 M_ALD_MEM(s1, TRAP_ClassCastException);
378 /* emit_nullpointer_check ******************************************************
380 Emit a NullPointerException check.
382 *******************************************************************************/
384 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
386 if (INSTRUCTION_MUST_CHECK(iptr)) {
389 M_ALD_MEM(reg, TRAP_NullPointerException);
394 /* emit_exception_check ********************************************************
396 Emit an Exception check.
398 *******************************************************************************/
400 void emit_exception_check(codegendata *cd, instruction *iptr)
402 if (INSTRUCTION_MUST_CHECK(iptr)) {
405 M_ALD_MEM(REG_RESULT, TRAP_CHECK_EXCEPTION);
410 /* emit_trap_compiler **********************************************************
412 Emit a trap instruction which calls the JIT compiler.
414 *******************************************************************************/
416 void emit_trap_compiler(codegendata *cd)
418 M_ALD_MEM(REG_METHODPTR, TRAP_COMPILER);
422 /* emit_trap *******************************************************************
424 Emit a trap instruction and return the original machine code.
426 *******************************************************************************/
428 uint32_t emit_trap(codegendata *cd)
432 /* Get machine code which is patched back in later. The trap is 2
435 mcode = *((uint16_t *) cd->mcodeptr);
437 /* XXX This needs to be change to INT3 when the debugging problems
438 with gdb are resolved. */
446 /* emit_verbosecall_enter ******************************************************
448 Generates the code for the call trace.
450 *******************************************************************************/
453 void emit_verbosecall_enter(jitdata *jd)
463 /* get required compiler data */
472 /* mark trace code */
476 /* keep 16-byte stack alignment */
478 stackframesize = md->paramcount + ARG_CNT + TMP_CNT;
479 ALIGN_2(stackframesize);
481 M_LSUB_IMM(stackframesize * 8, REG_SP);
483 /* save argument registers */
485 for (i = 0; i < md->paramcount; i++) {
486 if (!md->params[i].inmemory) {
487 s = md->params[i].regoff;
489 switch (md->paramtypes[i].type) {
493 M_LST(s, REG_SP, i * 8);
497 M_DST(s, REG_SP, i * 8);
503 /* save all argument and temporary registers for leaf methods */
505 if (code_is_leafmethod(code)) {
506 for (i = 0; i < INT_ARG_CNT; i++)
507 M_LST(abi_registers_integer_argument[i], REG_SP, (md->paramcount + i) * 8);
509 for (i = 0; i < FLT_ARG_CNT; i++)
510 M_DST(abi_registers_float_argument[i], REG_SP, (md->paramcount + INT_ARG_CNT + i) * 8);
512 for (i = 0; i < INT_TMP_CNT; i++)
513 M_LST(rd->tmpintregs[i], REG_SP, (md->paramcount + ARG_CNT + i) * 8);
515 for (i = 0; i < FLT_TMP_CNT; i++)
516 M_DST(rd->tmpfltregs[i], REG_SP, (md->paramcount + ARG_CNT + INT_TMP_CNT + i) * 8);
519 M_MOV_IMM(m, REG_A0);
520 M_MOV(REG_SP, REG_A1);
521 M_MOV(REG_SP, REG_A2);
522 M_AADD_IMM((stackframesize + cd->stackframesize + 1) * 8, REG_A2);
523 M_MOV_IMM(trace_java_call_enter, REG_ITMP1);
526 /* restore argument registers */
528 for (i = 0; i < md->paramcount; i++) {
529 if (!md->params[i].inmemory) {
530 s = md->params[i].regoff;
532 switch (md->paramtypes[i].type) {
536 M_LLD(s, REG_SP, i * 8);
540 M_DLD(s, REG_SP, i * 8);
547 /* restore all argument and temporary registers for leaf methods */
549 if (code_is_leafmethod(code)) {
550 for (i = 0; i < INT_ARG_CNT; i++)
551 M_LLD(abi_registers_integer_argument[i], REG_SP, (md->paramcount + i) * 8);
553 for (i = 0; i < FLT_ARG_CNT; i++)
554 M_DLD(abi_registers_float_argument[i], REG_SP, (md->paramcount + INT_ARG_CNT + i) * 8);
556 for (i = 0; i < INT_TMP_CNT; i++)
557 M_LLD(rd->tmpintregs[i], REG_SP, (md->paramcount + ARG_CNT + i) * 8);
559 for (i = 0; i < FLT_TMP_CNT; i++)
560 M_DLD(rd->tmpfltregs[i], REG_SP, (md->paramcount + ARG_CNT + INT_TMP_CNT + i) * 8);
563 M_LADD_IMM(stackframesize * 8, REG_SP);
565 /* mark trace code */
569 #endif /* !defined(NDEBUG) */
572 /* emit_verbosecall_exit *******************************************************
574 Generates the code for the call trace.
576 *******************************************************************************/
579 void emit_verbosecall_exit(jitdata *jd)
586 /* get required compiler data */
594 /* mark trace code */
598 /* keep 16-byte stack alignment */
600 M_ASUB_IMM(2 * 8, REG_SP);
602 /* save return value */
604 switch (md->returntype.type) {
608 M_LST(REG_RESULT, REG_SP, 0 * 8);
612 M_DST(REG_FRESULT, REG_SP, 0 * 8);
616 M_MOV_IMM(m, REG_A0);
617 M_MOV(REG_SP, REG_A1);
619 M_MOV_IMM(trace_java_call_exit, REG_ITMP1);
622 /* restore return value */
624 switch (md->returntype.type) {
628 M_LLD(REG_RESULT, REG_SP, 0 * 8);
632 M_DLD(REG_FRESULT, REG_SP, 0 * 8);
636 M_AADD_IMM(2 * 8, REG_SP);
638 /* mark trace code */
642 #endif /* !defined(NDEBUG) */
645 /* code generation functions **************************************************/
647 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
649 if ((basereg == REG_SP) || (basereg == R12)) {
651 emit_address_byte(0, dreg, REG_SP);
652 emit_address_byte(0, REG_SP, REG_SP);
654 } else if (IS_IMM8(disp)) {
655 emit_address_byte(1, dreg, REG_SP);
656 emit_address_byte(0, REG_SP, REG_SP);
660 emit_address_byte(2, dreg, REG_SP);
661 emit_address_byte(0, REG_SP, REG_SP);
665 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
666 emit_address_byte(0,(dreg),(basereg));
668 } else if ((basereg) == RIP) {
669 emit_address_byte(0, dreg, RBP);
674 emit_address_byte(1, dreg, basereg);
678 emit_address_byte(2, dreg, basereg);
685 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
687 if ((basereg == REG_SP) || (basereg == R12)) {
688 emit_address_byte(2, dreg, REG_SP);
689 emit_address_byte(0, REG_SP, REG_SP);
693 emit_address_byte(2, dreg, basereg);
699 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
702 emit_address_byte(0, reg, 4);
703 emit_address_byte(scale, indexreg, 5);
706 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
707 emit_address_byte(0, reg, 4);
708 emit_address_byte(scale, indexreg, basereg);
710 else if (IS_IMM8(disp)) {
711 emit_address_byte(1, reg, 4);
712 emit_address_byte(scale, indexreg, basereg);
716 emit_address_byte(2, reg, 4);
717 emit_address_byte(scale, indexreg, basereg);
723 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
726 varinfo *v_s1,*v_s2,*v_dst;
729 /* get required compiler data */
733 v_s1 = VAROP(iptr->s1);
734 v_s2 = VAROP(iptr->sx.s23.s2);
735 v_dst = VAROP(iptr->dst);
737 s1 = v_s1->vv.regoff;
738 s2 = v_s2->vv.regoff;
739 d = v_dst->vv.regoff;
741 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
743 if (IS_INMEMORY(v_dst->flags)) {
744 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
746 M_ILD(RCX, REG_SP, s2);
747 emit_shiftl_membase(cd, shift_op, REG_SP, d);
750 M_ILD(RCX, REG_SP, s2);
751 M_ILD(REG_ITMP2, REG_SP, s1);
752 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
753 M_IST(REG_ITMP2, REG_SP, d);
756 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
757 /* s1 may be equal to RCX */
760 M_ILD(REG_ITMP1, REG_SP, s2);
761 M_IST(s1, REG_SP, d);
762 M_INTMOVE(REG_ITMP1, RCX);
765 M_IST(s1, REG_SP, d);
766 M_ILD(RCX, REG_SP, s2);
770 M_ILD(RCX, REG_SP, s2);
771 M_IST(s1, REG_SP, d);
774 emit_shiftl_membase(cd, shift_op, REG_SP, d);
776 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
779 emit_shiftl_membase(cd, shift_op, REG_SP, d);
783 M_ILD(REG_ITMP2, REG_SP, s1);
784 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
785 M_IST(REG_ITMP2, REG_SP, d);
789 /* s1 may be equal to RCX */
790 M_IST(s1, REG_SP, d);
792 emit_shiftl_membase(cd, shift_op, REG_SP, d);
795 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
803 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
804 M_ILD(RCX, REG_SP, s2);
805 M_ILD(d, REG_SP, s1);
806 emit_shiftl_reg(cd, shift_op, d);
808 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
809 /* s1 may be equal to RCX */
811 M_ILD(RCX, REG_SP, s2);
812 emit_shiftl_reg(cd, shift_op, d);
814 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
816 M_ILD(d, REG_SP, s1);
817 emit_shiftl_reg(cd, shift_op, d);
820 /* s1 may be equal to RCX */
823 /* d cannot be used to backup s1 since this would
825 M_INTMOVE(s1, REG_ITMP3);
827 M_INTMOVE(REG_ITMP3, d);
835 /* d may be equal to s2 */
839 emit_shiftl_reg(cd, shift_op, d);
843 M_INTMOVE(REG_ITMP3, RCX);
845 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
850 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
853 varinfo *v_s1,*v_s2,*v_dst;
856 /* get required compiler data */
860 v_s1 = VAROP(iptr->s1);
861 v_s2 = VAROP(iptr->sx.s23.s2);
862 v_dst = VAROP(iptr->dst);
864 s1 = v_s1->vv.regoff;
865 s2 = v_s2->vv.regoff;
866 d = v_dst->vv.regoff;
868 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
870 if (IS_INMEMORY(v_dst->flags)) {
871 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
873 M_ILD(RCX, REG_SP, s2);
874 emit_shift_membase(cd, shift_op, REG_SP, d);
877 M_ILD(RCX, REG_SP, s2);
878 M_LLD(REG_ITMP2, REG_SP, s1);
879 emit_shift_reg(cd, shift_op, REG_ITMP2);
880 M_LST(REG_ITMP2, REG_SP, d);
883 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
884 /* s1 may be equal to RCX */
887 M_ILD(REG_ITMP1, REG_SP, s2);
888 M_LST(s1, REG_SP, d);
889 M_INTMOVE(REG_ITMP1, RCX);
892 M_LST(s1, REG_SP, d);
893 M_ILD(RCX, REG_SP, s2);
897 M_ILD(RCX, REG_SP, s2);
898 M_LST(s1, REG_SP, d);
901 emit_shift_membase(cd, shift_op, REG_SP, d);
903 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
906 emit_shift_membase(cd, shift_op, REG_SP, d);
910 M_LLD(REG_ITMP2, REG_SP, s1);
911 emit_shift_reg(cd, shift_op, REG_ITMP2);
912 M_LST(REG_ITMP2, REG_SP, d);
916 /* s1 may be equal to RCX */
917 M_LST(s1, REG_SP, d);
919 emit_shift_membase(cd, shift_op, REG_SP, d);
922 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
930 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
931 M_ILD(RCX, REG_SP, s2);
932 M_LLD(d, REG_SP, s1);
933 emit_shift_reg(cd, shift_op, d);
935 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
936 /* s1 may be equal to RCX */
938 M_ILD(RCX, REG_SP, s2);
939 emit_shift_reg(cd, shift_op, d);
941 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
943 M_LLD(d, REG_SP, s1);
944 emit_shift_reg(cd, shift_op, d);
947 /* s1 may be equal to RCX */
950 /* d cannot be used to backup s1 since this would
952 M_INTMOVE(s1, REG_ITMP3);
954 M_INTMOVE(REG_ITMP3, d);
962 /* d may be equal to s2 */
966 emit_shift_reg(cd, shift_op, d);
970 M_INTMOVE(REG_ITMP3, RCX);
972 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
977 /* low-level code emitter functions *******************************************/
979 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
981 emit_rex(1,(reg),0,(dreg));
982 *(cd->mcodeptr++) = 0x89;
983 emit_reg((reg),(dreg));
987 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
989 emit_rex(1,0,0,(reg));
990 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
995 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
997 emit_rex(0,(reg),0,(dreg));
998 *(cd->mcodeptr++) = 0x89;
999 emit_reg((reg),(dreg));
1003 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1004 emit_rex(0,0,0,(reg));
1005 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1010 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1011 emit_rex(1,(reg),0,(basereg));
1012 *(cd->mcodeptr++) = 0x8b;
1013 emit_membase(cd, (basereg),(disp),(reg));
1018 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1019 * constant membase immediate length of 32bit
1021 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1022 emit_rex(1,(reg),0,(basereg));
1023 *(cd->mcodeptr++) = 0x8b;
1024 emit_membase32(cd, (basereg),(disp),(reg));
1028 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1030 emit_rex(0,(reg),0,(basereg));
1031 *(cd->mcodeptr++) = 0x8b;
1032 emit_membase(cd, (basereg),(disp),(reg));
1036 /* ATTENTION: Always emit a REX byte, because the instruction size can
1037 be smaller when all register indexes are smaller than 7. */
1038 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1040 emit_byte_rex((reg),0,(basereg));
1041 *(cd->mcodeptr++) = 0x8b;
1042 emit_membase32(cd, (basereg),(disp),(reg));
1046 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1047 emit_rex(1,(reg),0,(basereg));
1048 *(cd->mcodeptr++) = 0x89;
1049 emit_membase(cd, (basereg),(disp),(reg));
1053 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1054 emit_rex(1,(reg),0,(basereg));
1055 *(cd->mcodeptr++) = 0x89;
1056 emit_membase32(cd, (basereg),(disp),(reg));
1060 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1061 emit_rex(0,(reg),0,(basereg));
1062 *(cd->mcodeptr++) = 0x89;
1063 emit_membase(cd, (basereg),(disp),(reg));
1067 /* Always emit a REX byte, because the instruction size can be smaller when */
1068 /* all register indexes are smaller than 7. */
1069 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1070 emit_byte_rex((reg),0,(basereg));
1071 *(cd->mcodeptr++) = 0x89;
1072 emit_membase32(cd, (basereg),(disp),(reg));
1076 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1077 emit_rex(1,(reg),(indexreg),(basereg));
1078 *(cd->mcodeptr++) = 0x8b;
1079 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1083 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1084 emit_rex(0,(reg),(indexreg),(basereg));
1085 *(cd->mcodeptr++) = 0x8b;
1086 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1090 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1091 emit_rex(1,(reg),(indexreg),(basereg));
1092 *(cd->mcodeptr++) = 0x89;
1093 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1097 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1098 emit_rex(0,(reg),(indexreg),(basereg));
1099 *(cd->mcodeptr++) = 0x89;
1100 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1104 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1105 *(cd->mcodeptr++) = 0x66;
1106 emit_rex(0,(reg),(indexreg),(basereg));
1107 *(cd->mcodeptr++) = 0x89;
1108 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1112 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1113 emit_byte_rex((reg),(indexreg),(basereg));
1114 *(cd->mcodeptr++) = 0x88;
1115 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1119 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1120 emit_rex(1,0,0,(basereg));
1121 *(cd->mcodeptr++) = 0xc7;
1122 emit_membase(cd, (basereg),(disp),0);
1127 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1128 emit_rex(1,0,0,(basereg));
1129 *(cd->mcodeptr++) = 0xc7;
1130 emit_membase32(cd, (basereg),(disp),0);
1135 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1136 emit_rex(0,0,0,(basereg));
1137 *(cd->mcodeptr++) = 0xc7;
1138 emit_membase(cd, (basereg),(disp),0);
1143 /* Always emit a REX byte, because the instruction size can be smaller when */
1144 /* all register indexes are smaller than 7. */
1145 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1146 emit_byte_rex(0,0,(basereg));
1147 *(cd->mcodeptr++) = 0xc7;
1148 emit_membase32(cd, (basereg),(disp),0);
1153 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1155 emit_rex(1,(dreg),0,(reg));
1156 *(cd->mcodeptr++) = 0x0f;
1157 *(cd->mcodeptr++) = 0xbe;
1158 /* XXX: why do reg and dreg have to be exchanged */
1159 emit_reg((dreg),(reg));
1163 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1165 emit_rex(1,(dreg),0,(reg));
1166 *(cd->mcodeptr++) = 0x0f;
1167 *(cd->mcodeptr++) = 0xbf;
1168 /* XXX: why do reg and dreg have to be exchanged */
1169 emit_reg((dreg),(reg));
1173 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1175 emit_rex(1,(dreg),0,(reg));
1176 *(cd->mcodeptr++) = 0x63;
1177 /* XXX: why do reg and dreg have to be exchanged */
1178 emit_reg((dreg),(reg));
1182 void emit_movzbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1184 emit_rex(1,(dreg),0,(reg));
1185 *(cd->mcodeptr++) = 0x0f;
1186 *(cd->mcodeptr++) = 0xb6;
1187 /* XXX: why do reg and dreg have to be exchanged */
1188 emit_reg((dreg),(reg));
1192 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1194 emit_rex(1,(dreg),0,(reg));
1195 *(cd->mcodeptr++) = 0x0f;
1196 *(cd->mcodeptr++) = 0xb7;
1197 /* XXX: why do reg and dreg have to be exchanged */
1198 emit_reg((dreg),(reg));
1202 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1203 emit_rex(1,(reg),(indexreg),(basereg));
1204 *(cd->mcodeptr++) = 0x0f;
1205 *(cd->mcodeptr++) = 0xbf;
1206 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1210 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1211 emit_rex(1,(reg),(indexreg),(basereg));
1212 *(cd->mcodeptr++) = 0x0f;
1213 *(cd->mcodeptr++) = 0xbe;
1214 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1218 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1219 emit_rex(1,(reg),(indexreg),(basereg));
1220 *(cd->mcodeptr++) = 0x0f;
1221 *(cd->mcodeptr++) = 0xb7;
1222 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1226 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1228 emit_rex(1,0,(indexreg),(basereg));
1229 *(cd->mcodeptr++) = 0xc7;
1230 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1235 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1237 emit_rex(0,0,(indexreg),(basereg));
1238 *(cd->mcodeptr++) = 0xc7;
1239 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1244 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1246 *(cd->mcodeptr++) = 0x66;
1247 emit_rex(0,0,(indexreg),(basereg));
1248 *(cd->mcodeptr++) = 0xc7;
1249 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1254 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1256 emit_rex(0,0,(indexreg),(basereg));
1257 *(cd->mcodeptr++) = 0xc6;
1258 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1263 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1265 emit_rex(1, dreg, 0, 0);
1266 *(cd->mcodeptr++) = 0x8b;
1267 emit_address_byte(0, dreg, 4);
1275 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1277 emit_rex(1,(reg),0,(dreg));
1278 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1279 emit_reg((reg),(dreg));
1283 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1285 emit_rex(0,(reg),0,(dreg));
1286 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1287 emit_reg((reg),(dreg));
1291 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1293 emit_rex(1,(reg),0,(basereg));
1294 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1295 emit_membase(cd, (basereg),(disp),(reg));
1299 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1301 emit_rex(0,(reg),0,(basereg));
1302 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1303 emit_membase(cd, (basereg),(disp),(reg));
1307 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1309 emit_rex(1,(reg),0,(basereg));
1310 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1311 emit_membase(cd, (basereg),(disp),(reg));
1315 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1317 emit_rex(0,(reg),0,(basereg));
1318 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1319 emit_membase(cd, (basereg),(disp),(reg));
1323 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1325 emit_rex(1,0,0,(dreg));
1326 *(cd->mcodeptr++) = 0x83;
1327 emit_reg((opc),(dreg));
1330 emit_rex(1,0,0,(dreg));
1331 *(cd->mcodeptr++) = 0x81;
1332 emit_reg((opc),(dreg));
1338 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1340 emit_rex(1,0,0,(dreg));
1341 *(cd->mcodeptr++) = 0x81;
1342 emit_reg((opc),(dreg));
1347 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1349 emit_rex(0,0,0,(dreg));
1350 *(cd->mcodeptr++) = 0x81;
1351 emit_reg((opc),(dreg));
1356 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1358 emit_rex(0,0,0,(dreg));
1359 *(cd->mcodeptr++) = 0x83;
1360 emit_reg((opc),(dreg));
1363 emit_rex(0,0,0,(dreg));
1364 *(cd->mcodeptr++) = 0x81;
1365 emit_reg((opc),(dreg));
1371 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1373 emit_rex(1,0,0,(basereg));
1374 *(cd->mcodeptr++) = 0x83;
1375 emit_membase(cd, (basereg),(disp),(opc));
1378 emit_rex(1,0,0,(basereg));
1379 *(cd->mcodeptr++) = 0x81;
1380 emit_membase(cd, (basereg),(disp),(opc));
1386 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1388 emit_rex(0,0,0,(basereg));
1389 *(cd->mcodeptr++) = 0x83;
1390 emit_membase(cd, (basereg),(disp),(opc));
1393 emit_rex(0,0,0,(basereg));
1394 *(cd->mcodeptr++) = 0x81;
1395 emit_membase(cd, (basereg),(disp),(opc));
1401 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1402 emit_rex(1,(reg),0,(dreg));
1403 *(cd->mcodeptr++) = 0x85;
1404 emit_reg((reg),(dreg));
1408 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1409 emit_rex(0,(reg),0,(dreg));
1410 *(cd->mcodeptr++) = 0x85;
1411 emit_reg((reg),(dreg));
1415 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1416 *(cd->mcodeptr++) = 0xf7;
1422 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1423 *(cd->mcodeptr++) = 0x66;
1424 *(cd->mcodeptr++) = 0xf7;
1430 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1431 *(cd->mcodeptr++) = 0xf6;
1437 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1438 emit_rex(1,(reg),0,(basereg));
1439 *(cd->mcodeptr++) = 0x8d;
1440 emit_membase(cd, (basereg),(disp),(reg));
1444 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1445 emit_rex(0,(reg),0,(basereg));
1446 *(cd->mcodeptr++) = 0x8d;
1447 emit_membase(cd, (basereg),(disp),(reg));
1452 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1454 emit_rex(0,0,0,(basereg));
1455 *(cd->mcodeptr++) = 0xff;
1456 emit_membase(cd, (basereg),(disp),0);
1461 void emit_cltd(codegendata *cd) {
1462 *(cd->mcodeptr++) = 0x99;
1466 void emit_cqto(codegendata *cd) {
1468 *(cd->mcodeptr++) = 0x99;
1473 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1474 emit_rex(1,(dreg),0,(reg));
1475 *(cd->mcodeptr++) = 0x0f;
1476 *(cd->mcodeptr++) = 0xaf;
1477 emit_reg((dreg),(reg));
1481 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1482 emit_rex(0,(dreg),0,(reg));
1483 *(cd->mcodeptr++) = 0x0f;
1484 *(cd->mcodeptr++) = 0xaf;
1485 emit_reg((dreg),(reg));
1489 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1490 emit_rex(1,(dreg),0,(basereg));
1491 *(cd->mcodeptr++) = 0x0f;
1492 *(cd->mcodeptr++) = 0xaf;
1493 emit_membase(cd, (basereg),(disp),(dreg));
1497 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1498 emit_rex(0,(dreg),0,(basereg));
1499 *(cd->mcodeptr++) = 0x0f;
1500 *(cd->mcodeptr++) = 0xaf;
1501 emit_membase(cd, (basereg),(disp),(dreg));
1505 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1506 if (IS_IMM8((imm))) {
1507 emit_rex(1,0,0,(dreg));
1508 *(cd->mcodeptr++) = 0x6b;
1512 emit_rex(1,0,0,(dreg));
1513 *(cd->mcodeptr++) = 0x69;
1520 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1521 if (IS_IMM8((imm))) {
1522 emit_rex(1,(dreg),0,(reg));
1523 *(cd->mcodeptr++) = 0x6b;
1524 emit_reg((dreg),(reg));
1527 emit_rex(1,(dreg),0,(reg));
1528 *(cd->mcodeptr++) = 0x69;
1529 emit_reg((dreg),(reg));
1535 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1536 if (IS_IMM8((imm))) {
1537 emit_rex(0,(dreg),0,(reg));
1538 *(cd->mcodeptr++) = 0x6b;
1539 emit_reg((dreg),(reg));
1542 emit_rex(0,(dreg),0,(reg));
1543 *(cd->mcodeptr++) = 0x69;
1544 emit_reg((dreg),(reg));
1550 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1551 if (IS_IMM8((imm))) {
1552 emit_rex(1,(dreg),0,(basereg));
1553 *(cd->mcodeptr++) = 0x6b;
1554 emit_membase(cd, (basereg),(disp),(dreg));
1557 emit_rex(1,(dreg),0,(basereg));
1558 *(cd->mcodeptr++) = 0x69;
1559 emit_membase(cd, (basereg),(disp),(dreg));
1565 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1566 if (IS_IMM8((imm))) {
1567 emit_rex(0,(dreg),0,(basereg));
1568 *(cd->mcodeptr++) = 0x6b;
1569 emit_membase(cd, (basereg),(disp),(dreg));
1572 emit_rex(0,(dreg),0,(basereg));
1573 *(cd->mcodeptr++) = 0x69;
1574 emit_membase(cd, (basereg),(disp),(dreg));
1580 void emit_idiv_reg(codegendata *cd, s8 reg) {
1581 emit_rex(1,0,0,(reg));
1582 *(cd->mcodeptr++) = 0xf7;
1587 void emit_idivl_reg(codegendata *cd, s8 reg) {
1588 emit_rex(0,0,0,(reg));
1589 *(cd->mcodeptr++) = 0xf7;
1598 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1599 emit_rex(1,0,0,(reg));
1600 *(cd->mcodeptr++) = 0xd3;
1601 emit_reg((opc),(reg));
1605 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1606 emit_rex(0,0,0,(reg));
1607 *(cd->mcodeptr++) = 0xd3;
1608 emit_reg((opc),(reg));
1612 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1613 emit_rex(1,0,0,(basereg));
1614 *(cd->mcodeptr++) = 0xd3;
1615 emit_membase(cd, (basereg),(disp),(opc));
1619 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1620 emit_rex(0,0,0,(basereg));
1621 *(cd->mcodeptr++) = 0xd3;
1622 emit_membase(cd, (basereg),(disp),(opc));
1626 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1628 emit_rex(1,0,0,(dreg));
1629 *(cd->mcodeptr++) = 0xd1;
1630 emit_reg((opc),(dreg));
1632 emit_rex(1,0,0,(dreg));
1633 *(cd->mcodeptr++) = 0xc1;
1634 emit_reg((opc),(dreg));
1640 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1642 emit_rex(0,0,0,(dreg));
1643 *(cd->mcodeptr++) = 0xd1;
1644 emit_reg((opc),(dreg));
1646 emit_rex(0,0,0,(dreg));
1647 *(cd->mcodeptr++) = 0xc1;
1648 emit_reg((opc),(dreg));
1654 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1656 emit_rex(1,0,0,(basereg));
1657 *(cd->mcodeptr++) = 0xd1;
1658 emit_membase(cd, (basereg),(disp),(opc));
1660 emit_rex(1,0,0,(basereg));
1661 *(cd->mcodeptr++) = 0xc1;
1662 emit_membase(cd, (basereg),(disp),(opc));
1668 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1670 emit_rex(0,0,0,(basereg));
1671 *(cd->mcodeptr++) = 0xd1;
1672 emit_membase(cd, (basereg),(disp),(opc));
1674 emit_rex(0,0,0,(basereg));
1675 *(cd->mcodeptr++) = 0xc1;
1676 emit_membase(cd, (basereg),(disp),(opc));
1686 void emit_jmp_imm(codegendata *cd, s8 imm) {
1687 *(cd->mcodeptr++) = 0xe9;
1692 void emit_jmp_reg(codegendata *cd, s8 reg) {
1693 emit_rex(0,0,0,(reg));
1694 *(cd->mcodeptr++) = 0xff;
1699 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1700 *(cd->mcodeptr++) = 0x0f;
1701 *(cd->mcodeptr++) = (0x80 + (opc));
1708 * conditional set and move operations
1711 /* we need the rex byte to get all low bytes */
1712 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1714 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1715 *(cd->mcodeptr++) = 0x0f;
1716 *(cd->mcodeptr++) = (0x90 + (opc));
1721 /* we need the rex byte to get all low bytes */
1722 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1724 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1725 *(cd->mcodeptr++) = 0x0f;
1726 *(cd->mcodeptr++) = (0x90 + (opc));
1727 emit_membase(cd, (basereg),(disp),0);
1731 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1733 emit_rex(1,(dreg),0,(reg));
1734 *(cd->mcodeptr++) = 0x0f;
1735 *(cd->mcodeptr++) = (0x40 + (opc));
1736 emit_reg((dreg),(reg));
1740 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1742 emit_rex(0,(dreg),0,(reg));
1743 *(cd->mcodeptr++) = 0x0f;
1744 *(cd->mcodeptr++) = (0x40 + (opc));
1745 emit_reg((dreg),(reg));
1749 void emit_neg_reg(codegendata *cd, s8 reg)
1751 emit_rex(1,0,0,(reg));
1752 *(cd->mcodeptr++) = 0xf7;
1757 void emit_negl_reg(codegendata *cd, s8 reg)
1759 emit_rex(0,0,0,(reg));
1760 *(cd->mcodeptr++) = 0xf7;
1765 void emit_push_reg(codegendata *cd, s8 reg) {
1766 emit_rex(0,0,0,(reg));
1767 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1771 void emit_push_imm(codegendata *cd, s8 imm) {
1772 *(cd->mcodeptr++) = 0x68;
1777 void emit_pop_reg(codegendata *cd, s8 reg) {
1778 emit_rex(0,0,0,(reg));
1779 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1783 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1784 emit_rex(1,(reg),0,(dreg));
1785 *(cd->mcodeptr++) = 0x87;
1786 emit_reg((reg),(dreg));
1794 void emit_call_reg(codegendata *cd, s8 reg)
1796 emit_rex(0,0,0,(reg));
1797 *(cd->mcodeptr++) = 0xff;
1802 void emit_call_imm(codegendata *cd, s8 imm)
1804 *(cd->mcodeptr++) = 0xe8;
1809 void emit_call_mem(codegendata *cd, ptrint mem)
1811 *(cd->mcodeptr++) = 0xff;
1818 * floating point instructions (SSE2)
1820 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1821 *(cd->mcodeptr++) = 0xf2;
1822 emit_rex(0,(dreg),0,(reg));
1823 *(cd->mcodeptr++) = 0x0f;
1824 *(cd->mcodeptr++) = 0x58;
1825 emit_reg((dreg),(reg));
1829 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1830 *(cd->mcodeptr++) = 0xf3;
1831 emit_rex(0,(dreg),0,(reg));
1832 *(cd->mcodeptr++) = 0x0f;
1833 *(cd->mcodeptr++) = 0x58;
1834 emit_reg((dreg),(reg));
1838 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1839 *(cd->mcodeptr++) = 0xf3;
1840 emit_rex(1,(dreg),0,(reg));
1841 *(cd->mcodeptr++) = 0x0f;
1842 *(cd->mcodeptr++) = 0x2a;
1843 emit_reg((dreg),(reg));
1847 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1848 *(cd->mcodeptr++) = 0xf3;
1849 emit_rex(0,(dreg),0,(reg));
1850 *(cd->mcodeptr++) = 0x0f;
1851 *(cd->mcodeptr++) = 0x2a;
1852 emit_reg((dreg),(reg));
1856 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1857 *(cd->mcodeptr++) = 0xf2;
1858 emit_rex(1,(dreg),0,(reg));
1859 *(cd->mcodeptr++) = 0x0f;
1860 *(cd->mcodeptr++) = 0x2a;
1861 emit_reg((dreg),(reg));
1865 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1866 *(cd->mcodeptr++) = 0xf2;
1867 emit_rex(0,(dreg),0,(reg));
1868 *(cd->mcodeptr++) = 0x0f;
1869 *(cd->mcodeptr++) = 0x2a;
1870 emit_reg((dreg),(reg));
1874 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1875 *(cd->mcodeptr++) = 0xf3;
1876 emit_rex(0,(dreg),0,(reg));
1877 *(cd->mcodeptr++) = 0x0f;
1878 *(cd->mcodeptr++) = 0x5a;
1879 emit_reg((dreg),(reg));
1883 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1884 *(cd->mcodeptr++) = 0xf2;
1885 emit_rex(0,(dreg),0,(reg));
1886 *(cd->mcodeptr++) = 0x0f;
1887 *(cd->mcodeptr++) = 0x5a;
1888 emit_reg((dreg),(reg));
1892 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1893 *(cd->mcodeptr++) = 0xf3;
1894 emit_rex(1,(dreg),0,(reg));
1895 *(cd->mcodeptr++) = 0x0f;
1896 *(cd->mcodeptr++) = 0x2c;
1897 emit_reg((dreg),(reg));
1901 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1902 *(cd->mcodeptr++) = 0xf3;
1903 emit_rex(0,(dreg),0,(reg));
1904 *(cd->mcodeptr++) = 0x0f;
1905 *(cd->mcodeptr++) = 0x2c;
1906 emit_reg((dreg),(reg));
1910 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1911 *(cd->mcodeptr++) = 0xf2;
1912 emit_rex(1,(dreg),0,(reg));
1913 *(cd->mcodeptr++) = 0x0f;
1914 *(cd->mcodeptr++) = 0x2c;
1915 emit_reg((dreg),(reg));
1919 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1920 *(cd->mcodeptr++) = 0xf2;
1921 emit_rex(0,(dreg),0,(reg));
1922 *(cd->mcodeptr++) = 0x0f;
1923 *(cd->mcodeptr++) = 0x2c;
1924 emit_reg((dreg),(reg));
1928 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1929 *(cd->mcodeptr++) = 0xf3;
1930 emit_rex(0,(dreg),0,(reg));
1931 *(cd->mcodeptr++) = 0x0f;
1932 *(cd->mcodeptr++) = 0x5e;
1933 emit_reg((dreg),(reg));
1937 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1938 *(cd->mcodeptr++) = 0xf2;
1939 emit_rex(0,(dreg),0,(reg));
1940 *(cd->mcodeptr++) = 0x0f;
1941 *(cd->mcodeptr++) = 0x5e;
1942 emit_reg((dreg),(reg));
1946 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1947 *(cd->mcodeptr++) = 0x66;
1948 emit_rex(1,(freg),0,(reg));
1949 *(cd->mcodeptr++) = 0x0f;
1950 *(cd->mcodeptr++) = 0x6e;
1951 emit_reg((freg),(reg));
1955 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1956 *(cd->mcodeptr++) = 0x66;
1957 emit_rex(1,(freg),0,(reg));
1958 *(cd->mcodeptr++) = 0x0f;
1959 *(cd->mcodeptr++) = 0x7e;
1960 emit_reg((freg),(reg));
1964 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1965 *(cd->mcodeptr++) = 0x66;
1966 emit_rex(0,(reg),0,(basereg));
1967 *(cd->mcodeptr++) = 0x0f;
1968 *(cd->mcodeptr++) = 0x7e;
1969 emit_membase(cd, (basereg),(disp),(reg));
1973 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1974 *(cd->mcodeptr++) = 0x66;
1975 emit_rex(0,(reg),(indexreg),(basereg));
1976 *(cd->mcodeptr++) = 0x0f;
1977 *(cd->mcodeptr++) = 0x7e;
1978 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1982 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1983 *(cd->mcodeptr++) = 0x66;
1984 emit_rex(1,(dreg),0,(basereg));
1985 *(cd->mcodeptr++) = 0x0f;
1986 *(cd->mcodeptr++) = 0x6e;
1987 emit_membase(cd, (basereg),(disp),(dreg));
1991 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1992 *(cd->mcodeptr++) = 0x66;
1993 emit_rex(0,(dreg),0,(basereg));
1994 *(cd->mcodeptr++) = 0x0f;
1995 *(cd->mcodeptr++) = 0x6e;
1996 emit_membase(cd, (basereg),(disp),(dreg));
2000 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2001 *(cd->mcodeptr++) = 0x66;
2002 emit_rex(0,(dreg),(indexreg),(basereg));
2003 *(cd->mcodeptr++) = 0x0f;
2004 *(cd->mcodeptr++) = 0x6e;
2005 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2009 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2010 *(cd->mcodeptr++) = 0xf3;
2011 emit_rex(0,(dreg),0,(reg));
2012 *(cd->mcodeptr++) = 0x0f;
2013 *(cd->mcodeptr++) = 0x7e;
2014 emit_reg((dreg),(reg));
2018 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2019 *(cd->mcodeptr++) = 0x66;
2020 emit_rex(0,(reg),0,(basereg));
2021 *(cd->mcodeptr++) = 0x0f;
2022 *(cd->mcodeptr++) = 0xd6;
2023 emit_membase(cd, (basereg),(disp),(reg));
2027 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2028 *(cd->mcodeptr++) = 0xf3;
2029 emit_rex(0,(dreg),0,(basereg));
2030 *(cd->mcodeptr++) = 0x0f;
2031 *(cd->mcodeptr++) = 0x7e;
2032 emit_membase(cd, (basereg),(disp),(dreg));
2036 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2037 *(cd->mcodeptr++) = 0xf3;
2038 emit_rex(0,(reg),0,(dreg));
2039 *(cd->mcodeptr++) = 0x0f;
2040 *(cd->mcodeptr++) = 0x10;
2041 emit_reg((reg),(dreg));
2045 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2046 *(cd->mcodeptr++) = 0xf2;
2047 emit_rex(0,(reg),0,(dreg));
2048 *(cd->mcodeptr++) = 0x0f;
2049 *(cd->mcodeptr++) = 0x10;
2050 emit_reg((reg),(dreg));
2054 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2055 *(cd->mcodeptr++) = 0xf3;
2056 emit_rex(0,(reg),0,(basereg));
2057 *(cd->mcodeptr++) = 0x0f;
2058 *(cd->mcodeptr++) = 0x11;
2059 emit_membase(cd, (basereg),(disp),(reg));
2063 /* Always emit a REX byte, because the instruction size can be smaller when */
2064 /* all register indexes are smaller than 7. */
2065 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2066 *(cd->mcodeptr++) = 0xf3;
2067 emit_byte_rex((reg),0,(basereg));
2068 *(cd->mcodeptr++) = 0x0f;
2069 *(cd->mcodeptr++) = 0x11;
2070 emit_membase32(cd, (basereg),(disp),(reg));
2074 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2075 *(cd->mcodeptr++) = 0xf2;
2076 emit_rex(0,(reg),0,(basereg));
2077 *(cd->mcodeptr++) = 0x0f;
2078 *(cd->mcodeptr++) = 0x11;
2079 emit_membase(cd, (basereg),(disp),(reg));
2083 /* Always emit a REX byte, because the instruction size can be smaller when */
2084 /* all register indexes are smaller than 7. */
2085 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2086 *(cd->mcodeptr++) = 0xf2;
2087 emit_byte_rex((reg),0,(basereg));
2088 *(cd->mcodeptr++) = 0x0f;
2089 *(cd->mcodeptr++) = 0x11;
2090 emit_membase32(cd, (basereg),(disp),(reg));
2094 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2095 *(cd->mcodeptr++) = 0xf3;
2096 emit_rex(0,(dreg),0,(basereg));
2097 *(cd->mcodeptr++) = 0x0f;
2098 *(cd->mcodeptr++) = 0x10;
2099 emit_membase(cd, (basereg),(disp),(dreg));
2103 /* Always emit a REX byte, because the instruction size can be smaller when */
2104 /* all register indexes are smaller than 7. */
2105 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2106 *(cd->mcodeptr++) = 0xf3;
2107 emit_byte_rex((dreg),0,(basereg));
2108 *(cd->mcodeptr++) = 0x0f;
2109 *(cd->mcodeptr++) = 0x10;
2110 emit_membase32(cd, (basereg),(disp),(dreg));
2114 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2116 emit_rex(0,(dreg),0,(basereg));
2117 *(cd->mcodeptr++) = 0x0f;
2118 *(cd->mcodeptr++) = 0x12;
2119 emit_membase(cd, (basereg),(disp),(dreg));
2123 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2125 emit_rex(0,(reg),0,(basereg));
2126 *(cd->mcodeptr++) = 0x0f;
2127 *(cd->mcodeptr++) = 0x13;
2128 emit_membase(cd, (basereg),(disp),(reg));
2132 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2133 *(cd->mcodeptr++) = 0xf2;
2134 emit_rex(0,(dreg),0,(basereg));
2135 *(cd->mcodeptr++) = 0x0f;
2136 *(cd->mcodeptr++) = 0x10;
2137 emit_membase(cd, (basereg),(disp),(dreg));
2141 /* Always emit a REX byte, because the instruction size can be smaller when */
2142 /* all register indexes are smaller than 7. */
2143 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2144 *(cd->mcodeptr++) = 0xf2;
2145 emit_byte_rex((dreg),0,(basereg));
2146 *(cd->mcodeptr++) = 0x0f;
2147 *(cd->mcodeptr++) = 0x10;
2148 emit_membase32(cd, (basereg),(disp),(dreg));
2152 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2154 *(cd->mcodeptr++) = 0x66;
2155 emit_rex(0,(dreg),0,(basereg));
2156 *(cd->mcodeptr++) = 0x0f;
2157 *(cd->mcodeptr++) = 0x12;
2158 emit_membase(cd, (basereg),(disp),(dreg));
2162 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2164 *(cd->mcodeptr++) = 0x66;
2165 emit_rex(0,(reg),0,(basereg));
2166 *(cd->mcodeptr++) = 0x0f;
2167 *(cd->mcodeptr++) = 0x13;
2168 emit_membase(cd, (basereg),(disp),(reg));
2172 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2173 *(cd->mcodeptr++) = 0xf3;
2174 emit_rex(0,(reg),(indexreg),(basereg));
2175 *(cd->mcodeptr++) = 0x0f;
2176 *(cd->mcodeptr++) = 0x11;
2177 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2181 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2182 *(cd->mcodeptr++) = 0xf2;
2183 emit_rex(0,(reg),(indexreg),(basereg));
2184 *(cd->mcodeptr++) = 0x0f;
2185 *(cd->mcodeptr++) = 0x11;
2186 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2190 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2191 *(cd->mcodeptr++) = 0xf3;
2192 emit_rex(0,(dreg),(indexreg),(basereg));
2193 *(cd->mcodeptr++) = 0x0f;
2194 *(cd->mcodeptr++) = 0x10;
2195 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2199 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2200 *(cd->mcodeptr++) = 0xf2;
2201 emit_rex(0,(dreg),(indexreg),(basereg));
2202 *(cd->mcodeptr++) = 0x0f;
2203 *(cd->mcodeptr++) = 0x10;
2204 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2208 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2209 *(cd->mcodeptr++) = 0xf3;
2210 emit_rex(0,(dreg),0,(reg));
2211 *(cd->mcodeptr++) = 0x0f;
2212 *(cd->mcodeptr++) = 0x59;
2213 emit_reg((dreg),(reg));
2217 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2218 *(cd->mcodeptr++) = 0xf2;
2219 emit_rex(0,(dreg),0,(reg));
2220 *(cd->mcodeptr++) = 0x0f;
2221 *(cd->mcodeptr++) = 0x59;
2222 emit_reg((dreg),(reg));
2226 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2227 *(cd->mcodeptr++) = 0xf3;
2228 emit_rex(0,(dreg),0,(reg));
2229 *(cd->mcodeptr++) = 0x0f;
2230 *(cd->mcodeptr++) = 0x5c;
2231 emit_reg((dreg),(reg));
2235 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2236 *(cd->mcodeptr++) = 0xf2;
2237 emit_rex(0,(dreg),0,(reg));
2238 *(cd->mcodeptr++) = 0x0f;
2239 *(cd->mcodeptr++) = 0x5c;
2240 emit_reg((dreg),(reg));
2244 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2245 emit_rex(0,(dreg),0,(reg));
2246 *(cd->mcodeptr++) = 0x0f;
2247 *(cd->mcodeptr++) = 0x2e;
2248 emit_reg((dreg),(reg));
2252 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2253 *(cd->mcodeptr++) = 0x66;
2254 emit_rex(0,(dreg),0,(reg));
2255 *(cd->mcodeptr++) = 0x0f;
2256 *(cd->mcodeptr++) = 0x2e;
2257 emit_reg((dreg),(reg));
2261 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2262 emit_rex(0,(dreg),0,(reg));
2263 *(cd->mcodeptr++) = 0x0f;
2264 *(cd->mcodeptr++) = 0x57;
2265 emit_reg((dreg),(reg));
2269 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2270 emit_rex(0,(dreg),0,(basereg));
2271 *(cd->mcodeptr++) = 0x0f;
2272 *(cd->mcodeptr++) = 0x57;
2273 emit_membase(cd, (basereg),(disp),(dreg));
2277 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2278 *(cd->mcodeptr++) = 0x66;
2279 emit_rex(0,(dreg),0,(reg));
2280 *(cd->mcodeptr++) = 0x0f;
2281 *(cd->mcodeptr++) = 0x57;
2282 emit_reg((dreg),(reg));
2286 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2287 *(cd->mcodeptr++) = 0x66;
2288 emit_rex(0,(dreg),0,(basereg));
2289 *(cd->mcodeptr++) = 0x0f;
2290 *(cd->mcodeptr++) = 0x57;
2291 emit_membase(cd, (basereg),(disp),(dreg));
2295 /* system instructions ********************************************************/
2297 void emit_rdtsc(codegendata *cd)
2299 *(cd->mcodeptr++) = 0x0f;
2300 *(cd->mcodeptr++) = 0x31;
2305 * These are local overrides for various environment variables in Emacs.
2306 * Please do not remove this and leave it at the end of the file, where
2307 * Emacs will automagically detect them.
2308 * ---------------------------------------------------------------------
2311 * indent-tabs-mode: t