1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007, 2008
4 CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
6 This file is part of CACAO.
8 This program is free software; you can redistribute it and/or
9 modify it under the terms of the GNU General Public License as
10 published by the Free Software Foundation; either version 2, or (at
11 your option) any later version.
13 This program is distributed in the hope that it will be useful, but
14 WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
33 #include "vm/jit/x86_64/codegen.h"
34 #include "vm/jit/x86_64/emit.h"
36 #include "mm/memory.h"
38 #include "threads/lock-common.h"
40 #include "vm/options.h"
42 #include "vm/jit/abi.h"
43 #include "vm/jit/abi-asm.h"
44 #include "vm/jit/asmpart.h"
45 #include "vm/jit/codegen-common.h"
46 #include "vm/jit/emit-common.hpp"
47 #include "vm/jit/jit.hpp"
48 #include "vm/jit/patcher-common.h"
49 #include "vm/jit/replace.hpp"
50 #include "vm/jit/trace.hpp"
51 #include "vm/jit/trap.h"
54 /* emit_load *******************************************************************
56 Emits a possible load of an operand.
58 *******************************************************************************/
60 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
66 /* get required compiler data */
70 if (IS_INMEMORY(src->flags)) {
73 disp = src->vv.regoff;
77 M_ILD(tempreg, REG_SP, disp);
81 M_LLD(tempreg, REG_SP, disp);
84 M_FLD(tempreg, REG_SP, disp);
87 M_DLD(tempreg, REG_SP, disp);
90 vm_abort("emit_load: unknown type %d", src->type);
102 /* emit_store ******************************************************************
104 This function generates the code to store the result of an
105 operation back into a spilled pseudo-variable. If the
106 pseudo-variable has not been spilled in the first place, this
107 function will generate nothing.
109 *******************************************************************************/
111 void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
116 /* get required compiler data */
120 if (IS_INMEMORY(dst->flags)) {
123 disp = dst->vv.regoff;
129 M_LST(d, REG_SP, disp);
132 M_FST(d, REG_SP, disp);
135 M_DST(d, REG_SP, disp);
138 vm_abort("emit_store: unknown type %d", dst->type);
144 /* emit_copy *******************************************************************
146 Generates a register/memory to register/memory copy.
148 *******************************************************************************/
150 void emit_copy(jitdata *jd, instruction *iptr)
157 /* get required compiler data */
161 /* get source and destination variables */
163 src = VAROP(iptr->s1);
164 dst = VAROP(iptr->dst);
166 if ((src->vv.regoff != dst->vv.regoff) ||
167 ((src->flags ^ dst->flags) & INMEMORY)) {
169 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
170 /* emit nothing, as the value won't be used anyway */
174 /* If one of the variables resides in memory, we can eliminate
175 the register move from/to the temporary register with the
176 order of getting the destination register and the load. */
178 if (IS_INMEMORY(src->flags)) {
179 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
180 s1 = emit_load(jd, iptr, src, d);
183 s1 = emit_load(jd, iptr, src, REG_IFTMP);
184 d = codegen_reg_of_var(iptr->opc, dst, s1);
199 vm_abort("emit_copy: unknown type %d", src->type);
203 emit_store(jd, iptr, dst, d);
208 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
211 switch (iptr->flags.fields.condition) {
235 /* emit_branch *****************************************************************
237 Emits the code for conditional and unconditional branchs.
239 *******************************************************************************/
241 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
245 /* NOTE: A displacement overflow cannot happen. */
247 /* check which branch to generate */
249 if (condition == BRANCH_UNCONDITIONAL) {
251 /* calculate the different displacements */
253 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
255 M_JMP_IMM(branchdisp);
258 /* calculate the different displacements */
260 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
294 vm_abort("emit_branch: unknown condition %d", condition);
300 /* emit_arithmetic_check *******************************************************
302 Emit an ArithmeticException check.
304 *******************************************************************************/
306 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
308 if (INSTRUCTION_MUST_CHECK(iptr)) {
311 M_ALD_MEM(reg, TRAP_ArithmeticException);
316 /* emit_arrayindexoutofbounds_check ********************************************
318 Emit a ArrayIndexOutOfBoundsException check.
320 *******************************************************************************/
322 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
324 if (INSTRUCTION_MUST_CHECK(iptr)) {
325 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
326 M_ICMP(REG_ITMP3, s2);
328 M_ALD_MEM(s2, TRAP_ArrayIndexOutOfBoundsException);
333 /* emit_arraystore_check *******************************************************
335 Emit an ArrayStoreException check.
337 *******************************************************************************/
339 void emit_arraystore_check(codegendata *cd, instruction *iptr)
341 if (INSTRUCTION_MUST_CHECK(iptr)) {
344 M_ALD_MEM(REG_RESULT, TRAP_ArrayStoreException);
349 /* emit_classcast_check ********************************************************
351 Emit a ClassCastException check.
353 *******************************************************************************/
355 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
357 if (INSTRUCTION_MUST_CHECK(iptr)) {
369 vm_abort("emit_classcast_check: unknown condition %d", condition);
371 M_ALD_MEM(s1, TRAP_ClassCastException);
376 /* emit_nullpointer_check ******************************************************
378 Emit a NullPointerException check.
380 *******************************************************************************/
382 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
384 if (INSTRUCTION_MUST_CHECK(iptr)) {
387 M_ALD_MEM(reg, TRAP_NullPointerException);
392 /* emit_exception_check ********************************************************
394 Emit an Exception check.
396 *******************************************************************************/
398 void emit_exception_check(codegendata *cd, instruction *iptr)
400 if (INSTRUCTION_MUST_CHECK(iptr)) {
403 M_ALD_MEM(REG_RESULT, TRAP_CHECK_EXCEPTION);
408 /* emit_trap_compiler **********************************************************
410 Emit a trap instruction which calls the JIT compiler.
412 *******************************************************************************/
414 void emit_trap_compiler(codegendata *cd)
416 M_ALD_MEM(REG_METHODPTR, TRAP_COMPILER);
420 /* emit_trap *******************************************************************
422 Emit a trap instruction and return the original machine code.
424 *******************************************************************************/
426 uint32_t emit_trap(codegendata *cd)
430 /* Get machine code which is patched back in later. The trap is 2
433 mcode = *((uint16_t *) cd->mcodeptr);
435 /* XXX This needs to be change to INT3 when the debugging problems
436 with gdb are resolved. */
444 /* emit_verbosecall_enter ******************************************************
446 Generates the code for the call trace.
448 *******************************************************************************/
451 void emit_verbosecall_enter(jitdata *jd)
461 /* get required compiler data */
470 /* mark trace code */
474 /* keep 16-byte stack alignment */
476 stackframesize = md->paramcount + ARG_CNT + TMP_CNT;
477 ALIGN_2(stackframesize);
479 M_LSUB_IMM(stackframesize * 8, REG_SP);
481 /* save argument registers */
483 for (i = 0; i < md->paramcount; i++) {
484 if (!md->params[i].inmemory) {
485 s = md->params[i].regoff;
487 switch (md->paramtypes[i].type) {
491 M_LST(s, REG_SP, i * 8);
495 M_DST(s, REG_SP, i * 8);
501 /* save all argument and temporary registers for leaf methods */
503 if (code_is_leafmethod(code)) {
504 for (i = 0; i < INT_ARG_CNT; i++)
505 M_LST(abi_registers_integer_argument[i], REG_SP, (md->paramcount + i) * 8);
507 for (i = 0; i < FLT_ARG_CNT; i++)
508 M_DST(abi_registers_float_argument[i], REG_SP, (md->paramcount + INT_ARG_CNT + i) * 8);
510 for (i = 0; i < INT_TMP_CNT; i++)
511 M_LST(rd->tmpintregs[i], REG_SP, (md->paramcount + ARG_CNT + i) * 8);
513 for (i = 0; i < FLT_TMP_CNT; i++)
514 M_DST(rd->tmpfltregs[i], REG_SP, (md->paramcount + ARG_CNT + INT_TMP_CNT + i) * 8);
517 M_MOV_IMM(m, REG_A0);
518 M_MOV(REG_SP, REG_A1);
519 M_MOV(REG_SP, REG_A2);
520 M_AADD_IMM((stackframesize + cd->stackframesize + 1) * 8, REG_A2);
521 M_MOV_IMM(trace_java_call_enter, REG_ITMP1);
524 /* restore argument registers */
526 for (i = 0; i < md->paramcount; i++) {
527 if (!md->params[i].inmemory) {
528 s = md->params[i].regoff;
530 switch (md->paramtypes[i].type) {
534 M_LLD(s, REG_SP, i * 8);
538 M_DLD(s, REG_SP, i * 8);
545 /* restore all argument and temporary registers for leaf methods */
547 if (code_is_leafmethod(code)) {
548 for (i = 0; i < INT_ARG_CNT; i++)
549 M_LLD(abi_registers_integer_argument[i], REG_SP, (md->paramcount + i) * 8);
551 for (i = 0; i < FLT_ARG_CNT; i++)
552 M_DLD(abi_registers_float_argument[i], REG_SP, (md->paramcount + INT_ARG_CNT + i) * 8);
554 for (i = 0; i < INT_TMP_CNT; i++)
555 M_LLD(rd->tmpintregs[i], REG_SP, (md->paramcount + ARG_CNT + i) * 8);
557 for (i = 0; i < FLT_TMP_CNT; i++)
558 M_DLD(rd->tmpfltregs[i], REG_SP, (md->paramcount + ARG_CNT + INT_TMP_CNT + i) * 8);
561 M_LADD_IMM(stackframesize * 8, REG_SP);
563 /* mark trace code */
567 #endif /* !defined(NDEBUG) */
570 /* emit_verbosecall_exit *******************************************************
572 Generates the code for the call trace.
574 *******************************************************************************/
577 void emit_verbosecall_exit(jitdata *jd)
584 /* get required compiler data */
592 /* mark trace code */
596 /* keep 16-byte stack alignment */
598 M_ASUB_IMM(2 * 8, REG_SP);
600 /* save return value */
602 switch (md->returntype.type) {
606 M_LST(REG_RESULT, REG_SP, 0 * 8);
610 M_DST(REG_FRESULT, REG_SP, 0 * 8);
614 M_MOV_IMM(m, REG_A0);
615 M_MOV(REG_SP, REG_A1);
617 M_MOV_IMM(trace_java_call_exit, REG_ITMP1);
620 /* restore return value */
622 switch (md->returntype.type) {
626 M_LLD(REG_RESULT, REG_SP, 0 * 8);
630 M_DLD(REG_FRESULT, REG_SP, 0 * 8);
634 M_AADD_IMM(2 * 8, REG_SP);
636 /* mark trace code */
640 #endif /* !defined(NDEBUG) */
643 /* code generation functions **************************************************/
645 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
647 if ((basereg == REG_SP) || (basereg == R12)) {
649 emit_address_byte(0, dreg, REG_SP);
650 emit_address_byte(0, REG_SP, REG_SP);
652 } else if (IS_IMM8(disp)) {
653 emit_address_byte(1, dreg, REG_SP);
654 emit_address_byte(0, REG_SP, REG_SP);
658 emit_address_byte(2, dreg, REG_SP);
659 emit_address_byte(0, REG_SP, REG_SP);
663 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
664 emit_address_byte(0,(dreg),(basereg));
666 } else if ((basereg) == RIP) {
667 emit_address_byte(0, dreg, RBP);
672 emit_address_byte(1, dreg, basereg);
676 emit_address_byte(2, dreg, basereg);
683 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
685 if ((basereg == REG_SP) || (basereg == R12)) {
686 emit_address_byte(2, dreg, REG_SP);
687 emit_address_byte(0, REG_SP, REG_SP);
691 emit_address_byte(2, dreg, basereg);
697 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
700 emit_address_byte(0, reg, 4);
701 emit_address_byte(scale, indexreg, 5);
704 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
705 emit_address_byte(0, reg, 4);
706 emit_address_byte(scale, indexreg, basereg);
708 else if (IS_IMM8(disp)) {
709 emit_address_byte(1, reg, 4);
710 emit_address_byte(scale, indexreg, basereg);
714 emit_address_byte(2, reg, 4);
715 emit_address_byte(scale, indexreg, basereg);
721 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
724 varinfo *v_s1,*v_s2,*v_dst;
727 /* get required compiler data */
731 v_s1 = VAROP(iptr->s1);
732 v_s2 = VAROP(iptr->sx.s23.s2);
733 v_dst = VAROP(iptr->dst);
735 s1 = v_s1->vv.regoff;
736 s2 = v_s2->vv.regoff;
737 d = v_dst->vv.regoff;
739 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
741 if (IS_INMEMORY(v_dst->flags)) {
742 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
744 M_ILD(RCX, REG_SP, s2);
745 emit_shiftl_membase(cd, shift_op, REG_SP, d);
748 M_ILD(RCX, REG_SP, s2);
749 M_ILD(REG_ITMP2, REG_SP, s1);
750 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
751 M_IST(REG_ITMP2, REG_SP, d);
754 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
755 /* s1 may be equal to RCX */
758 M_ILD(REG_ITMP1, REG_SP, s2);
759 M_IST(s1, REG_SP, d);
760 M_INTMOVE(REG_ITMP1, RCX);
763 M_IST(s1, REG_SP, d);
764 M_ILD(RCX, REG_SP, s2);
768 M_ILD(RCX, REG_SP, s2);
769 M_IST(s1, REG_SP, d);
772 emit_shiftl_membase(cd, shift_op, REG_SP, d);
774 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
777 emit_shiftl_membase(cd, shift_op, REG_SP, d);
781 M_ILD(REG_ITMP2, REG_SP, s1);
782 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
783 M_IST(REG_ITMP2, REG_SP, d);
787 /* s1 may be equal to RCX */
788 M_IST(s1, REG_SP, d);
790 emit_shiftl_membase(cd, shift_op, REG_SP, d);
793 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
801 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
802 M_ILD(RCX, REG_SP, s2);
803 M_ILD(d, REG_SP, s1);
804 emit_shiftl_reg(cd, shift_op, d);
806 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
807 /* s1 may be equal to RCX */
809 M_ILD(RCX, REG_SP, s2);
810 emit_shiftl_reg(cd, shift_op, d);
812 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
814 M_ILD(d, REG_SP, s1);
815 emit_shiftl_reg(cd, shift_op, d);
818 /* s1 may be equal to RCX */
821 /* d cannot be used to backup s1 since this would
823 M_INTMOVE(s1, REG_ITMP3);
825 M_INTMOVE(REG_ITMP3, d);
833 /* d may be equal to s2 */
837 emit_shiftl_reg(cd, shift_op, d);
841 M_INTMOVE(REG_ITMP3, RCX);
843 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
848 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
851 varinfo *v_s1,*v_s2,*v_dst;
854 /* get required compiler data */
858 v_s1 = VAROP(iptr->s1);
859 v_s2 = VAROP(iptr->sx.s23.s2);
860 v_dst = VAROP(iptr->dst);
862 s1 = v_s1->vv.regoff;
863 s2 = v_s2->vv.regoff;
864 d = v_dst->vv.regoff;
866 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
868 if (IS_INMEMORY(v_dst->flags)) {
869 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
871 M_ILD(RCX, REG_SP, s2);
872 emit_shift_membase(cd, shift_op, REG_SP, d);
875 M_ILD(RCX, REG_SP, s2);
876 M_LLD(REG_ITMP2, REG_SP, s1);
877 emit_shift_reg(cd, shift_op, REG_ITMP2);
878 M_LST(REG_ITMP2, REG_SP, d);
881 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
882 /* s1 may be equal to RCX */
885 M_ILD(REG_ITMP1, REG_SP, s2);
886 M_LST(s1, REG_SP, d);
887 M_INTMOVE(REG_ITMP1, RCX);
890 M_LST(s1, REG_SP, d);
891 M_ILD(RCX, REG_SP, s2);
895 M_ILD(RCX, REG_SP, s2);
896 M_LST(s1, REG_SP, d);
899 emit_shift_membase(cd, shift_op, REG_SP, d);
901 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
904 emit_shift_membase(cd, shift_op, REG_SP, d);
908 M_LLD(REG_ITMP2, REG_SP, s1);
909 emit_shift_reg(cd, shift_op, REG_ITMP2);
910 M_LST(REG_ITMP2, REG_SP, d);
914 /* s1 may be equal to RCX */
915 M_LST(s1, REG_SP, d);
917 emit_shift_membase(cd, shift_op, REG_SP, d);
920 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
928 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
929 M_ILD(RCX, REG_SP, s2);
930 M_LLD(d, REG_SP, s1);
931 emit_shift_reg(cd, shift_op, d);
933 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
934 /* s1 may be equal to RCX */
936 M_ILD(RCX, REG_SP, s2);
937 emit_shift_reg(cd, shift_op, d);
939 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
941 M_LLD(d, REG_SP, s1);
942 emit_shift_reg(cd, shift_op, d);
945 /* s1 may be equal to RCX */
948 /* d cannot be used to backup s1 since this would
950 M_INTMOVE(s1, REG_ITMP3);
952 M_INTMOVE(REG_ITMP3, d);
960 /* d may be equal to s2 */
964 emit_shift_reg(cd, shift_op, d);
968 M_INTMOVE(REG_ITMP3, RCX);
970 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
975 /* low-level code emitter functions *******************************************/
977 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
979 emit_rex(1,(reg),0,(dreg));
980 *(cd->mcodeptr++) = 0x89;
981 emit_reg((reg),(dreg));
985 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
987 emit_rex(1,0,0,(reg));
988 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
993 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
995 emit_rex(0,(reg),0,(dreg));
996 *(cd->mcodeptr++) = 0x89;
997 emit_reg((reg),(dreg));
1001 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1002 emit_rex(0,0,0,(reg));
1003 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1008 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1009 emit_rex(1,(reg),0,(basereg));
1010 *(cd->mcodeptr++) = 0x8b;
1011 emit_membase(cd, (basereg),(disp),(reg));
1016 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1017 * constant membase immediate length of 32bit
1019 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1020 emit_rex(1,(reg),0,(basereg));
1021 *(cd->mcodeptr++) = 0x8b;
1022 emit_membase32(cd, (basereg),(disp),(reg));
1026 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1028 emit_rex(0,(reg),0,(basereg));
1029 *(cd->mcodeptr++) = 0x8b;
1030 emit_membase(cd, (basereg),(disp),(reg));
1034 /* ATTENTION: Always emit a REX byte, because the instruction size can
1035 be smaller when all register indexes are smaller than 7. */
1036 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1038 emit_byte_rex((reg),0,(basereg));
1039 *(cd->mcodeptr++) = 0x8b;
1040 emit_membase32(cd, (basereg),(disp),(reg));
1044 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1045 emit_rex(1,(reg),0,(basereg));
1046 *(cd->mcodeptr++) = 0x89;
1047 emit_membase(cd, (basereg),(disp),(reg));
1051 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1052 emit_rex(1,(reg),0,(basereg));
1053 *(cd->mcodeptr++) = 0x89;
1054 emit_membase32(cd, (basereg),(disp),(reg));
1058 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1059 emit_rex(0,(reg),0,(basereg));
1060 *(cd->mcodeptr++) = 0x89;
1061 emit_membase(cd, (basereg),(disp),(reg));
1065 /* Always emit a REX byte, because the instruction size can be smaller when */
1066 /* all register indexes are smaller than 7. */
1067 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1068 emit_byte_rex((reg),0,(basereg));
1069 *(cd->mcodeptr++) = 0x89;
1070 emit_membase32(cd, (basereg),(disp),(reg));
1074 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1075 emit_rex(1,(reg),(indexreg),(basereg));
1076 *(cd->mcodeptr++) = 0x8b;
1077 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1081 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1082 emit_rex(0,(reg),(indexreg),(basereg));
1083 *(cd->mcodeptr++) = 0x8b;
1084 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1088 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1089 emit_rex(1,(reg),(indexreg),(basereg));
1090 *(cd->mcodeptr++) = 0x89;
1091 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1095 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1096 emit_rex(0,(reg),(indexreg),(basereg));
1097 *(cd->mcodeptr++) = 0x89;
1098 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1102 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1103 *(cd->mcodeptr++) = 0x66;
1104 emit_rex(0,(reg),(indexreg),(basereg));
1105 *(cd->mcodeptr++) = 0x89;
1106 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1110 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1111 emit_byte_rex((reg),(indexreg),(basereg));
1112 *(cd->mcodeptr++) = 0x88;
1113 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1117 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1118 emit_rex(1,0,0,(basereg));
1119 *(cd->mcodeptr++) = 0xc7;
1120 emit_membase(cd, (basereg),(disp),0);
1125 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1126 emit_rex(1,0,0,(basereg));
1127 *(cd->mcodeptr++) = 0xc7;
1128 emit_membase32(cd, (basereg),(disp),0);
1133 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1134 emit_rex(0,0,0,(basereg));
1135 *(cd->mcodeptr++) = 0xc7;
1136 emit_membase(cd, (basereg),(disp),0);
1141 /* Always emit a REX byte, because the instruction size can be smaller when */
1142 /* all register indexes are smaller than 7. */
1143 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1144 emit_byte_rex(0,0,(basereg));
1145 *(cd->mcodeptr++) = 0xc7;
1146 emit_membase32(cd, (basereg),(disp),0);
1151 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1153 emit_rex(1,(dreg),0,(reg));
1154 *(cd->mcodeptr++) = 0x0f;
1155 *(cd->mcodeptr++) = 0xbe;
1156 /* XXX: why do reg and dreg have to be exchanged */
1157 emit_reg((dreg),(reg));
1161 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1163 emit_rex(1,(dreg),0,(reg));
1164 *(cd->mcodeptr++) = 0x0f;
1165 *(cd->mcodeptr++) = 0xbf;
1166 /* XXX: why do reg and dreg have to be exchanged */
1167 emit_reg((dreg),(reg));
1171 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1173 emit_rex(1,(dreg),0,(reg));
1174 *(cd->mcodeptr++) = 0x63;
1175 /* XXX: why do reg and dreg have to be exchanged */
1176 emit_reg((dreg),(reg));
1180 void emit_movzbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1182 emit_rex(1,(dreg),0,(reg));
1183 *(cd->mcodeptr++) = 0x0f;
1184 *(cd->mcodeptr++) = 0xb6;
1185 /* XXX: why do reg and dreg have to be exchanged */
1186 emit_reg((dreg),(reg));
1190 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1192 emit_rex(1,(dreg),0,(reg));
1193 *(cd->mcodeptr++) = 0x0f;
1194 *(cd->mcodeptr++) = 0xb7;
1195 /* XXX: why do reg and dreg have to be exchanged */
1196 emit_reg((dreg),(reg));
1200 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1201 emit_rex(1,(reg),(indexreg),(basereg));
1202 *(cd->mcodeptr++) = 0x0f;
1203 *(cd->mcodeptr++) = 0xbf;
1204 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1208 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1209 emit_rex(1,(reg),(indexreg),(basereg));
1210 *(cd->mcodeptr++) = 0x0f;
1211 *(cd->mcodeptr++) = 0xbe;
1212 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1216 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1217 emit_rex(1,(reg),(indexreg),(basereg));
1218 *(cd->mcodeptr++) = 0x0f;
1219 *(cd->mcodeptr++) = 0xb7;
1220 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1224 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1226 emit_rex(1,0,(indexreg),(basereg));
1227 *(cd->mcodeptr++) = 0xc7;
1228 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1233 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1235 emit_rex(0,0,(indexreg),(basereg));
1236 *(cd->mcodeptr++) = 0xc7;
1237 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1242 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1244 *(cd->mcodeptr++) = 0x66;
1245 emit_rex(0,0,(indexreg),(basereg));
1246 *(cd->mcodeptr++) = 0xc7;
1247 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1252 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1254 emit_rex(0,0,(indexreg),(basereg));
1255 *(cd->mcodeptr++) = 0xc6;
1256 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1261 void emit_mov_mem_reg(codegendata *cd, s4 disp, s4 dreg)
1263 emit_rex(1, dreg, 0, 0);
1264 *(cd->mcodeptr++) = 0x8b;
1265 emit_address_byte(0, dreg, 4);
1273 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1275 emit_rex(1,(reg),0,(dreg));
1276 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1277 emit_reg((reg),(dreg));
1281 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1283 emit_rex(0,(reg),0,(dreg));
1284 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1285 emit_reg((reg),(dreg));
1289 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1291 emit_rex(1,(reg),0,(basereg));
1292 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1293 emit_membase(cd, (basereg),(disp),(reg));
1297 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1299 emit_rex(0,(reg),0,(basereg));
1300 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1301 emit_membase(cd, (basereg),(disp),(reg));
1305 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1307 emit_rex(1,(reg),0,(basereg));
1308 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1309 emit_membase(cd, (basereg),(disp),(reg));
1313 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1315 emit_rex(0,(reg),0,(basereg));
1316 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1317 emit_membase(cd, (basereg),(disp),(reg));
1321 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1323 emit_rex(1,0,0,(dreg));
1324 *(cd->mcodeptr++) = 0x83;
1325 emit_reg((opc),(dreg));
1328 emit_rex(1,0,0,(dreg));
1329 *(cd->mcodeptr++) = 0x81;
1330 emit_reg((opc),(dreg));
1336 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1338 emit_rex(1,0,0,(dreg));
1339 *(cd->mcodeptr++) = 0x81;
1340 emit_reg((opc),(dreg));
1345 void emit_alul_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1347 emit_rex(0,0,0,(dreg));
1348 *(cd->mcodeptr++) = 0x81;
1349 emit_reg((opc),(dreg));
1354 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1356 emit_rex(0,0,0,(dreg));
1357 *(cd->mcodeptr++) = 0x83;
1358 emit_reg((opc),(dreg));
1361 emit_rex(0,0,0,(dreg));
1362 *(cd->mcodeptr++) = 0x81;
1363 emit_reg((opc),(dreg));
1369 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1371 emit_rex(1,0,0,(basereg));
1372 *(cd->mcodeptr++) = 0x83;
1373 emit_membase(cd, (basereg),(disp),(opc));
1376 emit_rex(1,0,0,(basereg));
1377 *(cd->mcodeptr++) = 0x81;
1378 emit_membase(cd, (basereg),(disp),(opc));
1384 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1386 emit_rex(0,0,0,(basereg));
1387 *(cd->mcodeptr++) = 0x83;
1388 emit_membase(cd, (basereg),(disp),(opc));
1391 emit_rex(0,0,0,(basereg));
1392 *(cd->mcodeptr++) = 0x81;
1393 emit_membase(cd, (basereg),(disp),(opc));
1399 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1400 emit_rex(1,(reg),0,(dreg));
1401 *(cd->mcodeptr++) = 0x85;
1402 emit_reg((reg),(dreg));
1406 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1407 emit_rex(0,(reg),0,(dreg));
1408 *(cd->mcodeptr++) = 0x85;
1409 emit_reg((reg),(dreg));
1413 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1414 *(cd->mcodeptr++) = 0xf7;
1420 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1421 *(cd->mcodeptr++) = 0x66;
1422 *(cd->mcodeptr++) = 0xf7;
1428 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1429 *(cd->mcodeptr++) = 0xf6;
1435 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1436 emit_rex(1,(reg),0,(basereg));
1437 *(cd->mcodeptr++) = 0x8d;
1438 emit_membase(cd, (basereg),(disp),(reg));
1442 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1443 emit_rex(0,(reg),0,(basereg));
1444 *(cd->mcodeptr++) = 0x8d;
1445 emit_membase(cd, (basereg),(disp),(reg));
1450 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1452 emit_rex(0,0,0,(basereg));
1453 *(cd->mcodeptr++) = 0xff;
1454 emit_membase(cd, (basereg),(disp),0);
1459 void emit_cltd(codegendata *cd) {
1460 *(cd->mcodeptr++) = 0x99;
1464 void emit_cqto(codegendata *cd) {
1466 *(cd->mcodeptr++) = 0x99;
1471 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1472 emit_rex(1,(dreg),0,(reg));
1473 *(cd->mcodeptr++) = 0x0f;
1474 *(cd->mcodeptr++) = 0xaf;
1475 emit_reg((dreg),(reg));
1479 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1480 emit_rex(0,(dreg),0,(reg));
1481 *(cd->mcodeptr++) = 0x0f;
1482 *(cd->mcodeptr++) = 0xaf;
1483 emit_reg((dreg),(reg));
1487 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1488 emit_rex(1,(dreg),0,(basereg));
1489 *(cd->mcodeptr++) = 0x0f;
1490 *(cd->mcodeptr++) = 0xaf;
1491 emit_membase(cd, (basereg),(disp),(dreg));
1495 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1496 emit_rex(0,(dreg),0,(basereg));
1497 *(cd->mcodeptr++) = 0x0f;
1498 *(cd->mcodeptr++) = 0xaf;
1499 emit_membase(cd, (basereg),(disp),(dreg));
1503 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1504 if (IS_IMM8((imm))) {
1505 emit_rex(1,0,0,(dreg));
1506 *(cd->mcodeptr++) = 0x6b;
1510 emit_rex(1,0,0,(dreg));
1511 *(cd->mcodeptr++) = 0x69;
1518 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1519 if (IS_IMM8((imm))) {
1520 emit_rex(1,(dreg),0,(reg));
1521 *(cd->mcodeptr++) = 0x6b;
1522 emit_reg((dreg),(reg));
1525 emit_rex(1,(dreg),0,(reg));
1526 *(cd->mcodeptr++) = 0x69;
1527 emit_reg((dreg),(reg));
1533 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1534 if (IS_IMM8((imm))) {
1535 emit_rex(0,(dreg),0,(reg));
1536 *(cd->mcodeptr++) = 0x6b;
1537 emit_reg((dreg),(reg));
1540 emit_rex(0,(dreg),0,(reg));
1541 *(cd->mcodeptr++) = 0x69;
1542 emit_reg((dreg),(reg));
1548 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1549 if (IS_IMM8((imm))) {
1550 emit_rex(1,(dreg),0,(basereg));
1551 *(cd->mcodeptr++) = 0x6b;
1552 emit_membase(cd, (basereg),(disp),(dreg));
1555 emit_rex(1,(dreg),0,(basereg));
1556 *(cd->mcodeptr++) = 0x69;
1557 emit_membase(cd, (basereg),(disp),(dreg));
1563 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1564 if (IS_IMM8((imm))) {
1565 emit_rex(0,(dreg),0,(basereg));
1566 *(cd->mcodeptr++) = 0x6b;
1567 emit_membase(cd, (basereg),(disp),(dreg));
1570 emit_rex(0,(dreg),0,(basereg));
1571 *(cd->mcodeptr++) = 0x69;
1572 emit_membase(cd, (basereg),(disp),(dreg));
1578 void emit_idiv_reg(codegendata *cd, s8 reg) {
1579 emit_rex(1,0,0,(reg));
1580 *(cd->mcodeptr++) = 0xf7;
1585 void emit_idivl_reg(codegendata *cd, s8 reg) {
1586 emit_rex(0,0,0,(reg));
1587 *(cd->mcodeptr++) = 0xf7;
1596 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1597 emit_rex(1,0,0,(reg));
1598 *(cd->mcodeptr++) = 0xd3;
1599 emit_reg((opc),(reg));
1603 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1604 emit_rex(0,0,0,(reg));
1605 *(cd->mcodeptr++) = 0xd3;
1606 emit_reg((opc),(reg));
1610 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1611 emit_rex(1,0,0,(basereg));
1612 *(cd->mcodeptr++) = 0xd3;
1613 emit_membase(cd, (basereg),(disp),(opc));
1617 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1618 emit_rex(0,0,0,(basereg));
1619 *(cd->mcodeptr++) = 0xd3;
1620 emit_membase(cd, (basereg),(disp),(opc));
1624 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1626 emit_rex(1,0,0,(dreg));
1627 *(cd->mcodeptr++) = 0xd1;
1628 emit_reg((opc),(dreg));
1630 emit_rex(1,0,0,(dreg));
1631 *(cd->mcodeptr++) = 0xc1;
1632 emit_reg((opc),(dreg));
1638 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1640 emit_rex(0,0,0,(dreg));
1641 *(cd->mcodeptr++) = 0xd1;
1642 emit_reg((opc),(dreg));
1644 emit_rex(0,0,0,(dreg));
1645 *(cd->mcodeptr++) = 0xc1;
1646 emit_reg((opc),(dreg));
1652 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1654 emit_rex(1,0,0,(basereg));
1655 *(cd->mcodeptr++) = 0xd1;
1656 emit_membase(cd, (basereg),(disp),(opc));
1658 emit_rex(1,0,0,(basereg));
1659 *(cd->mcodeptr++) = 0xc1;
1660 emit_membase(cd, (basereg),(disp),(opc));
1666 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1668 emit_rex(0,0,0,(basereg));
1669 *(cd->mcodeptr++) = 0xd1;
1670 emit_membase(cd, (basereg),(disp),(opc));
1672 emit_rex(0,0,0,(basereg));
1673 *(cd->mcodeptr++) = 0xc1;
1674 emit_membase(cd, (basereg),(disp),(opc));
1684 void emit_jmp_imm(codegendata *cd, s8 imm) {
1685 *(cd->mcodeptr++) = 0xe9;
1690 void emit_jmp_reg(codegendata *cd, s8 reg) {
1691 emit_rex(0,0,0,(reg));
1692 *(cd->mcodeptr++) = 0xff;
1697 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1698 *(cd->mcodeptr++) = 0x0f;
1699 *(cd->mcodeptr++) = (0x80 + (opc));
1706 * conditional set and move operations
1709 /* we need the rex byte to get all low bytes */
1710 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1712 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1713 *(cd->mcodeptr++) = 0x0f;
1714 *(cd->mcodeptr++) = (0x90 + (opc));
1719 /* we need the rex byte to get all low bytes */
1720 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1722 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1723 *(cd->mcodeptr++) = 0x0f;
1724 *(cd->mcodeptr++) = (0x90 + (opc));
1725 emit_membase(cd, (basereg),(disp),0);
1729 void emit_cmovcc_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1731 emit_rex(1,(dreg),0,(reg));
1732 *(cd->mcodeptr++) = 0x0f;
1733 *(cd->mcodeptr++) = (0x40 + (opc));
1734 emit_reg((dreg),(reg));
1738 void emit_cmovccl_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1740 emit_rex(0,(dreg),0,(reg));
1741 *(cd->mcodeptr++) = 0x0f;
1742 *(cd->mcodeptr++) = (0x40 + (opc));
1743 emit_reg((dreg),(reg));
1747 void emit_neg_reg(codegendata *cd, s8 reg)
1749 emit_rex(1,0,0,(reg));
1750 *(cd->mcodeptr++) = 0xf7;
1755 void emit_negl_reg(codegendata *cd, s8 reg)
1757 emit_rex(0,0,0,(reg));
1758 *(cd->mcodeptr++) = 0xf7;
1763 void emit_push_reg(codegendata *cd, s8 reg) {
1764 emit_rex(0,0,0,(reg));
1765 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1769 void emit_push_imm(codegendata *cd, s8 imm) {
1770 *(cd->mcodeptr++) = 0x68;
1775 void emit_pop_reg(codegendata *cd, s8 reg) {
1776 emit_rex(0,0,0,(reg));
1777 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1781 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1782 emit_rex(1,(reg),0,(dreg));
1783 *(cd->mcodeptr++) = 0x87;
1784 emit_reg((reg),(dreg));
1792 void emit_call_reg(codegendata *cd, s8 reg)
1794 emit_rex(0,0,0,(reg));
1795 *(cd->mcodeptr++) = 0xff;
1800 void emit_call_imm(codegendata *cd, s8 imm)
1802 *(cd->mcodeptr++) = 0xe8;
1807 void emit_call_mem(codegendata *cd, ptrint mem)
1809 *(cd->mcodeptr++) = 0xff;
1816 * floating point instructions (SSE2)
1818 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1819 *(cd->mcodeptr++) = 0xf2;
1820 emit_rex(0,(dreg),0,(reg));
1821 *(cd->mcodeptr++) = 0x0f;
1822 *(cd->mcodeptr++) = 0x58;
1823 emit_reg((dreg),(reg));
1827 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1828 *(cd->mcodeptr++) = 0xf3;
1829 emit_rex(0,(dreg),0,(reg));
1830 *(cd->mcodeptr++) = 0x0f;
1831 *(cd->mcodeptr++) = 0x58;
1832 emit_reg((dreg),(reg));
1836 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1837 *(cd->mcodeptr++) = 0xf3;
1838 emit_rex(1,(dreg),0,(reg));
1839 *(cd->mcodeptr++) = 0x0f;
1840 *(cd->mcodeptr++) = 0x2a;
1841 emit_reg((dreg),(reg));
1845 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1846 *(cd->mcodeptr++) = 0xf3;
1847 emit_rex(0,(dreg),0,(reg));
1848 *(cd->mcodeptr++) = 0x0f;
1849 *(cd->mcodeptr++) = 0x2a;
1850 emit_reg((dreg),(reg));
1854 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1855 *(cd->mcodeptr++) = 0xf2;
1856 emit_rex(1,(dreg),0,(reg));
1857 *(cd->mcodeptr++) = 0x0f;
1858 *(cd->mcodeptr++) = 0x2a;
1859 emit_reg((dreg),(reg));
1863 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1864 *(cd->mcodeptr++) = 0xf2;
1865 emit_rex(0,(dreg),0,(reg));
1866 *(cd->mcodeptr++) = 0x0f;
1867 *(cd->mcodeptr++) = 0x2a;
1868 emit_reg((dreg),(reg));
1872 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1873 *(cd->mcodeptr++) = 0xf3;
1874 emit_rex(0,(dreg),0,(reg));
1875 *(cd->mcodeptr++) = 0x0f;
1876 *(cd->mcodeptr++) = 0x5a;
1877 emit_reg((dreg),(reg));
1881 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1882 *(cd->mcodeptr++) = 0xf2;
1883 emit_rex(0,(dreg),0,(reg));
1884 *(cd->mcodeptr++) = 0x0f;
1885 *(cd->mcodeptr++) = 0x5a;
1886 emit_reg((dreg),(reg));
1890 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1891 *(cd->mcodeptr++) = 0xf3;
1892 emit_rex(1,(dreg),0,(reg));
1893 *(cd->mcodeptr++) = 0x0f;
1894 *(cd->mcodeptr++) = 0x2c;
1895 emit_reg((dreg),(reg));
1899 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1900 *(cd->mcodeptr++) = 0xf3;
1901 emit_rex(0,(dreg),0,(reg));
1902 *(cd->mcodeptr++) = 0x0f;
1903 *(cd->mcodeptr++) = 0x2c;
1904 emit_reg((dreg),(reg));
1908 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1909 *(cd->mcodeptr++) = 0xf2;
1910 emit_rex(1,(dreg),0,(reg));
1911 *(cd->mcodeptr++) = 0x0f;
1912 *(cd->mcodeptr++) = 0x2c;
1913 emit_reg((dreg),(reg));
1917 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1918 *(cd->mcodeptr++) = 0xf2;
1919 emit_rex(0,(dreg),0,(reg));
1920 *(cd->mcodeptr++) = 0x0f;
1921 *(cd->mcodeptr++) = 0x2c;
1922 emit_reg((dreg),(reg));
1926 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1927 *(cd->mcodeptr++) = 0xf3;
1928 emit_rex(0,(dreg),0,(reg));
1929 *(cd->mcodeptr++) = 0x0f;
1930 *(cd->mcodeptr++) = 0x5e;
1931 emit_reg((dreg),(reg));
1935 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1936 *(cd->mcodeptr++) = 0xf2;
1937 emit_rex(0,(dreg),0,(reg));
1938 *(cd->mcodeptr++) = 0x0f;
1939 *(cd->mcodeptr++) = 0x5e;
1940 emit_reg((dreg),(reg));
1944 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1945 *(cd->mcodeptr++) = 0x66;
1946 emit_rex(1,(freg),0,(reg));
1947 *(cd->mcodeptr++) = 0x0f;
1948 *(cd->mcodeptr++) = 0x6e;
1949 emit_reg((freg),(reg));
1953 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1954 *(cd->mcodeptr++) = 0x66;
1955 emit_rex(1,(freg),0,(reg));
1956 *(cd->mcodeptr++) = 0x0f;
1957 *(cd->mcodeptr++) = 0x7e;
1958 emit_reg((freg),(reg));
1962 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1963 *(cd->mcodeptr++) = 0x66;
1964 emit_rex(0,(reg),0,(basereg));
1965 *(cd->mcodeptr++) = 0x0f;
1966 *(cd->mcodeptr++) = 0x7e;
1967 emit_membase(cd, (basereg),(disp),(reg));
1971 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1972 *(cd->mcodeptr++) = 0x66;
1973 emit_rex(0,(reg),(indexreg),(basereg));
1974 *(cd->mcodeptr++) = 0x0f;
1975 *(cd->mcodeptr++) = 0x7e;
1976 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1980 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1981 *(cd->mcodeptr++) = 0x66;
1982 emit_rex(1,(dreg),0,(basereg));
1983 *(cd->mcodeptr++) = 0x0f;
1984 *(cd->mcodeptr++) = 0x6e;
1985 emit_membase(cd, (basereg),(disp),(dreg));
1989 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1990 *(cd->mcodeptr++) = 0x66;
1991 emit_rex(0,(dreg),0,(basereg));
1992 *(cd->mcodeptr++) = 0x0f;
1993 *(cd->mcodeptr++) = 0x6e;
1994 emit_membase(cd, (basereg),(disp),(dreg));
1998 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
1999 *(cd->mcodeptr++) = 0x66;
2000 emit_rex(0,(dreg),(indexreg),(basereg));
2001 *(cd->mcodeptr++) = 0x0f;
2002 *(cd->mcodeptr++) = 0x6e;
2003 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2007 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2008 *(cd->mcodeptr++) = 0xf3;
2009 emit_rex(0,(dreg),0,(reg));
2010 *(cd->mcodeptr++) = 0x0f;
2011 *(cd->mcodeptr++) = 0x7e;
2012 emit_reg((dreg),(reg));
2016 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2017 *(cd->mcodeptr++) = 0x66;
2018 emit_rex(0,(reg),0,(basereg));
2019 *(cd->mcodeptr++) = 0x0f;
2020 *(cd->mcodeptr++) = 0xd6;
2021 emit_membase(cd, (basereg),(disp),(reg));
2025 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2026 *(cd->mcodeptr++) = 0xf3;
2027 emit_rex(0,(dreg),0,(basereg));
2028 *(cd->mcodeptr++) = 0x0f;
2029 *(cd->mcodeptr++) = 0x7e;
2030 emit_membase(cd, (basereg),(disp),(dreg));
2034 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2035 *(cd->mcodeptr++) = 0xf3;
2036 emit_rex(0,(reg),0,(dreg));
2037 *(cd->mcodeptr++) = 0x0f;
2038 *(cd->mcodeptr++) = 0x10;
2039 emit_reg((reg),(dreg));
2043 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2044 *(cd->mcodeptr++) = 0xf2;
2045 emit_rex(0,(reg),0,(dreg));
2046 *(cd->mcodeptr++) = 0x0f;
2047 *(cd->mcodeptr++) = 0x10;
2048 emit_reg((reg),(dreg));
2052 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2053 *(cd->mcodeptr++) = 0xf3;
2054 emit_rex(0,(reg),0,(basereg));
2055 *(cd->mcodeptr++) = 0x0f;
2056 *(cd->mcodeptr++) = 0x11;
2057 emit_membase(cd, (basereg),(disp),(reg));
2061 /* Always emit a REX byte, because the instruction size can be smaller when */
2062 /* all register indexes are smaller than 7. */
2063 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2064 *(cd->mcodeptr++) = 0xf3;
2065 emit_byte_rex((reg),0,(basereg));
2066 *(cd->mcodeptr++) = 0x0f;
2067 *(cd->mcodeptr++) = 0x11;
2068 emit_membase32(cd, (basereg),(disp),(reg));
2072 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2073 *(cd->mcodeptr++) = 0xf2;
2074 emit_rex(0,(reg),0,(basereg));
2075 *(cd->mcodeptr++) = 0x0f;
2076 *(cd->mcodeptr++) = 0x11;
2077 emit_membase(cd, (basereg),(disp),(reg));
2081 /* Always emit a REX byte, because the instruction size can be smaller when */
2082 /* all register indexes are smaller than 7. */
2083 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2084 *(cd->mcodeptr++) = 0xf2;
2085 emit_byte_rex((reg),0,(basereg));
2086 *(cd->mcodeptr++) = 0x0f;
2087 *(cd->mcodeptr++) = 0x11;
2088 emit_membase32(cd, (basereg),(disp),(reg));
2092 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2093 *(cd->mcodeptr++) = 0xf3;
2094 emit_rex(0,(dreg),0,(basereg));
2095 *(cd->mcodeptr++) = 0x0f;
2096 *(cd->mcodeptr++) = 0x10;
2097 emit_membase(cd, (basereg),(disp),(dreg));
2101 /* Always emit a REX byte, because the instruction size can be smaller when */
2102 /* all register indexes are smaller than 7. */
2103 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2104 *(cd->mcodeptr++) = 0xf3;
2105 emit_byte_rex((dreg),0,(basereg));
2106 *(cd->mcodeptr++) = 0x0f;
2107 *(cd->mcodeptr++) = 0x10;
2108 emit_membase32(cd, (basereg),(disp),(dreg));
2112 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2114 emit_rex(0,(dreg),0,(basereg));
2115 *(cd->mcodeptr++) = 0x0f;
2116 *(cd->mcodeptr++) = 0x12;
2117 emit_membase(cd, (basereg),(disp),(dreg));
2121 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2123 emit_rex(0,(reg),0,(basereg));
2124 *(cd->mcodeptr++) = 0x0f;
2125 *(cd->mcodeptr++) = 0x13;
2126 emit_membase(cd, (basereg),(disp),(reg));
2130 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2131 *(cd->mcodeptr++) = 0xf2;
2132 emit_rex(0,(dreg),0,(basereg));
2133 *(cd->mcodeptr++) = 0x0f;
2134 *(cd->mcodeptr++) = 0x10;
2135 emit_membase(cd, (basereg),(disp),(dreg));
2139 /* Always emit a REX byte, because the instruction size can be smaller when */
2140 /* all register indexes are smaller than 7. */
2141 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2142 *(cd->mcodeptr++) = 0xf2;
2143 emit_byte_rex((dreg),0,(basereg));
2144 *(cd->mcodeptr++) = 0x0f;
2145 *(cd->mcodeptr++) = 0x10;
2146 emit_membase32(cd, (basereg),(disp),(dreg));
2150 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2152 *(cd->mcodeptr++) = 0x66;
2153 emit_rex(0,(dreg),0,(basereg));
2154 *(cd->mcodeptr++) = 0x0f;
2155 *(cd->mcodeptr++) = 0x12;
2156 emit_membase(cd, (basereg),(disp),(dreg));
2160 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2162 *(cd->mcodeptr++) = 0x66;
2163 emit_rex(0,(reg),0,(basereg));
2164 *(cd->mcodeptr++) = 0x0f;
2165 *(cd->mcodeptr++) = 0x13;
2166 emit_membase(cd, (basereg),(disp),(reg));
2170 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2171 *(cd->mcodeptr++) = 0xf3;
2172 emit_rex(0,(reg),(indexreg),(basereg));
2173 *(cd->mcodeptr++) = 0x0f;
2174 *(cd->mcodeptr++) = 0x11;
2175 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2179 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2180 *(cd->mcodeptr++) = 0xf2;
2181 emit_rex(0,(reg),(indexreg),(basereg));
2182 *(cd->mcodeptr++) = 0x0f;
2183 *(cd->mcodeptr++) = 0x11;
2184 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2188 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2189 *(cd->mcodeptr++) = 0xf3;
2190 emit_rex(0,(dreg),(indexreg),(basereg));
2191 *(cd->mcodeptr++) = 0x0f;
2192 *(cd->mcodeptr++) = 0x10;
2193 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2197 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2198 *(cd->mcodeptr++) = 0xf2;
2199 emit_rex(0,(dreg),(indexreg),(basereg));
2200 *(cd->mcodeptr++) = 0x0f;
2201 *(cd->mcodeptr++) = 0x10;
2202 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2206 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2207 *(cd->mcodeptr++) = 0xf3;
2208 emit_rex(0,(dreg),0,(reg));
2209 *(cd->mcodeptr++) = 0x0f;
2210 *(cd->mcodeptr++) = 0x59;
2211 emit_reg((dreg),(reg));
2215 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2216 *(cd->mcodeptr++) = 0xf2;
2217 emit_rex(0,(dreg),0,(reg));
2218 *(cd->mcodeptr++) = 0x0f;
2219 *(cd->mcodeptr++) = 0x59;
2220 emit_reg((dreg),(reg));
2224 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2225 *(cd->mcodeptr++) = 0xf3;
2226 emit_rex(0,(dreg),0,(reg));
2227 *(cd->mcodeptr++) = 0x0f;
2228 *(cd->mcodeptr++) = 0x5c;
2229 emit_reg((dreg),(reg));
2233 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2234 *(cd->mcodeptr++) = 0xf2;
2235 emit_rex(0,(dreg),0,(reg));
2236 *(cd->mcodeptr++) = 0x0f;
2237 *(cd->mcodeptr++) = 0x5c;
2238 emit_reg((dreg),(reg));
2242 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2243 emit_rex(0,(dreg),0,(reg));
2244 *(cd->mcodeptr++) = 0x0f;
2245 *(cd->mcodeptr++) = 0x2e;
2246 emit_reg((dreg),(reg));
2250 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2251 *(cd->mcodeptr++) = 0x66;
2252 emit_rex(0,(dreg),0,(reg));
2253 *(cd->mcodeptr++) = 0x0f;
2254 *(cd->mcodeptr++) = 0x2e;
2255 emit_reg((dreg),(reg));
2259 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2260 emit_rex(0,(dreg),0,(reg));
2261 *(cd->mcodeptr++) = 0x0f;
2262 *(cd->mcodeptr++) = 0x57;
2263 emit_reg((dreg),(reg));
2267 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2268 emit_rex(0,(dreg),0,(basereg));
2269 *(cd->mcodeptr++) = 0x0f;
2270 *(cd->mcodeptr++) = 0x57;
2271 emit_membase(cd, (basereg),(disp),(dreg));
2275 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2276 *(cd->mcodeptr++) = 0x66;
2277 emit_rex(0,(dreg),0,(reg));
2278 *(cd->mcodeptr++) = 0x0f;
2279 *(cd->mcodeptr++) = 0x57;
2280 emit_reg((dreg),(reg));
2284 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2285 *(cd->mcodeptr++) = 0x66;
2286 emit_rex(0,(dreg),0,(basereg));
2287 *(cd->mcodeptr++) = 0x0f;
2288 *(cd->mcodeptr++) = 0x57;
2289 emit_membase(cd, (basereg),(disp),(dreg));
2293 /* system instructions ********************************************************/
2295 void emit_rdtsc(codegendata *cd)
2297 *(cd->mcodeptr++) = 0x0f;
2298 *(cd->mcodeptr++) = 0x31;
2303 * These are local overrides for various environment variables in Emacs.
2304 * Please do not remove this and leave it at the end of the file, where
2305 * Emacs will automagically detect them.
2306 * ---------------------------------------------------------------------
2309 * indent-tabs-mode: t