1 /* src/vm/jit/x86_64/codegen.h - code generation macros for x86_64
3 Copyright (C) 1996-2005 R. Grafl, A. Krall, C. Kruegel, C. Oates,
4 R. Obermaisser, M. Platter, M. Probst, S. Ring, E. Steiner,
5 C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, J. Wenninger,
6 Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
25 Contact: cacao@complang.tuwien.ac.at
27 Authors: Andreas Krall
31 $Id: codegen.h 3275 2005-09-21 21:18:35Z twisti $
43 /* macros to create code ******************************************************/
45 /* immediate data union */
57 /* opcodes for alu instructions */
81 } X86_64_Shift_Opcode;
87 X86_64_CC_B = 2, X86_64_CC_C = 2, X86_64_CC_NAE = 2,
88 X86_64_CC_BE = 6, X86_64_CC_NA = 6,
89 X86_64_CC_AE = 3, X86_64_CC_NB = 3, X86_64_CC_NC = 3,
90 X86_64_CC_E = 4, X86_64_CC_Z = 4,
91 X86_64_CC_NE = 5, X86_64_CC_NZ = 5,
92 X86_64_CC_A = 7, X86_64_CC_NBE = 7,
93 X86_64_CC_S = 8, X86_64_CC_LZ = 8,
94 X86_64_CC_NS = 9, X86_64_CC_GEZ = 9,
95 X86_64_CC_P = 0x0a, X86_64_CC_PE = 0x0a,
96 X86_64_CC_NP = 0x0b, X86_64_CC_PO = 0x0b,
97 X86_64_CC_L = 0x0c, X86_64_CC_NGE = 0x0c,
98 X86_64_CC_GE = 0x0d, X86_64_CC_NL = 0x0d,
99 X86_64_CC_LE = 0x0e, X86_64_CC_NG = 0x0e,
100 X86_64_CC_G = 0x0f, X86_64_CC_NLE = 0x0f,
105 #define IS_IMM8(imm) \
106 (((long) (imm) >= -128) && ((long) (imm) <= 127))
109 #define IS_IMM32(imm) \
110 (((long) (imm) >= (-2147483647-1)) && ((long) (imm) <= 2147483647))
113 /* modrm and stuff */
115 #define x86_64_address_byte(mod,reg,rm) \
116 *(cd->mcodeptr++) = ((((mod) & 0x03) << 6) | (((reg) & 0x07) << 3) | ((rm) & 0x07));
119 #define x86_64_emit_reg(reg,rm) \
120 x86_64_address_byte(3,(reg),(rm));
123 #define x86_64_emit_rex(size,reg,index,rm) \
124 if ((size) == 1 || (reg) > 7 || (index) > 7 || (rm) > 7) { \
125 *(cd->mcodeptr++) = (0x40 | (((size) & 0x01) << 3) | ((((reg) >> 3) & 0x01) << 2) | ((((index) >> 3) & 0x01) << 1) | (((rm) >> 3) & 0x01)); \
129 #define x86_64_emit_byte_rex(reg,index,rm) \
130 *(cd->mcodeptr++) = (0x40 | ((((reg) >> 3) & 0x01) << 2) | ((((index) >> 3) & 0x01) << 1) | (((rm) >> 3) & 0x01));
133 #define x86_64_emit_mem(r,disp) \
135 x86_64_address_byte(0,(r),5); \
136 x86_64_emit_imm32((disp)); \
140 #define x86_64_emit_membase(basereg,disp,dreg) \
142 if ((basereg) == REG_SP || (basereg) == R12) { \
144 x86_64_address_byte(0,(dreg),REG_SP); \
145 x86_64_address_byte(0,REG_SP,REG_SP); \
146 } else if (IS_IMM8((disp))) { \
147 x86_64_address_byte(1,(dreg),REG_SP); \
148 x86_64_address_byte(0,REG_SP,REG_SP); \
149 x86_64_emit_imm8((disp)); \
151 x86_64_address_byte(2,(dreg),REG_SP); \
152 x86_64_address_byte(0,REG_SP,REG_SP); \
153 x86_64_emit_imm32((disp)); \
157 if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) { \
158 x86_64_address_byte(0,(dreg),(basereg)); \
162 if ((basereg) == RIP) { \
163 x86_64_address_byte(0,(dreg),RBP); \
164 x86_64_emit_imm32((disp)); \
168 if (IS_IMM8((disp))) { \
169 x86_64_address_byte(1,(dreg),(basereg)); \
170 x86_64_emit_imm8((disp)); \
172 x86_64_address_byte(2,(dreg),(basereg)); \
173 x86_64_emit_imm32((disp)); \
178 #define x86_64_emit_membase32(basereg,disp,dreg) \
180 if ((basereg) == REG_SP || (basereg) == R12) { \
181 x86_64_address_byte(2,(dreg),REG_SP); \
182 x86_64_address_byte(0,REG_SP,REG_SP); \
183 x86_64_emit_imm32((disp)); \
185 x86_64_address_byte(2,(dreg),(basereg)); \
186 x86_64_emit_imm32((disp)); \
191 #define x86_64_emit_memindex(reg,disp,basereg,indexreg,scale) \
193 if ((basereg) == -1) { \
194 x86_64_address_byte(0,(reg),4); \
195 x86_64_address_byte((scale),(indexreg),5); \
196 x86_64_emit_imm32((disp)); \
198 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) { \
199 x86_64_address_byte(0,(reg),4); \
200 x86_64_address_byte((scale),(indexreg),(basereg)); \
202 } else if (IS_IMM8((disp))) { \
203 x86_64_address_byte(1,(reg),4); \
204 x86_64_address_byte((scale),(indexreg),(basereg)); \
205 x86_64_emit_imm8 ((disp)); \
208 x86_64_address_byte(2,(reg),4); \
209 x86_64_address_byte((scale),(indexreg),(basereg)); \
210 x86_64_emit_imm32((disp)); \
215 #define x86_64_emit_imm8(imm) \
216 *(cd->mcodeptr++) = (u1) ((imm) & 0xff);
219 #define x86_64_emit_imm16(imm) \
221 x86_64_imm_buf imb; \
222 imb.i = (s4) (imm); \
223 *(cd->mcodeptr++) = imb.b[0]; \
224 *(cd->mcodeptr++) = imb.b[1]; \
228 #define x86_64_emit_imm32(imm) \
230 x86_64_imm_buf imb; \
231 imb.i = (s4) (imm); \
232 *(cd->mcodeptr++) = imb.b[0]; \
233 *(cd->mcodeptr++) = imb.b[1]; \
234 *(cd->mcodeptr++) = imb.b[2]; \
235 *(cd->mcodeptr++) = imb.b[3]; \
239 #define x86_64_emit_imm64(imm) \
241 x86_64_imm_buf imb; \
242 imb.l = (s8) (imm); \
243 *(cd->mcodeptr++) = imb.b[0]; \
244 *(cd->mcodeptr++) = imb.b[1]; \
245 *(cd->mcodeptr++) = imb.b[2]; \
246 *(cd->mcodeptr++) = imb.b[3]; \
247 *(cd->mcodeptr++) = imb.b[4]; \
248 *(cd->mcodeptr++) = imb.b[5]; \
249 *(cd->mcodeptr++) = imb.b[6]; \
250 *(cd->mcodeptr++) = imb.b[7]; \
254 /* additional functions and macros to generate code ***************************/
257 #define COUNT_SPILLS count_spills++
263 #define CALCOFFSETBYTES(var, reg, val) \
264 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
265 else if ((s4) (val) != 0) (var) += 1; \
266 else if ((reg) == RBP || (reg) == RSP || (reg) == R12 || (reg) == R13) (var) += 1;
269 #define CALCIMMEDIATEBYTES(var, val) \
270 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
274 /* gen_nullptr_check(objreg) */
276 #define gen_nullptr_check(objreg) \
278 x86_64_test_reg_reg(cd, (objreg), (objreg)); \
279 x86_64_jcc(cd, X86_64_CC_E, 0); \
280 codegen_addxnullrefs(cd, cd->mcodeptr); \
284 #define gen_bound_check \
286 x86_64_alul_membase_reg(cd, X86_64_CMP, s1, OFFSET(java_arrayheader, size), s2); \
287 x86_64_jcc(cd, X86_64_CC_AE, 0); \
288 codegen_addxboundrefs(cd, cd->mcodeptr, s2); \
292 #define gen_div_check(v) \
294 if ((v)->flags & INMEMORY) { \
295 x86_64_alu_imm_membase(cd, X86_64_CMP, 0, REG_SP, src->regoff * 8); \
297 x86_64_test_reg_reg(cd, src->regoff, src->regoff); \
299 x86_64_jcc(cd, X86_64_CC_E, 0); \
300 codegen_addxdivrefs(cd, cd->mcodeptr); \
304 /* MCODECHECK(icnt) */
306 #define MCODECHECK(icnt) \
307 if ((cd->mcodeptr + (icnt)) > (u1 *) cd->mcodeend) \
308 cd->mcodeptr = (u1 *) codegen_increase(cd, cd->mcodeptr)
311 generates an integer-move from register a to b.
312 if a and b are the same int-register, no code will be generated.
315 #define M_INTMOVE(reg,dreg) \
316 if ((reg) != (dreg)) { \
317 x86_64_mov_reg_reg(cd, (reg),(dreg)); \
322 generates a floating-point-move from register a to b.
323 if a and b are the same float-register, no code will be generated
326 #define M_FLTMOVE(reg,dreg) \
327 if ((reg) != (dreg)) { \
328 x86_64_movq_reg_reg(cd, (reg),(dreg)); \
333 this function generates code to fetch data from a pseudo-register
334 into a real register.
335 If the pseudo-register has actually been assigned to a real
336 register, no code will be emitted, since following operations
337 can use this register directly.
339 v: pseudoregister to be fetched from
340 tempregnum: temporary register to be used if v is actually spilled to ram
342 return: the register number, where the operand can be found after
343 fetching (this wil be either tempregnum or the register
344 number allready given to v)
347 #define var_to_reg_int(regnr,v,tempnr) \
348 if ((v)->flags & INMEMORY) { \
350 if ((v)->type == TYPE_INT) { \
351 x86_64_movl_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
353 x86_64_mov_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
357 regnr = (v)->regoff; \
362 #define var_to_reg_flt(regnr,v,tempnr) \
363 if ((v)->flags & INMEMORY) { \
365 if ((v)->type == TYPE_FLT) { \
366 x86_64_movlps_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
368 x86_64_movlpd_membase_reg(cd, REG_SP, (v)->regoff * 8, tempnr); \
370 /* x86_64_movq_membase_reg(REG_SP, (v)->regoff * 8, tempnr);*/ \
373 regnr = (v)->regoff; \
377 /* store_reg_to_var_xxx:
378 This function generates the code to store the result of an operation
379 back into a spilled pseudo-variable.
380 If the pseudo-variable has not been spilled in the first place, this
381 function will generate nothing.
383 v ............ Pseudovariable
384 tempregnum ... Number of the temporary registers as returned by
388 #define store_reg_to_var_int(sptr, tempregnum) \
389 if ((sptr)->flags & INMEMORY) { \
391 x86_64_mov_reg_membase(cd, tempregnum, REG_SP, (sptr)->regoff * 8); \
395 #define store_reg_to_var_flt(sptr, tempregnum) \
396 if ((sptr)->flags & INMEMORY) { \
398 x86_64_movq_reg_membase(cd, tempregnum, REG_SP, (sptr)->regoff * 8); \
402 #define M_COPY(from,to) \
403 d = reg_of_var(rd, to, REG_ITMP1); \
404 if ((from->regoff != to->regoff) || \
405 ((from->flags ^ to->flags) & INMEMORY)) { \
406 if (IS_FLT_DBL_TYPE(from->type)) { \
407 var_to_reg_flt(s1, from, d); \
409 store_reg_to_var_flt(to, d); \
411 var_to_reg_int(s1, from, d); \
413 store_reg_to_var_int(to, d); \
418 /* macros to create code ******************************************************/
420 #define M_MOV(a,b) x86_64_mov_reg_reg(cd, (a), (b))
421 #define M_MOV_IMM(a,b) x86_64_mov_imm_reg(cd, (a), (b))
423 #define M_ILD(a,b,disp) x86_64_movl_membase_reg(cd, (b), (disp), (a))
424 #define M_LLD(a,b,disp) x86_64_mov_membase_reg(cd, (b), (disp), (a))
425 #define M_DLD(a,b,disp) x86_64_movq_membase_reg(cd, (b), (disp), (a))
427 #define M_IST(a,b,disp) x86_64_movl_reg_membase(cd, (a), (b), (disp))
428 #define M_LST(a,b,disp) x86_64_mov_reg_membase(cd, (a), (b), (disp))
429 #define M_DST(a,b,disp) x86_64_movq_reg_membase(cd, (a), (b), (disp))
431 #define M_LADD(a,b) x86_64_alu_reg_reg(cd, X86_64_ADD, (a), (b))
432 #define M_LADD_IMM(a,b) x86_64_alu_imm_reg(cd, X86_64_ADD, (a), (b))
433 #define M_LSUB_IMM(a,b) x86_64_alu_imm_reg(cd, X86_64_SUB, (a), (b))
435 #define M_ALD(a,b,c) M_LLD(a,b,c)
436 #define M_AST(a,b,c) M_LST(a,b,c)
437 #define M_AADD(a,b) M_LADD(a,b)
438 #define M_AADD_IMM(a,b) M_LADD_IMM(a,b)
439 #define M_ASUB_IMM(a,b) M_LSUB_IMM(a,b)
441 #define M_LADD_IMM32(a,b) x86_64_alu_imm32_reg(cd, X86_64_ADD, (a), (b))
442 #define M_AADD_IMM32(a,b) M_LADD_IMM32(a,b)
444 #define M_ILEA(a,b,c) x86_64_leal_membase_reg(cd, (a), (b), (c))
445 #define M_LLEA(a,b,c) x86_64_lea_membase_reg(cd, (a), (b), (c))
446 #define M_ALEA(a,b,c) M_LLEA(a,b,c)
448 #define M_TEST(a) x86_64_test_reg_reg(cd, (a), (a))
450 #define M_BEQ(disp) x86_64_jcc(cd, X86_64_CC_E, (disp))
452 #define M_PUSH(a) x86_64_push_reg(cd, (a))
453 #define M_PUSH_IMM(a) x86_64_push_imm(cd, (a))
455 #define M_JMP(a) x86_64_jmp_reg(cd, (a))
456 #define M_JMP_IMM(a) x86_64_jmp_imm(cd, (a))
457 #define M_CALL(a) x86_64_call_reg(cd, (a))
458 #define M_RET x86_64_ret(cd)
460 #define M_NOP x86_64_nop(cd)
463 /* function gen_resolvebranch **************************************************
465 backpatches a branch instruction
467 parameters: ip ... pointer to instruction after branch (void*)
468 so ... offset of instruction after branch (s8)
469 to ... offset of branch target (s8)
471 *******************************************************************************/
473 #define gen_resolvebranch(ip,so,to) \
474 *((s4*) ((ip) - 4)) = (s4) ((to) - (so));
476 #endif /* _CODEGEN_H */
480 * These are local overrides for various environment variables in Emacs.
481 * Please do not remove this and leave it at the end of the file, where
482 * Emacs will automagically detect them.
483 * ---------------------------------------------------------------------
486 * indent-tabs-mode: t