1 /* src/vm/jit/s390/emit.c - s390 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 8296 2007-08-11 22:38:38Z pm $
34 #include "mm/memory.h"
35 #if defined(ENABLE_THREADS)
36 # include "threads/native/lock.h"
38 #include "vm/builtin.h"
39 #include "vm/exceptions.h"
40 #include "vm/global.h"
41 #include "vm/jit/abi.h"
42 #include "vm/jit/abi-asm.h"
43 #include "vm/jit/asmpart.h"
44 #include "vm/jit/codegen-common.h"
45 #include "vm/jit/emit-common.h"
46 #include "vm/jit/jit.h"
47 #include "vm/jit/patcher-common.h"
48 #include "vm/jit/replace.h"
49 #include "vm/jit/s390/codegen.h"
50 #include "vm/jit/s390/emit.h"
51 #include "vm/jit/s390/md-abi.h"
53 #include "vmcore/options.h"
55 /* emit_load *******************************************************************
57 Emits a possible load of an operand.
59 *******************************************************************************/
61 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
67 /* get required compiler data */
71 if (IS_INMEMORY(src->flags)) {
74 disp = src->vv.regoff;
76 if (IS_FLT_DBL_TYPE(src->type)) {
77 if (IS_2_WORD_TYPE(src->type))
78 M_DLD(tempreg, REG_SP, disp);
80 M_FLD(tempreg, REG_SP, disp);
83 if (IS_2_WORD_TYPE(src->type))
84 M_LLD(tempreg, REG_SP, disp);
86 M_ILD(tempreg, REG_SP, disp);
98 /* emit_store ******************************************************************
100 This function generates the code to store the result of an
101 operation back into a spilled pseudo-variable. If the
102 pseudo-variable has not been spilled in the first place, this
103 function will generate nothing.
105 *******************************************************************************/
107 void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
111 /* get required compiler data */
115 if (IS_INMEMORY(dst->flags)) {
118 if (IS_FLT_DBL_TYPE(dst->type)) {
119 if (IS_2_WORD_TYPE(dst->type))
120 M_DST(d, REG_SP, dst->vv.regoff);
122 M_FST(d, REG_SP, dst->vv.regoff);
125 if (IS_2_WORD_TYPE(dst->type))
126 M_LST(d, REG_SP, dst->vv.regoff);
128 M_IST(d, REG_SP, dst->vv.regoff);
134 /* emit_copy *******************************************************************
136 Generates a register/memory to register/memory copy.
138 *******************************************************************************/
140 void emit_copy(jitdata *jd, instruction *iptr)
147 /* get required compiler data */
151 /* get source and destination variables */
153 src = VAROP(iptr->s1);
154 dst = VAROP(iptr->dst);
156 if ((src->vv.regoff != dst->vv.regoff) ||
157 ((src->flags ^ dst->flags) & INMEMORY)) {
159 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
160 /* emit nothing, as the value won't be used anyway */
164 /* If one of the variables resides in memory, we can eliminate
165 the register move from/to the temporary register with the
166 order of getting the destination register and the load. */
168 if (IS_INMEMORY(src->flags)) {
169 if (IS_FLT_DBL_TYPE(dst->type)) {
170 d = codegen_reg_of_var(iptr->opc, dst, REG_FTMP1);
172 if (IS_2_WORD_TYPE(dst->type)) {
173 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
175 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP1);
178 s1 = emit_load(jd, iptr, src, d);
181 if (IS_FLT_DBL_TYPE(src->type)) {
182 s1 = emit_load(jd, iptr, src, REG_FTMP1);
184 if (IS_2_WORD_TYPE(src->type)) {
185 s1 = emit_load(jd, iptr, src, REG_ITMP12_PACKED);
187 s1 = emit_load(jd, iptr, src, REG_ITMP1);
190 d = codegen_reg_of_var(iptr->opc, dst, s1);
194 if (IS_FLT_DBL_TYPE(src->type)) {
197 if (IS_2_WORD_TYPE(src->type)) {
205 emit_store(jd, iptr, dst, d);
209 /* emit_trap *******************************************************************
211 Emit a trap instruction and return the original machine code.
213 *******************************************************************************/
215 uint32_t emit_trap(codegendata *cd)
219 /* Get machine code which is patched back in later. The
220 trap is 2 bytes long. */
222 mcode = *((u2 *) cd->mcodeptr);
224 M_ILL(EXCEPTION_HARDWARE_PATCHER);
230 /* emit_verbosecall_enter ******************************************************
232 Generates the code for the call trace.
234 *******************************************************************************/
237 void emit_verbosecall_enter(jitdata *jd)
244 s4 stackframesize, off, foff, aoff, doff, t, iargctr, fargctr, disp;
246 /* get required compiler data */
253 /* mark trace code */
258 (6 * 8) + /* s8 on stack parameters x 6 */
259 (1 * 4) + /* methodinfo on stack parameter */
264 M_ASUB_IMM(stackframesize, REG_SP); /* allocate stackframe */
266 /* save argument registers */
268 off = (6 * 8) + (1 * 4);
270 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
271 M_IST(abi_registers_integer_argument[i], REG_SP, off);
273 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
274 M_DST(abi_registers_float_argument[i], REG_SP, off);
276 /* save temporary registers for leaf methods */
278 if (jd->isleafmethod) {
279 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
280 M_LST(abi_registers_integer_temporary[i], REG_SP, off);
282 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
283 M_DST(abi_registers_float_temporary[i], REG_SP, off);
286 /* Load arguments to new locations */
288 /* First move all arguments to stack
293 * (s8) a1 \ Auxilliary stack frame
298 M_ASUB_IMM(2 * 8, REG_SP);
300 /* offset to where first integer arg is saved on stack */
301 off = (2 * 8) + (6 * 8) + (1 * 4);
302 /* offset to where first float arg is saved on stack */
303 foff = off + (INT_ARG_CNT * 8);
304 /* offset to where first argument is passed on stack */
305 aoff = (2 * 8) + stackframesize + (cd->stackframesize * 8);
306 /* offset to destination on stack */
309 iargctr = fargctr = 0;
311 ICONST(REG_ITMP1, 0);
313 for (i = 0; i < md->paramcount && i < 8; i++) {
314 t = md->paramtypes[i].type;
316 M_IST(REG_ITMP1, REG_SP, doff);
317 M_IST(REG_ITMP1, REG_SP, doff + 4);
319 if (IS_FLT_DBL_TYPE(t)) {
320 if (fargctr < 2) { /* passed in register */
321 N_STD(abi_registers_float_argument[fargctr], doff, RN, REG_SP);
323 } else { /* passed on stack */
325 if (IS_2_WORD_TYPE(t)) {
326 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
328 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
331 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
335 if (IS_2_WORD_TYPE(t)) {
336 if (iargctr < 4) { /* passed in 2 registers */
337 N_STM(REG_A0 + iargctr, REG_A0 + iargctr + 1, doff, REG_SP);
339 } else { /* passed on stack */
340 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
344 if (iargctr < 5) { /* passed in register */
345 N_ST(REG_A0 + iargctr, doff + 4, RN, REG_SP);
347 } else { /* passed on stack */
348 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
357 /* Now move a0 and a1 to registers
367 N_LM(REG_A0, REG_A1, 0, REG_SP);
368 N_LM(REG_A2, REG_A3, 8, REG_SP);
370 M_AADD_IMM(2 * 8, REG_SP);
372 /* Finally load methodinfo argument */
374 disp = dseg_add_address(cd, m);
375 M_ALD_DSEG(REG_ITMP2, disp);
376 M_AST(REG_ITMP2, REG_SP, 6 * 8);
378 /* Call builtin_verbosecall_enter */
380 disp = dseg_add_address(cd, builtin_verbosecall_enter);
381 M_ALD_DSEG(REG_ITMP2, disp);
382 M_ASUB_IMM(96, REG_SP);
384 M_AADD_IMM(96, REG_SP);
386 /* restore argument registers */
388 off = (6 * 8) + (1 * 4);
390 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
391 M_ILD(abi_registers_integer_argument[i], REG_SP, off);
393 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
394 M_DLD(abi_registers_float_argument[i], REG_SP, off);
396 /* restore temporary registers for leaf methods */
398 if (jd->isleafmethod) {
399 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
400 M_ILD(abi_registers_integer_temporary[i], REG_SP, off);
402 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
403 M_DLD(abi_registers_float_temporary[i], REG_SP, off);
406 /* remove stackframe */
408 M_AADD_IMM(stackframesize, REG_SP);
410 /* mark trace code */
414 #endif /* !defined(NDEBUG) */
417 /* emit_verbosecall_exit *******************************************************
419 Generates the code for the call trace.
421 *******************************************************************************/
424 void emit_verbosecall_exit(jitdata *jd)
431 /* get required compiler data */
437 /* mark trace code */
441 M_ASUB_IMM(2 * 8, REG_SP);
443 N_STM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
444 M_DST(REG_FRESULT, REG_SP, 1 * 8);
446 if (IS_2_WORD_TYPE(m->parseddesc->returntype.type)) {
447 /* (REG_A0, REG_A1) == (REG_RESULT, REG_RESULT2), se no need to move */
449 M_INTMOVE(REG_RESULT, REG_A1);
453 disp = dseg_add_address(cd, m);
454 M_ALD_DSEG(REG_A2, disp);
456 /* REG_FRESULT is REG_FA0, so no need to move */
457 M_FLTMOVE(REG_FRESULT, REG_FA1);
459 disp = dseg_add_address(cd, builtin_verbosecall_exit);
460 M_ALD_DSEG(REG_ITMP1, disp);
461 M_ASUB_IMM(96, REG_SP);
463 M_AADD_IMM(96, REG_SP);
465 N_LM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
466 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
468 M_AADD_IMM(2 * 8, REG_SP);
470 /* mark trace code */
474 #endif /* !defined(NDEBUG) */
477 /* emit_load_high **************************************************************
479 Emits a possible load of the high 32-bits of an operand.
481 *******************************************************************************/
483 s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
489 assert(src->type == TYPE_LNG);
491 /* get required compiler data */
495 if (IS_INMEMORY(src->flags)) {
498 disp = src->vv.regoff;
500 M_ILD(tempreg, REG_SP, disp);
505 reg = GET_HIGH_REG(src->vv.regoff);
510 /* emit_load_low ***************************************************************
512 Emits a possible load of the low 32-bits of an operand.
514 *******************************************************************************/
516 s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
522 assert(src->type == TYPE_LNG);
524 /* get required compiler data */
528 if (IS_INMEMORY(src->flags)) {
531 disp = src->vv.regoff;
533 M_ILD(tempreg, REG_SP, disp + 4);
538 reg = GET_LOW_REG(src->vv.regoff);
543 s4 emit_load_s1_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
544 codegendata *cd = jd->cd;
545 s4 reg = emit_load_s1(jd, iptr, tempreg);
554 s4 emit_load_s2_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
555 codegendata *cd = jd->cd;
556 s4 reg = emit_load_s2(jd, iptr, tempreg);
558 if (IS_FLT_DBL_TYPE(VAROP(iptr->sx.s23.s2)->type)) {
559 M_FMOV(reg, tempreg);
569 s4 emit_load_s1_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
570 codegendata *cd = jd->cd;
571 s4 reg = emit_load_s1(jd, iptr, tempreg);
573 if (IS_FLT_DBL_TYPE(VAROP(iptr->s1)->type)) {
574 M_FMOV(reg, tempreg);
584 s4 emit_load_s2_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
585 codegendata *cd = jd->cd;
586 s4 reg = emit_load_s2(jd, iptr, tempreg);
588 if (IS_FLT_DBL_TYPE(VAROP(iptr->sx.s23.s2)->type)) {
589 M_FMOV(reg, tempreg);
599 s4 emit_alloc_dst_even_odd(jitdata *jd, instruction *iptr, s4 htmpreg, s4 ltmpreg, s4 breg) {
610 * (r12, r13) Illegal, because r13 is PV
611 * (r14, r15) Illegal, because r15 is SP
615 dst = VAROP(iptr->dst);
617 if (IS_INMEMORY(dst->flags)) {
618 if (! IS_REG_ITMP(ltmpreg)) {
619 M_INTMOVE(ltmpreg, breg);
621 if (! IS_REG_ITMP(htmpreg)) {
622 M_INTMOVE(htmpreg, breg);
624 return PACK_REGS(ltmpreg, htmpreg);
626 hr = GET_HIGH_REG(dst->vv.regoff);
627 lr = GET_LOW_REG(dst->vv.regoff);
628 if (((hr % 2) == 0) && lr == (hr + 1)) {
629 /* the result is already in a even-odd pair */
630 return dst->vv.regoff;
631 } else if (((hr % 2) == 0) && (hr < R12)) {
632 /* the high register is at a even position */
633 M_INTMOVE(hr + 1, breg);
634 return PACK_REGS(hr + 1, hr);
635 } else if (((lr % 2) == 1) && (lr < R12)) {
636 /* the low register is at a odd position */
637 M_INTMOVE(lr - 1, breg);
638 return PACK_REGS(lr, lr - 1);
640 /* no way to create an even-odd pair by 1 copy operation,
641 * Use the temporary register pair.
643 if (! IS_REG_ITMP(ltmpreg)) {
644 M_INTMOVE(ltmpreg, breg);
646 if (! IS_REG_ITMP(htmpreg)) {
647 M_INTMOVE(htmpreg, breg);
649 return PACK_REGS(ltmpreg, htmpreg);
654 void emit_restore_dst_even_odd(jitdata *jd, instruction *iptr, s4 htmpreg, s4 ltmpreg, s4 breg) {
660 dst = VAROP(iptr->dst);
662 if (IS_INMEMORY(dst->flags)) {
663 if (! IS_REG_ITMP(ltmpreg)) {
664 M_INTMOVE(breg, ltmpreg);
666 if (! IS_REG_ITMP(htmpreg)) {
667 M_INTMOVE(breg, htmpreg);
670 hr = GET_HIGH_REG(dst->vv.regoff);
671 lr = GET_LOW_REG(dst->vv.regoff);
672 if (((hr % 2) == 0) && lr == (hr + 1)) {
674 } else if (((hr % 2) == 0) && (hr < R12)) {
675 M_INTMOVE(breg, hr + 1);
676 } else if (((lr % 2) == 1) && (lr < R12)) {
677 M_INTMOVE(breg, lr - 1);
679 if (! IS_REG_ITMP(ltmpreg)) {
680 M_INTMOVE(breg, ltmpreg);
682 if (! IS_REG_ITMP(htmpreg)) {
683 M_INTMOVE(breg, htmpreg);
689 void emit_copy_dst(jitdata *jd, instruction *iptr, s4 dtmpreg) {
693 dst = VAROP(iptr->dst);
694 if (! IS_INMEMORY(dst->flags)) {
695 if (dst->vv.regoff != dtmpreg) {
696 if (IS_FLT_DBL_TYPE(dst->type)) {
697 M_FLTMOVE(dtmpreg, dst->vv.regoff);
698 } else if (IS_2_WORD_TYPE(dst->type)) {
699 M_LNGMOVE(dtmpreg, dst->vv.regoff);
701 M_INTMOVE(dtmpreg, dst->vv.regoff);
707 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 opt) {
709 s4 branchdisp = disp;
713 if (N_VALID_BRANCH(branchdisp)) {
715 /* valid displacement */
736 case BRANCH_UNCONDITIONAL:
740 vm_abort("emit_branch: unknown condition %d", condition);
744 /* If LONGBRANCHES is not set, the flag and the error flag */
746 if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
747 cd->flags |= (CODEGENDATA_FLAG_ERROR |
748 CODEGENDATA_FLAG_LONGBRANCHES);
751 /* If error flag is set, do nothing. The method has to be recompiled. */
753 if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd) && CODEGENDATA_HAS_FLAG_ERROR(cd)) {
757 /* Patch the displacement to branch over the actual branch manually
758 * to not get yet more nops.
761 branchmpc = cd->mcodeptr - cd->mcodebase;
783 case BRANCH_UNCONDITIONAL:
784 /* fall through, no displacement to patch */
788 vm_abort("emit_branch: unknown condition %d", condition);
791 /* The actual long branch */
793 disp = dseg_add_s4(cd, branchmpc + disp - N_PV_OFFSET);
794 M_ILD_DSEG(REG_ITMP3, disp);
795 M_AADD(REG_PV, REG_ITMP3);
796 M_JMP(RN, REG_ITMP3);
798 /* Patch back the displacement */
801 *(u4 *)ref |= (u4)((cd->mcodeptr - ref) / 2);
806 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg) {
807 if (INSTRUCTION_MUST_CHECK(iptr)) {
809 M_BNE(SZ_BRC + SZ_ILL);
810 M_ILL(EXCEPTION_HARDWARE_ARITHMETIC);
814 /* emit_arrayindexoutofbounds_check ********************************************
816 Emit a ArrayIndexOutOfBoundsException check.
818 *******************************************************************************/
820 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
822 if (INSTRUCTION_MUST_CHECK(iptr)) {
824 * Do unsigned comparison to catch negative indexes.
826 N_CL(s2, OFFSET(java_arrayheader, size), RN, s1);
827 M_BLT(SZ_BRC + SZ_ILL);
828 M_ILL2(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
832 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1) {
833 if (INSTRUCTION_MUST_CHECK(iptr)) {
839 M_BGT(SZ_BRC + SZ_ILL);
842 M_BNE(SZ_BRC + SZ_ILL);
845 M_BLE(SZ_BRC + SZ_ILL);
848 vm_abort("emit_classcast_check: unknown condition %d", condition);
850 M_ILL2(s1, EXCEPTION_HARDWARE_CLASSCAST);
854 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg) {
855 if (INSTRUCTION_MUST_CHECK(iptr)) {
857 M_BNE(SZ_BRC + SZ_ILL);
858 M_ILL(EXCEPTION_HARDWARE_NULLPOINTER);
862 void emit_exception_check(codegendata *cd, instruction *iptr) {
863 if (INSTRUCTION_MUST_CHECK(iptr)) {
865 M_BNE(SZ_BRC + SZ_ILL);
866 M_ILL(EXCEPTION_HARDWARE_EXCEPTION);
870 void emit_restore_pv(codegendata *cd) {
871 s4 offset, offset_imm;
875 disp = (s4) (cd->mcodeptr - cd->mcodebase);
876 M_ASUB_IMM32(disp, REG_ITMP1, REG_PV);
879 /* If the offset from the method start does not fit into an immediate
880 * value, we can't put it into the data segment!
883 /* Displacement from start of method to here */
885 offset = (s4) (cd->mcodeptr - cd->mcodebase);
886 offset_imm = -offset - SZ_BASR + N_PV_OFFSET;
888 if (N_VALID_IMM(offset_imm)) {
889 /* Get program counter */
891 /* Substract displacement */
892 M_AADD_IMM(offset_imm, REG_PV);
894 /* Save program counter and jump over displacement in instruction flow */
895 N_BRAS(REG_PV, SZ_BRAS + SZ_LONG);
896 /* Place displacement here */
897 /* REG_PV points now exactly to this position */
898 N_LONG(-offset - SZ_BRAS + N_PV_OFFSET);
899 /* Substract *(REG_PV) from REG_PV */
900 N_A(REG_PV, 0, RN, REG_PV);
905 * These are local overrides for various environment variables in Emacs.
906 * Please do not remove this and leave it at the end of the file, where
907 * Emacs will automagically detect them.
908 * ---------------------------------------------------------------------
911 * indent-tabs-mode: t