1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 Contact: cacao@cacaojvm.org
27 Authors: Christian Thalinger
29 $Id: emit.c 7355 2007-02-14 10:57:32Z twisti $
41 #include "vm/jit/s390/codegen.h"
42 #include "vm/jit/s390/emit.h"
44 #if defined(ENABLE_THREADS)
45 # include "threads/native/lock.h"
48 #include "vm/builtin.h"
49 #include "vm/jit/abi-asm.h"
50 #include "vm/jit/asmpart.h"
51 #include "vm/jit/codegen-common.h"
52 #include "vm/jit/emit-common.h"
53 #include "vm/jit/jit.h"
54 #include "vm/jit/replace.h"
58 /* emit_load *******************************************************************
60 Emits a possible load of an operand.
62 *******************************************************************************/
64 __PORTED__ s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
70 /* get required compiler data */
74 if (IS_INMEMORY(src->flags)) {
77 disp = src->vv.regoff * 4;
79 if (IS_FLT_DBL_TYPE(src->type)) {
80 if (IS_2_WORD_TYPE(src->type))
81 M_DLD(tempreg, REG_SP, disp);
83 M_FLD(tempreg, REG_SP, disp);
86 if (IS_2_WORD_TYPE(src->type))
87 M_LLD(tempreg, REG_SP, disp);
89 M_ILD(tempreg, REG_SP, disp);
101 /* emit_store ******************************************************************
103 This function generates the code to store the result of an
104 operation back into a spilled pseudo-variable. If the
105 pseudo-variable has not been spilled in the first place, this
106 function will generate nothing.
108 *******************************************************************************/
110 __PORTED__ inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
114 /* get required compiler data */
118 if (IS_INMEMORY(dst->flags)) {
121 if (IS_FLT_DBL_TYPE(dst->type)) {
122 if (IS_2_WORD_TYPE(dst->type))
123 M_DST(d, REG_SP, dst->vv.regoff * 4);
125 M_FST(d, REG_SP, dst->vv.regoff * 4);
128 if (IS_2_WORD_TYPE(dst->type))
129 M_LST(d, REG_SP, dst->vv.regoff * 4);
131 M_IST(d, REG_SP, dst->vv.regoff * 4);
137 /* emit_copy *******************************************************************
139 Generates a register/memory to register/memory copy.
141 *******************************************************************************/
143 __PORTED__ void emit_copy(jitdata *jd, instruction *iptr, varinfo *src, varinfo *dst)
148 /* get required compiler data */
152 if ((src->vv.regoff != dst->vv.regoff) ||
153 ((src->flags ^ dst->flags) & INMEMORY)) {
155 /* If one of the variables resides in memory, we can eliminate
156 the register move from/to the temporary register with the
157 order of getting the destination register and the load. */
159 if (IS_INMEMORY(src->flags)) {
160 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
161 s1 = emit_load(jd, iptr, src, d);
164 s1 = emit_load(jd, iptr, src, REG_IFTMP);
165 d = codegen_reg_of_var(iptr->opc, dst, s1);
169 if (IS_FLT_DBL_TYPE(src->type))
175 emit_store(jd, iptr, dst, d);
180 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
183 switch (iptr->flags.fields.condition) {
207 /* emit_exception_stubs ********************************************************
209 Generates the code for the exception stubs.
211 *******************************************************************************/
213 void emit_exception_stubs(jitdata *jd)
223 /* get required compiler data */
228 /* generate exception stubs */
232 for (er = cd->exceptionrefs; er != NULL; er = er->next) {
233 /* back-patch the branch to this exception code */
235 branchmpc = er->branchpos;
236 targetmpc = cd->mcodeptr - cd->mcodebase;
238 md_codegen_patch_branch(cd, branchmpc, targetmpc);
242 /* Check if the exception is an
243 ArrayIndexOutOfBoundsException. If so, move index register
247 M_MOV(er->reg, rd->argintregs[4]);
249 /* calcuate exception address */
251 M_MOV_IMM(0, rd->argintregs[3]);
253 M_AADD_IMM32(er->branchpos - 6, rd->argintregs[3]);
255 /* move function to call into REG_ITMP3 */
257 M_MOV_IMM(er->function, REG_ITMP3);
259 if (targetdisp == 0) {
260 targetdisp = cd->mcodeptr - cd->mcodebase;
262 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase), rd->argintregs[0]);
263 M_MOV(REG_SP, rd->argintregs[1]);
264 M_ALD(rd->argintregs[2], REG_SP, cd->stackframesize * 8);
266 M_ASUB_IMM(2 * 8, REG_SP);
267 M_AST(rd->argintregs[3], REG_SP, 0 * 8); /* store XPC */
271 M_ALD(REG_ITMP2_XPC, REG_SP, 0 * 8);
272 M_AADD_IMM(2 * 8, REG_SP);
274 M_MOV_IMM(asm_handle_exception, REG_ITMP3);
278 M_JMP_IMM((cd->mcodebase + targetdisp) -
279 (cd->mcodeptr + PATCHER_CALL_SIZE));
286 /* emit_patcher_stubs **********************************************************
288 Generates the code for the patcher stubs.
290 *******************************************************************************/
292 __PORTED__ void emit_patcher_stubs(jitdata *jd)
303 /* get required compiler data */
307 /* generate code patching stub call code */
311 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
312 /* check code segment size */
316 /* Get machine code which is patched back in later. The
317 call is 1 instruction word long. */
319 tmpmcodeptr = (u1 *) (cd->mcodebase + pref->branchpos);
321 mcode = *((u4 *) tmpmcodeptr);
323 /* Patch in the call to call the following code (done at
326 savedmcodeptr = cd->mcodeptr; /* save current mcodeptr */
327 cd->mcodeptr = tmpmcodeptr; /* set mcodeptr to patch position */
329 disp = (savedmcodeptr) - (tmpmcodeptr);
330 M_BSR(REG_ITMP3, disp);
332 cd->mcodeptr = savedmcodeptr; /* restore the current mcodeptr */
334 /* create stack frame */
336 M_ASUB_IMM(6 * 4, REG_SP);
338 /* move return address onto stack */
340 M_AST(REG_ITMP3, REG_SP, 5 * 4);
342 /* move pointer to java_objectheader onto stack */
344 #if defined(ENABLE_THREADS)
345 /* create a virtual java_objectheader */
347 (void) dseg_add_unique_address(cd, NULL); /* flcword */
348 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
349 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
351 M_LDA(REG_ITMP3, REG_PV, disp);
352 M_AST(REG_ITMP3, REG_SP, 4 * 4);
357 /* move machine code onto stack */
359 disp = dseg_add_s4(cd, mcode);
360 M_ILD(REG_ITMP3, REG_PV, disp);
361 M_IST(REG_ITMP3, REG_SP, 3 * 4);
363 /* move class/method/field reference onto stack */
365 disp = dseg_add_address(cd, pref->ref);
366 M_ALD(REG_ITMP3, REG_PV, disp);
367 M_AST(REG_ITMP3, REG_SP, 2 * 4);
369 /* move data segment displacement onto stack */
371 disp = dseg_add_s4(cd, pref->disp);
372 M_ILD(REG_ITMP3, REG_PV, disp);
373 M_IST(REG_ITMP3, REG_SP, 1 * 4);
375 /* move patcher function pointer onto stack */
377 disp = dseg_add_functionptr(cd, pref->patcher);
378 M_ALD(REG_ITMP3, REG_PV, disp);
379 M_AST(REG_ITMP3, REG_SP, 0 * 4);
381 if (targetdisp == 0) {
382 targetdisp = (cd->mcodeptr) - (cd->mcodebase);
384 disp = dseg_add_functionptr(cd, asm_patcher_wrapper);
385 M_ALD(REG_ITMP3, REG_PV, disp);
386 M_JMP(RN, REG_ITMP3);
389 disp = ((cd->mcodebase) + targetdisp) -
398 /* emit_replacement_stubs ******************************************************
400 Generates the code for the replacement stubs.
402 *******************************************************************************/
404 void emit_replacement_stubs(jitdata *jd)
413 /* get required compiler data */
418 rplp = code->rplpoints;
420 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
421 /* check code segment size */
425 /* note start of stub code */
427 rplp->outcode = (u1 *) (ptrint) (cd->mcodeptr - cd->mcodebase);
429 /* make machine code for patching */
431 disp = (ptrint) (rplp->outcode - rplp->pc) - 5;
433 rplp->mcode = 0xe9 | ((u8) disp << 8);
435 /* push address of `rplpoint` struct */
437 M_MOV_IMM(rplp, REG_ITMP3);
440 /* jump to replacement function */
442 M_MOV_IMM(asm_replacement_out, REG_ITMP3);
449 /* emit_verbosecall_enter ******************************************************
451 Generates the code for the call trace.
453 *******************************************************************************/
456 void emit_verbosecall_enter(jitdata *jd)
464 /* get required compiler data */
472 /* mark trace code */
476 /* additional +1 is for 16-byte stack alignment */
478 M_LSUB_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
480 /* save argument registers */
482 for (i = 0; i < INT_ARG_CNT; i++)
483 M_LST(rd->argintregs[i], REG_SP, (1 + i) * 8);
485 for (i = 0; i < FLT_ARG_CNT; i++)
486 M_DST(rd->argfltregs[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
488 /* save temporary registers for leaf methods */
490 if (jd->isleafmethod) {
491 for (i = 0; i < INT_TMP_CNT; i++)
492 M_LST(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
494 for (i = 0; i < FLT_TMP_CNT; i++)
495 M_DST(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
498 /* show integer hex code for float arguments */
500 for (i = 0, j = 0; i < md->paramcount && i < INT_ARG_CNT; i++) {
501 /* If the paramtype is a float, we have to right shift all
502 following integer registers. */
504 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
505 for (k = INT_ARG_CNT - 2; k >= i; k--)
506 M_MOV(rd->argintregs[k], rd->argintregs[k + 1]);
508 emit_movd_freg_reg(cd, rd->argfltregs[j], rd->argintregs[i]);
513 M_MOV_IMM(m, REG_ITMP2);
514 M_AST(REG_ITMP2, REG_SP, 0 * 8);
515 M_MOV_IMM(builtin_trace_args, REG_ITMP1);
518 /* restore argument registers */
520 for (i = 0; i < INT_ARG_CNT; i++)
521 M_LLD(rd->argintregs[i], REG_SP, (1 + i) * 8);
523 for (i = 0; i < FLT_ARG_CNT; i++)
524 M_DLD(rd->argfltregs[i], REG_SP, (1 + INT_ARG_CNT + i) * 8);
526 /* restore temporary registers for leaf methods */
528 if (jd->isleafmethod) {
529 for (i = 0; i < INT_TMP_CNT; i++)
530 M_LLD(rd->tmpintregs[i], REG_SP, (1 + ARG_CNT + i) * 8);
532 for (i = 0; i < FLT_TMP_CNT; i++)
533 M_DLD(rd->tmpfltregs[i], REG_SP, (1 + ARG_CNT + INT_TMP_CNT + i) * 8);
536 M_LADD_IMM((ARG_CNT + TMP_CNT + 1 + 1) * 8, REG_SP);
538 /* mark trace code */
542 #endif /* !defined(NDEBUG) */
545 /* emit_verbosecall_exit *******************************************************
547 Generates the code for the call trace.
549 *******************************************************************************/
552 void emit_verbosecall_exit(jitdata *jd)
558 /* get required compiler data */
564 /* mark trace code */
568 M_ASUB_IMM(2 * 8, REG_SP);
570 M_LST(REG_RESULT, REG_SP, 0 * 8);
571 M_DST(REG_FRESULT, REG_SP, 1 * 8);
573 M_MOV_IMM(m, rd->argintregs[0]);
574 M_MOV(REG_RESULT, rd->argintregs[1]);
575 M_FLTMOVE(REG_FRESULT, rd->argfltregs[0]);
576 M_FLTMOVE(REG_FRESULT, rd->argfltregs[1]);
578 M_MOV_IMM(builtin_displaymethodstop, REG_ITMP1);
581 M_LLD(REG_RESULT, REG_SP, 0 * 8);
582 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
584 M_AADD_IMM(2 * 8, REG_SP);
586 /* mark trace code */
590 #endif /* !defined(NDEBUG) */
593 /* code generation functions **************************************************/
595 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
597 if ((basereg == REG_SP) || (basereg == R12)) {
599 emit_address_byte(0, dreg, REG_SP);
600 emit_address_byte(0, REG_SP, REG_SP);
602 } else if (IS_IMM8(disp)) {
603 emit_address_byte(1, dreg, REG_SP);
604 emit_address_byte(0, REG_SP, REG_SP);
608 emit_address_byte(2, dreg, REG_SP);
609 emit_address_byte(0, REG_SP, REG_SP);
613 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
614 emit_address_byte(0,(dreg),(basereg));
616 } else if ((basereg) == RIP) {
617 emit_address_byte(0, dreg, RBP);
622 emit_address_byte(1, dreg, basereg);
626 emit_address_byte(2, dreg, basereg);
633 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
635 if ((basereg == REG_SP) || (basereg == R12)) {
636 emit_address_byte(2, dreg, REG_SP);
637 emit_address_byte(0, REG_SP, REG_SP);
641 emit_address_byte(2, dreg, basereg);
647 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
650 emit_address_byte(0, reg, 4);
651 emit_address_byte(scale, indexreg, 5);
654 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
655 emit_address_byte(0, reg, 4);
656 emit_address_byte(scale, indexreg, basereg);
658 else if (IS_IMM8(disp)) {
659 emit_address_byte(1, reg, 4);
660 emit_address_byte(scale, indexreg, basereg);
664 emit_address_byte(2, reg, 4);
665 emit_address_byte(scale, indexreg, basereg);
671 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
674 varinfo *v_s1,*v_s2,*v_dst;
677 /* get required compiler data */
681 v_s1 = VAROP(iptr->s1);
682 v_s2 = VAROP(iptr->sx.s23.s2);
683 v_dst = VAROP(iptr->dst);
685 s1 = v_s1->vv.regoff;
686 s2 = v_s2->vv.regoff;
687 d = v_dst->vv.regoff;
689 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
691 if (IS_INMEMORY(v_dst->flags)) {
692 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
694 M_ILD(RCX, REG_SP, s2 * 8);
695 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
698 M_ILD(RCX, REG_SP, s2 * 8);
699 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
700 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
701 M_IST(REG_ITMP2, REG_SP, d * 8);
704 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
705 /* s1 may be equal to RCX */
708 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
709 M_IST(s1, REG_SP, d * 8);
710 M_INTMOVE(REG_ITMP1, RCX);
713 M_IST(s1, REG_SP, d * 8);
714 M_ILD(RCX, REG_SP, s2 * 8);
718 M_ILD(RCX, REG_SP, s2 * 8);
719 M_IST(s1, REG_SP, d * 8);
722 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
724 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
727 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
731 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
732 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
733 M_IST(REG_ITMP2, REG_SP, d * 8);
737 /* s1 may be equal to RCX */
738 M_IST(s1, REG_SP, d * 8);
740 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
743 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
751 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
752 M_ILD(RCX, REG_SP, s2 * 8);
753 M_ILD(d, REG_SP, s1 * 8);
754 emit_shiftl_reg(cd, shift_op, d);
756 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
757 /* s1 may be equal to RCX */
759 M_ILD(RCX, REG_SP, s2 * 8);
760 emit_shiftl_reg(cd, shift_op, d);
762 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
764 M_ILD(d, REG_SP, s1 * 8);
765 emit_shiftl_reg(cd, shift_op, d);
768 /* s1 may be equal to RCX */
771 /* d cannot be used to backup s1 since this would
773 M_INTMOVE(s1, REG_ITMP3);
775 M_INTMOVE(REG_ITMP3, d);
783 /* d may be equal to s2 */
787 emit_shiftl_reg(cd, shift_op, d);
791 M_INTMOVE(REG_ITMP3, RCX);
793 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
798 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
801 varinfo *v_s1,*v_s2,*v_dst;
804 /* get required compiler data */
808 v_s1 = VAROP(iptr->s1);
809 v_s2 = VAROP(iptr->sx.s23.s2);
810 v_dst = VAROP(iptr->dst);
812 s1 = v_s1->vv.regoff;
813 s2 = v_s2->vv.regoff;
814 d = v_dst->vv.regoff;
816 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
818 if (IS_INMEMORY(v_dst->flags)) {
819 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
821 M_ILD(RCX, REG_SP, s2 * 8);
822 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
825 M_ILD(RCX, REG_SP, s2 * 8);
826 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
827 emit_shift_reg(cd, shift_op, REG_ITMP2);
828 M_LST(REG_ITMP2, REG_SP, d * 8);
831 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
832 /* s1 may be equal to RCX */
835 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
836 M_LST(s1, REG_SP, d * 8);
837 M_INTMOVE(REG_ITMP1, RCX);
840 M_LST(s1, REG_SP, d * 8);
841 M_ILD(RCX, REG_SP, s2 * 8);
845 M_ILD(RCX, REG_SP, s2 * 8);
846 M_LST(s1, REG_SP, d * 8);
849 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
851 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
854 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
858 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
859 emit_shift_reg(cd, shift_op, REG_ITMP2);
860 M_LST(REG_ITMP2, REG_SP, d * 8);
864 /* s1 may be equal to RCX */
865 M_LST(s1, REG_SP, d * 8);
867 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
870 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
878 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
879 M_ILD(RCX, REG_SP, s2 * 8);
880 M_LLD(d, REG_SP, s1 * 8);
881 emit_shift_reg(cd, shift_op, d);
883 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
884 /* s1 may be equal to RCX */
886 M_ILD(RCX, REG_SP, s2 * 8);
887 emit_shift_reg(cd, shift_op, d);
889 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
891 M_LLD(d, REG_SP, s1 * 8);
892 emit_shift_reg(cd, shift_op, d);
895 /* s1 may be equal to RCX */
898 /* d cannot be used to backup s1 since this would
900 M_INTMOVE(s1, REG_ITMP3);
902 M_INTMOVE(REG_ITMP3, d);
910 /* d may be equal to s2 */
914 emit_shift_reg(cd, shift_op, d);
918 M_INTMOVE(REG_ITMP3, RCX);
920 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
925 /* low-level code emitter functions *******************************************/
927 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
929 emit_rex(1,(reg),0,(dreg));
930 *(cd->mcodeptr++) = 0x89;
931 emit_reg((reg),(dreg));
935 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
937 emit_rex(1,0,0,(reg));
938 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
943 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
945 emit_rex(0,(reg),0,(dreg));
946 *(cd->mcodeptr++) = 0x89;
947 emit_reg((reg),(dreg));
951 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
952 emit_rex(0,0,0,(reg));
953 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
958 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
959 emit_rex(1,(reg),0,(basereg));
960 *(cd->mcodeptr++) = 0x8b;
961 emit_membase(cd, (basereg),(disp),(reg));
966 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
967 * constant membase immediate length of 32bit
969 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
970 emit_rex(1,(reg),0,(basereg));
971 *(cd->mcodeptr++) = 0x8b;
972 emit_membase32(cd, (basereg),(disp),(reg));
976 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
978 emit_rex(0,(reg),0,(basereg));
979 *(cd->mcodeptr++) = 0x8b;
980 emit_membase(cd, (basereg),(disp),(reg));
984 /* ATTENTION: Always emit a REX byte, because the instruction size can
985 be smaller when all register indexes are smaller than 7. */
986 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
988 emit_byte_rex((reg),0,(basereg));
989 *(cd->mcodeptr++) = 0x8b;
990 emit_membase32(cd, (basereg),(disp),(reg));
994 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
995 emit_rex(1,(reg),0,(basereg));
996 *(cd->mcodeptr++) = 0x89;
997 emit_membase(cd, (basereg),(disp),(reg));
1001 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1002 emit_rex(1,(reg),0,(basereg));
1003 *(cd->mcodeptr++) = 0x89;
1004 emit_membase32(cd, (basereg),(disp),(reg));
1008 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1009 emit_rex(0,(reg),0,(basereg));
1010 *(cd->mcodeptr++) = 0x89;
1011 emit_membase(cd, (basereg),(disp),(reg));
1015 /* Always emit a REX byte, because the instruction size can be smaller when */
1016 /* all register indexes are smaller than 7. */
1017 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1018 emit_byte_rex((reg),0,(basereg));
1019 *(cd->mcodeptr++) = 0x89;
1020 emit_membase32(cd, (basereg),(disp),(reg));
1024 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1025 emit_rex(1,(reg),(indexreg),(basereg));
1026 *(cd->mcodeptr++) = 0x8b;
1027 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1031 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1032 emit_rex(0,(reg),(indexreg),(basereg));
1033 *(cd->mcodeptr++) = 0x8b;
1034 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1038 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1039 emit_rex(1,(reg),(indexreg),(basereg));
1040 *(cd->mcodeptr++) = 0x89;
1041 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1045 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1046 emit_rex(0,(reg),(indexreg),(basereg));
1047 *(cd->mcodeptr++) = 0x89;
1048 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1052 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1053 *(cd->mcodeptr++) = 0x66;
1054 emit_rex(0,(reg),(indexreg),(basereg));
1055 *(cd->mcodeptr++) = 0x89;
1056 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1060 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1061 emit_byte_rex((reg),(indexreg),(basereg));
1062 *(cd->mcodeptr++) = 0x88;
1063 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1067 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1068 emit_rex(1,0,0,(basereg));
1069 *(cd->mcodeptr++) = 0xc7;
1070 emit_membase(cd, (basereg),(disp),0);
1075 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1076 emit_rex(1,0,0,(basereg));
1077 *(cd->mcodeptr++) = 0xc7;
1078 emit_membase32(cd, (basereg),(disp),0);
1083 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1084 emit_rex(0,0,0,(basereg));
1085 *(cd->mcodeptr++) = 0xc7;
1086 emit_membase(cd, (basereg),(disp),0);
1091 /* Always emit a REX byte, because the instruction size can be smaller when */
1092 /* all register indexes are smaller than 7. */
1093 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1094 emit_byte_rex(0,0,(basereg));
1095 *(cd->mcodeptr++) = 0xc7;
1096 emit_membase32(cd, (basereg),(disp),0);
1101 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1103 emit_rex(1,(dreg),0,(reg));
1104 *(cd->mcodeptr++) = 0x0f;
1105 *(cd->mcodeptr++) = 0xbe;
1106 /* XXX: why do reg and dreg have to be exchanged */
1107 emit_reg((dreg),(reg));
1111 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1113 emit_rex(1,(dreg),0,(reg));
1114 *(cd->mcodeptr++) = 0x0f;
1115 *(cd->mcodeptr++) = 0xbf;
1116 /* XXX: why do reg and dreg have to be exchanged */
1117 emit_reg((dreg),(reg));
1121 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1123 emit_rex(1,(dreg),0,(reg));
1124 *(cd->mcodeptr++) = 0x63;
1125 /* XXX: why do reg and dreg have to be exchanged */
1126 emit_reg((dreg),(reg));
1130 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1132 emit_rex(1,(dreg),0,(reg));
1133 *(cd->mcodeptr++) = 0x0f;
1134 *(cd->mcodeptr++) = 0xb7;
1135 /* XXX: why do reg and dreg have to be exchanged */
1136 emit_reg((dreg),(reg));
1140 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1141 emit_rex(1,(reg),(indexreg),(basereg));
1142 *(cd->mcodeptr++) = 0x0f;
1143 *(cd->mcodeptr++) = 0xbf;
1144 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1148 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1149 emit_rex(1,(reg),(indexreg),(basereg));
1150 *(cd->mcodeptr++) = 0x0f;
1151 *(cd->mcodeptr++) = 0xbe;
1152 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1156 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1157 emit_rex(1,(reg),(indexreg),(basereg));
1158 *(cd->mcodeptr++) = 0x0f;
1159 *(cd->mcodeptr++) = 0xb7;
1160 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1164 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1166 emit_rex(1,0,(indexreg),(basereg));
1167 *(cd->mcodeptr++) = 0xc7;
1168 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1173 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1175 emit_rex(0,0,(indexreg),(basereg));
1176 *(cd->mcodeptr++) = 0xc7;
1177 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1182 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1184 *(cd->mcodeptr++) = 0x66;
1185 emit_rex(0,0,(indexreg),(basereg));
1186 *(cd->mcodeptr++) = 0xc7;
1187 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1192 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1194 emit_rex(0,0,(indexreg),(basereg));
1195 *(cd->mcodeptr++) = 0xc6;
1196 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1204 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1206 emit_rex(1,(reg),0,(dreg));
1207 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1208 emit_reg((reg),(dreg));
1212 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1214 emit_rex(0,(reg),0,(dreg));
1215 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1216 emit_reg((reg),(dreg));
1220 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1222 emit_rex(1,(reg),0,(basereg));
1223 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1224 emit_membase(cd, (basereg),(disp),(reg));
1228 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1230 emit_rex(0,(reg),0,(basereg));
1231 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1232 emit_membase(cd, (basereg),(disp),(reg));
1236 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1238 emit_rex(1,(reg),0,(basereg));
1239 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1240 emit_membase(cd, (basereg),(disp),(reg));
1244 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1246 emit_rex(0,(reg),0,(basereg));
1247 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1248 emit_membase(cd, (basereg),(disp),(reg));
1252 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1254 emit_rex(1,0,0,(dreg));
1255 *(cd->mcodeptr++) = 0x83;
1256 emit_reg((opc),(dreg));
1259 emit_rex(1,0,0,(dreg));
1260 *(cd->mcodeptr++) = 0x81;
1261 emit_reg((opc),(dreg));
1267 void emit_alu_imm32_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1268 emit_rex(1,0,0,(dreg));
1269 *(cd->mcodeptr++) = 0x81;
1270 emit_reg((opc),(dreg));
1275 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1277 emit_rex(0,0,0,(dreg));
1278 *(cd->mcodeptr++) = 0x83;
1279 emit_reg((opc),(dreg));
1282 emit_rex(0,0,0,(dreg));
1283 *(cd->mcodeptr++) = 0x81;
1284 emit_reg((opc),(dreg));
1290 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1292 emit_rex(1,(basereg),0,0);
1293 *(cd->mcodeptr++) = 0x83;
1294 emit_membase(cd, (basereg),(disp),(opc));
1297 emit_rex(1,(basereg),0,0);
1298 *(cd->mcodeptr++) = 0x81;
1299 emit_membase(cd, (basereg),(disp),(opc));
1305 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1307 emit_rex(0,(basereg),0,0);
1308 *(cd->mcodeptr++) = 0x83;
1309 emit_membase(cd, (basereg),(disp),(opc));
1312 emit_rex(0,(basereg),0,0);
1313 *(cd->mcodeptr++) = 0x81;
1314 emit_membase(cd, (basereg),(disp),(opc));
1320 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1321 emit_rex(1,(reg),0,(dreg));
1322 *(cd->mcodeptr++) = 0x85;
1323 emit_reg((reg),(dreg));
1327 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1328 emit_rex(0,(reg),0,(dreg));
1329 *(cd->mcodeptr++) = 0x85;
1330 emit_reg((reg),(dreg));
1334 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1335 *(cd->mcodeptr++) = 0xf7;
1341 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1342 *(cd->mcodeptr++) = 0x66;
1343 *(cd->mcodeptr++) = 0xf7;
1349 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1350 *(cd->mcodeptr++) = 0xf6;
1356 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1357 emit_rex(1,(reg),0,(basereg));
1358 *(cd->mcodeptr++) = 0x8d;
1359 emit_membase(cd, (basereg),(disp),(reg));
1363 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1364 emit_rex(0,(reg),0,(basereg));
1365 *(cd->mcodeptr++) = 0x8d;
1366 emit_membase(cd, (basereg),(disp),(reg));
1371 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1373 emit_rex(0,0,0,(basereg));
1374 *(cd->mcodeptr++) = 0xff;
1375 emit_membase(cd, (basereg),(disp),0);
1380 void emit_cltd(codegendata *cd) {
1381 *(cd->mcodeptr++) = 0x99;
1385 void emit_cqto(codegendata *cd) {
1387 *(cd->mcodeptr++) = 0x99;
1392 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1393 emit_rex(1,(dreg),0,(reg));
1394 *(cd->mcodeptr++) = 0x0f;
1395 *(cd->mcodeptr++) = 0xaf;
1396 emit_reg((dreg),(reg));
1400 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1401 emit_rex(0,(dreg),0,(reg));
1402 *(cd->mcodeptr++) = 0x0f;
1403 *(cd->mcodeptr++) = 0xaf;
1404 emit_reg((dreg),(reg));
1408 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1409 emit_rex(1,(dreg),0,(basereg));
1410 *(cd->mcodeptr++) = 0x0f;
1411 *(cd->mcodeptr++) = 0xaf;
1412 emit_membase(cd, (basereg),(disp),(dreg));
1416 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1417 emit_rex(0,(dreg),0,(basereg));
1418 *(cd->mcodeptr++) = 0x0f;
1419 *(cd->mcodeptr++) = 0xaf;
1420 emit_membase(cd, (basereg),(disp),(dreg));
1424 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1425 if (IS_IMM8((imm))) {
1426 emit_rex(1,0,0,(dreg));
1427 *(cd->mcodeptr++) = 0x6b;
1431 emit_rex(1,0,0,(dreg));
1432 *(cd->mcodeptr++) = 0x69;
1439 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1440 if (IS_IMM8((imm))) {
1441 emit_rex(1,(dreg),0,(reg));
1442 *(cd->mcodeptr++) = 0x6b;
1443 emit_reg((dreg),(reg));
1446 emit_rex(1,(dreg),0,(reg));
1447 *(cd->mcodeptr++) = 0x69;
1448 emit_reg((dreg),(reg));
1454 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1455 if (IS_IMM8((imm))) {
1456 emit_rex(0,(dreg),0,(reg));
1457 *(cd->mcodeptr++) = 0x6b;
1458 emit_reg((dreg),(reg));
1461 emit_rex(0,(dreg),0,(reg));
1462 *(cd->mcodeptr++) = 0x69;
1463 emit_reg((dreg),(reg));
1469 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1470 if (IS_IMM8((imm))) {
1471 emit_rex(1,(dreg),0,(basereg));
1472 *(cd->mcodeptr++) = 0x6b;
1473 emit_membase(cd, (basereg),(disp),(dreg));
1476 emit_rex(1,(dreg),0,(basereg));
1477 *(cd->mcodeptr++) = 0x69;
1478 emit_membase(cd, (basereg),(disp),(dreg));
1484 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1485 if (IS_IMM8((imm))) {
1486 emit_rex(0,(dreg),0,(basereg));
1487 *(cd->mcodeptr++) = 0x6b;
1488 emit_membase(cd, (basereg),(disp),(dreg));
1491 emit_rex(0,(dreg),0,(basereg));
1492 *(cd->mcodeptr++) = 0x69;
1493 emit_membase(cd, (basereg),(disp),(dreg));
1499 void emit_idiv_reg(codegendata *cd, s8 reg) {
1500 emit_rex(1,0,0,(reg));
1501 *(cd->mcodeptr++) = 0xf7;
1506 void emit_idivl_reg(codegendata *cd, s8 reg) {
1507 emit_rex(0,0,0,(reg));
1508 *(cd->mcodeptr++) = 0xf7;
1514 void emit_ret(codegendata *cd) {
1515 *(cd->mcodeptr++) = 0xc3;
1523 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1524 emit_rex(1,0,0,(reg));
1525 *(cd->mcodeptr++) = 0xd3;
1526 emit_reg((opc),(reg));
1530 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1531 emit_rex(0,0,0,(reg));
1532 *(cd->mcodeptr++) = 0xd3;
1533 emit_reg((opc),(reg));
1537 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1538 emit_rex(1,0,0,(basereg));
1539 *(cd->mcodeptr++) = 0xd3;
1540 emit_membase(cd, (basereg),(disp),(opc));
1544 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1545 emit_rex(0,0,0,(basereg));
1546 *(cd->mcodeptr++) = 0xd3;
1547 emit_membase(cd, (basereg),(disp),(opc));
1551 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1553 emit_rex(1,0,0,(dreg));
1554 *(cd->mcodeptr++) = 0xd1;
1555 emit_reg((opc),(dreg));
1557 emit_rex(1,0,0,(dreg));
1558 *(cd->mcodeptr++) = 0xc1;
1559 emit_reg((opc),(dreg));
1565 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1567 emit_rex(0,0,0,(dreg));
1568 *(cd->mcodeptr++) = 0xd1;
1569 emit_reg((opc),(dreg));
1571 emit_rex(0,0,0,(dreg));
1572 *(cd->mcodeptr++) = 0xc1;
1573 emit_reg((opc),(dreg));
1579 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1581 emit_rex(1,0,0,(basereg));
1582 *(cd->mcodeptr++) = 0xd1;
1583 emit_membase(cd, (basereg),(disp),(opc));
1585 emit_rex(1,0,0,(basereg));
1586 *(cd->mcodeptr++) = 0xc1;
1587 emit_membase(cd, (basereg),(disp),(opc));
1593 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1595 emit_rex(0,0,0,(basereg));
1596 *(cd->mcodeptr++) = 0xd1;
1597 emit_membase(cd, (basereg),(disp),(opc));
1599 emit_rex(0,0,0,(basereg));
1600 *(cd->mcodeptr++) = 0xc1;
1601 emit_membase(cd, (basereg),(disp),(opc));
1611 void emit_jmp_imm(codegendata *cd, s8 imm) {
1612 *(cd->mcodeptr++) = 0xe9;
1617 void emit_jmp_reg(codegendata *cd, s8 reg) {
1618 emit_rex(0,0,0,(reg));
1619 *(cd->mcodeptr++) = 0xff;
1624 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1625 *(cd->mcodeptr++) = 0x0f;
1626 *(cd->mcodeptr++) = (0x80 + (opc));
1633 * conditional set and move operations
1636 /* we need the rex byte to get all low bytes */
1637 void emit_setcc_reg(codegendata *cd, s8 opc, s8 reg) {
1638 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1639 *(cd->mcodeptr++) = 0x0f;
1640 *(cd->mcodeptr++) = (0x90 + (opc));
1645 /* we need the rex byte to get all low bytes */
1646 void emit_setcc_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1647 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1648 *(cd->mcodeptr++) = 0x0f;
1649 *(cd->mcodeptr++) = (0x90 + (opc));
1650 emit_membase(cd, (basereg),(disp),0);
1654 void emit_cmovcc_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1656 emit_rex(1,(dreg),0,(reg));
1657 *(cd->mcodeptr++) = 0x0f;
1658 *(cd->mcodeptr++) = (0x40 + (opc));
1659 emit_reg((dreg),(reg));
1663 void emit_cmovccl_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1665 emit_rex(0,(dreg),0,(reg));
1666 *(cd->mcodeptr++) = 0x0f;
1667 *(cd->mcodeptr++) = (0x40 + (opc));
1668 emit_reg((dreg),(reg));
1673 void emit_neg_reg(codegendata *cd, s8 reg)
1675 emit_rex(1,0,0,(reg));
1676 *(cd->mcodeptr++) = 0xf7;
1681 void emit_negl_reg(codegendata *cd, s8 reg)
1683 emit_rex(0,0,0,(reg));
1684 *(cd->mcodeptr++) = 0xf7;
1689 void emit_push_reg(codegendata *cd, s8 reg) {
1690 emit_rex(0,0,0,(reg));
1691 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1695 void emit_push_imm(codegendata *cd, s8 imm) {
1696 *(cd->mcodeptr++) = 0x68;
1701 void emit_pop_reg(codegendata *cd, s8 reg) {
1702 emit_rex(0,0,0,(reg));
1703 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1707 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1708 emit_rex(1,(reg),0,(dreg));
1709 *(cd->mcodeptr++) = 0x87;
1710 emit_reg((reg),(dreg));
1714 void emit_nop(codegendata *cd) {
1715 *(cd->mcodeptr++) = 0x90;
1723 void emit_call_reg(codegendata *cd, s8 reg) {
1724 emit_rex(1,0,0,(reg));
1725 *(cd->mcodeptr++) = 0xff;
1730 void emit_call_imm(codegendata *cd, s8 imm) {
1731 *(cd->mcodeptr++) = 0xe8;
1736 void emit_call_mem(codegendata *cd, ptrint mem)
1738 *(cd->mcodeptr++) = 0xff;
1745 * floating point instructions (SSE2)
1747 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1748 *(cd->mcodeptr++) = 0xf2;
1749 emit_rex(0,(dreg),0,(reg));
1750 *(cd->mcodeptr++) = 0x0f;
1751 *(cd->mcodeptr++) = 0x58;
1752 emit_reg((dreg),(reg));
1756 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1757 *(cd->mcodeptr++) = 0xf3;
1758 emit_rex(0,(dreg),0,(reg));
1759 *(cd->mcodeptr++) = 0x0f;
1760 *(cd->mcodeptr++) = 0x58;
1761 emit_reg((dreg),(reg));
1765 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1766 *(cd->mcodeptr++) = 0xf3;
1767 emit_rex(1,(dreg),0,(reg));
1768 *(cd->mcodeptr++) = 0x0f;
1769 *(cd->mcodeptr++) = 0x2a;
1770 emit_reg((dreg),(reg));
1774 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1775 *(cd->mcodeptr++) = 0xf3;
1776 emit_rex(0,(dreg),0,(reg));
1777 *(cd->mcodeptr++) = 0x0f;
1778 *(cd->mcodeptr++) = 0x2a;
1779 emit_reg((dreg),(reg));
1783 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1784 *(cd->mcodeptr++) = 0xf2;
1785 emit_rex(1,(dreg),0,(reg));
1786 *(cd->mcodeptr++) = 0x0f;
1787 *(cd->mcodeptr++) = 0x2a;
1788 emit_reg((dreg),(reg));
1792 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1793 *(cd->mcodeptr++) = 0xf2;
1794 emit_rex(0,(dreg),0,(reg));
1795 *(cd->mcodeptr++) = 0x0f;
1796 *(cd->mcodeptr++) = 0x2a;
1797 emit_reg((dreg),(reg));
1801 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1802 *(cd->mcodeptr++) = 0xf3;
1803 emit_rex(0,(dreg),0,(reg));
1804 *(cd->mcodeptr++) = 0x0f;
1805 *(cd->mcodeptr++) = 0x5a;
1806 emit_reg((dreg),(reg));
1810 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1811 *(cd->mcodeptr++) = 0xf2;
1812 emit_rex(0,(dreg),0,(reg));
1813 *(cd->mcodeptr++) = 0x0f;
1814 *(cd->mcodeptr++) = 0x5a;
1815 emit_reg((dreg),(reg));
1819 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1820 *(cd->mcodeptr++) = 0xf3;
1821 emit_rex(1,(dreg),0,(reg));
1822 *(cd->mcodeptr++) = 0x0f;
1823 *(cd->mcodeptr++) = 0x2c;
1824 emit_reg((dreg),(reg));
1828 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1829 *(cd->mcodeptr++) = 0xf3;
1830 emit_rex(0,(dreg),0,(reg));
1831 *(cd->mcodeptr++) = 0x0f;
1832 *(cd->mcodeptr++) = 0x2c;
1833 emit_reg((dreg),(reg));
1837 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1838 *(cd->mcodeptr++) = 0xf2;
1839 emit_rex(1,(dreg),0,(reg));
1840 *(cd->mcodeptr++) = 0x0f;
1841 *(cd->mcodeptr++) = 0x2c;
1842 emit_reg((dreg),(reg));
1846 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1847 *(cd->mcodeptr++) = 0xf2;
1848 emit_rex(0,(dreg),0,(reg));
1849 *(cd->mcodeptr++) = 0x0f;
1850 *(cd->mcodeptr++) = 0x2c;
1851 emit_reg((dreg),(reg));
1855 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1856 *(cd->mcodeptr++) = 0xf3;
1857 emit_rex(0,(dreg),0,(reg));
1858 *(cd->mcodeptr++) = 0x0f;
1859 *(cd->mcodeptr++) = 0x5e;
1860 emit_reg((dreg),(reg));
1864 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1865 *(cd->mcodeptr++) = 0xf2;
1866 emit_rex(0,(dreg),0,(reg));
1867 *(cd->mcodeptr++) = 0x0f;
1868 *(cd->mcodeptr++) = 0x5e;
1869 emit_reg((dreg),(reg));
1873 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1874 *(cd->mcodeptr++) = 0x66;
1875 emit_rex(1,(freg),0,(reg));
1876 *(cd->mcodeptr++) = 0x0f;
1877 *(cd->mcodeptr++) = 0x6e;
1878 emit_reg((freg),(reg));
1882 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1883 *(cd->mcodeptr++) = 0x66;
1884 emit_rex(1,(freg),0,(reg));
1885 *(cd->mcodeptr++) = 0x0f;
1886 *(cd->mcodeptr++) = 0x7e;
1887 emit_reg((freg),(reg));
1891 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1892 *(cd->mcodeptr++) = 0x66;
1893 emit_rex(0,(reg),0,(basereg));
1894 *(cd->mcodeptr++) = 0x0f;
1895 *(cd->mcodeptr++) = 0x7e;
1896 emit_membase(cd, (basereg),(disp),(reg));
1900 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1901 *(cd->mcodeptr++) = 0x66;
1902 emit_rex(0,(reg),(indexreg),(basereg));
1903 *(cd->mcodeptr++) = 0x0f;
1904 *(cd->mcodeptr++) = 0x7e;
1905 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1909 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1910 *(cd->mcodeptr++) = 0x66;
1911 emit_rex(1,(dreg),0,(basereg));
1912 *(cd->mcodeptr++) = 0x0f;
1913 *(cd->mcodeptr++) = 0x6e;
1914 emit_membase(cd, (basereg),(disp),(dreg));
1918 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1919 *(cd->mcodeptr++) = 0x66;
1920 emit_rex(0,(dreg),0,(basereg));
1921 *(cd->mcodeptr++) = 0x0f;
1922 *(cd->mcodeptr++) = 0x6e;
1923 emit_membase(cd, (basereg),(disp),(dreg));
1927 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
1928 *(cd->mcodeptr++) = 0x66;
1929 emit_rex(0,(dreg),(indexreg),(basereg));
1930 *(cd->mcodeptr++) = 0x0f;
1931 *(cd->mcodeptr++) = 0x6e;
1932 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
1936 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1937 *(cd->mcodeptr++) = 0xf3;
1938 emit_rex(0,(dreg),0,(reg));
1939 *(cd->mcodeptr++) = 0x0f;
1940 *(cd->mcodeptr++) = 0x7e;
1941 emit_reg((dreg),(reg));
1945 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1946 *(cd->mcodeptr++) = 0x66;
1947 emit_rex(0,(reg),0,(basereg));
1948 *(cd->mcodeptr++) = 0x0f;
1949 *(cd->mcodeptr++) = 0xd6;
1950 emit_membase(cd, (basereg),(disp),(reg));
1954 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1955 *(cd->mcodeptr++) = 0xf3;
1956 emit_rex(0,(dreg),0,(basereg));
1957 *(cd->mcodeptr++) = 0x0f;
1958 *(cd->mcodeptr++) = 0x7e;
1959 emit_membase(cd, (basereg),(disp),(dreg));
1963 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1964 *(cd->mcodeptr++) = 0xf3;
1965 emit_rex(0,(reg),0,(dreg));
1966 *(cd->mcodeptr++) = 0x0f;
1967 *(cd->mcodeptr++) = 0x10;
1968 emit_reg((reg),(dreg));
1972 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1973 *(cd->mcodeptr++) = 0xf2;
1974 emit_rex(0,(reg),0,(dreg));
1975 *(cd->mcodeptr++) = 0x0f;
1976 *(cd->mcodeptr++) = 0x10;
1977 emit_reg((reg),(dreg));
1981 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1982 *(cd->mcodeptr++) = 0xf3;
1983 emit_rex(0,(reg),0,(basereg));
1984 *(cd->mcodeptr++) = 0x0f;
1985 *(cd->mcodeptr++) = 0x11;
1986 emit_membase(cd, (basereg),(disp),(reg));
1990 /* Always emit a REX byte, because the instruction size can be smaller when */
1991 /* all register indexes are smaller than 7. */
1992 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1993 *(cd->mcodeptr++) = 0xf3;
1994 emit_byte_rex((reg),0,(basereg));
1995 *(cd->mcodeptr++) = 0x0f;
1996 *(cd->mcodeptr++) = 0x11;
1997 emit_membase32(cd, (basereg),(disp),(reg));
2001 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2002 *(cd->mcodeptr++) = 0xf2;
2003 emit_rex(0,(reg),0,(basereg));
2004 *(cd->mcodeptr++) = 0x0f;
2005 *(cd->mcodeptr++) = 0x11;
2006 emit_membase(cd, (basereg),(disp),(reg));
2010 /* Always emit a REX byte, because the instruction size can be smaller when */
2011 /* all register indexes are smaller than 7. */
2012 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2013 *(cd->mcodeptr++) = 0xf2;
2014 emit_byte_rex((reg),0,(basereg));
2015 *(cd->mcodeptr++) = 0x0f;
2016 *(cd->mcodeptr++) = 0x11;
2017 emit_membase32(cd, (basereg),(disp),(reg));
2021 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2022 *(cd->mcodeptr++) = 0xf3;
2023 emit_rex(0,(dreg),0,(basereg));
2024 *(cd->mcodeptr++) = 0x0f;
2025 *(cd->mcodeptr++) = 0x10;
2026 emit_membase(cd, (basereg),(disp),(dreg));
2030 /* Always emit a REX byte, because the instruction size can be smaller when */
2031 /* all register indexes are smaller than 7. */
2032 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2033 *(cd->mcodeptr++) = 0xf3;
2034 emit_byte_rex((dreg),0,(basereg));
2035 *(cd->mcodeptr++) = 0x0f;
2036 *(cd->mcodeptr++) = 0x10;
2037 emit_membase32(cd, (basereg),(disp),(dreg));
2041 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2043 emit_rex(0,(dreg),0,(basereg));
2044 *(cd->mcodeptr++) = 0x0f;
2045 *(cd->mcodeptr++) = 0x12;
2046 emit_membase(cd, (basereg),(disp),(dreg));
2050 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2052 emit_rex(0,(reg),0,(basereg));
2053 *(cd->mcodeptr++) = 0x0f;
2054 *(cd->mcodeptr++) = 0x13;
2055 emit_membase(cd, (basereg),(disp),(reg));
2059 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2060 *(cd->mcodeptr++) = 0xf2;
2061 emit_rex(0,(dreg),0,(basereg));
2062 *(cd->mcodeptr++) = 0x0f;
2063 *(cd->mcodeptr++) = 0x10;
2064 emit_membase(cd, (basereg),(disp),(dreg));
2068 /* Always emit a REX byte, because the instruction size can be smaller when */
2069 /* all register indexes are smaller than 7. */
2070 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2071 *(cd->mcodeptr++) = 0xf2;
2072 emit_byte_rex((dreg),0,(basereg));
2073 *(cd->mcodeptr++) = 0x0f;
2074 *(cd->mcodeptr++) = 0x10;
2075 emit_membase32(cd, (basereg),(disp),(dreg));
2079 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2081 *(cd->mcodeptr++) = 0x66;
2082 emit_rex(0,(dreg),0,(basereg));
2083 *(cd->mcodeptr++) = 0x0f;
2084 *(cd->mcodeptr++) = 0x12;
2085 emit_membase(cd, (basereg),(disp),(dreg));
2089 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2091 *(cd->mcodeptr++) = 0x66;
2092 emit_rex(0,(reg),0,(basereg));
2093 *(cd->mcodeptr++) = 0x0f;
2094 *(cd->mcodeptr++) = 0x13;
2095 emit_membase(cd, (basereg),(disp),(reg));
2099 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2100 *(cd->mcodeptr++) = 0xf3;
2101 emit_rex(0,(reg),(indexreg),(basereg));
2102 *(cd->mcodeptr++) = 0x0f;
2103 *(cd->mcodeptr++) = 0x11;
2104 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2108 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2109 *(cd->mcodeptr++) = 0xf2;
2110 emit_rex(0,(reg),(indexreg),(basereg));
2111 *(cd->mcodeptr++) = 0x0f;
2112 *(cd->mcodeptr++) = 0x11;
2113 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2117 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2118 *(cd->mcodeptr++) = 0xf3;
2119 emit_rex(0,(dreg),(indexreg),(basereg));
2120 *(cd->mcodeptr++) = 0x0f;
2121 *(cd->mcodeptr++) = 0x10;
2122 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2126 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2127 *(cd->mcodeptr++) = 0xf2;
2128 emit_rex(0,(dreg),(indexreg),(basereg));
2129 *(cd->mcodeptr++) = 0x0f;
2130 *(cd->mcodeptr++) = 0x10;
2131 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2135 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2136 *(cd->mcodeptr++) = 0xf3;
2137 emit_rex(0,(dreg),0,(reg));
2138 *(cd->mcodeptr++) = 0x0f;
2139 *(cd->mcodeptr++) = 0x59;
2140 emit_reg((dreg),(reg));
2144 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2145 *(cd->mcodeptr++) = 0xf2;
2146 emit_rex(0,(dreg),0,(reg));
2147 *(cd->mcodeptr++) = 0x0f;
2148 *(cd->mcodeptr++) = 0x59;
2149 emit_reg((dreg),(reg));
2153 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2154 *(cd->mcodeptr++) = 0xf3;
2155 emit_rex(0,(dreg),0,(reg));
2156 *(cd->mcodeptr++) = 0x0f;
2157 *(cd->mcodeptr++) = 0x5c;
2158 emit_reg((dreg),(reg));
2162 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2163 *(cd->mcodeptr++) = 0xf2;
2164 emit_rex(0,(dreg),0,(reg));
2165 *(cd->mcodeptr++) = 0x0f;
2166 *(cd->mcodeptr++) = 0x5c;
2167 emit_reg((dreg),(reg));
2171 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2172 emit_rex(0,(dreg),0,(reg));
2173 *(cd->mcodeptr++) = 0x0f;
2174 *(cd->mcodeptr++) = 0x2e;
2175 emit_reg((dreg),(reg));
2179 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2180 *(cd->mcodeptr++) = 0x66;
2181 emit_rex(0,(dreg),0,(reg));
2182 *(cd->mcodeptr++) = 0x0f;
2183 *(cd->mcodeptr++) = 0x2e;
2184 emit_reg((dreg),(reg));
2188 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2189 emit_rex(0,(dreg),0,(reg));
2190 *(cd->mcodeptr++) = 0x0f;
2191 *(cd->mcodeptr++) = 0x57;
2192 emit_reg((dreg),(reg));
2196 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2197 emit_rex(0,(dreg),0,(basereg));
2198 *(cd->mcodeptr++) = 0x0f;
2199 *(cd->mcodeptr++) = 0x57;
2200 emit_membase(cd, (basereg),(disp),(dreg));
2204 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2205 *(cd->mcodeptr++) = 0x66;
2206 emit_rex(0,(dreg),0,(reg));
2207 *(cd->mcodeptr++) = 0x0f;
2208 *(cd->mcodeptr++) = 0x57;
2209 emit_reg((dreg),(reg));
2213 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2214 *(cd->mcodeptr++) = 0x66;
2215 emit_rex(0,(dreg),0,(basereg));
2216 *(cd->mcodeptr++) = 0x0f;
2217 *(cd->mcodeptr++) = 0x57;
2218 emit_membase(cd, (basereg),(disp),(dreg));
2222 /* system instructions ********************************************************/
2224 void emit_rdtsc(codegendata *cd)
2226 *(cd->mcodeptr++) = 0x0f;
2227 *(cd->mcodeptr++) = 0x31;
2230 /* emit_load_high **************************************************************
2232 Emits a possible load of the high 32-bits of an operand.
2234 *******************************************************************************/
2236 s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
2242 assert(src->type == TYPE_LNG);
2244 /* get required compiler data */
2248 if (IS_INMEMORY(src->flags)) {
2251 disp = src->vv.regoff * 4;
2253 M_ILD(tempreg, REG_SP, disp);
2258 reg = GET_HIGH_REG(src->vv.regoff);
2263 /* emit_load_low ***************************************************************
2265 Emits a possible load of the low 32-bits of an operand.
2267 *******************************************************************************/
2269 s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
2275 assert(src->type == TYPE_LNG);
2277 /* get required compiler data */
2281 if (IS_INMEMORY(src->flags)) {
2284 disp = src->vv.regoff * 4;
2286 M_ILD(tempreg, REG_SP, disp + 4);
2291 reg = GET_LOW_REG(src->vv.regoff);
2296 /* emit_nullpointer_check ******************************************************
2298 Emit a NullPointerException check.
2300 *******************************************************************************/
2302 __PORTED__ void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
2304 if (INSTRUCTION_MUST_CHECK(iptr)) {
2307 codegen_add_nullpointerexception_ref(cd);
2311 /* emit_arrayindexoutofbounds_check ********************************************
2313 Emit a ArrayIndexOutOfBoundsException check.
2315 *******************************************************************************/
2317 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
2320 if (INSTRUCTION_MUST_CHECK(iptr)) {
2321 M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));
2322 M_ICMP(REG_ITMP3, s2);
2324 codegen_add_arrayindexoutofboundsexception_ref(cd, s2);
2331 * These are local overrides for various environment variables in Emacs.
2332 * Please do not remove this and leave it at the end of the file, where
2333 * Emacs will automagically detect them.
2334 * ---------------------------------------------------------------------
2337 * indent-tabs-mode: t