1 /* src/vm/jit/x86_64/emit.c - x86_64 code emitter functions
3 Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 Contact: cacao@cacaojvm.org
27 Authors: Christian Thalinger
29 $Id: emit.c 7453 2007-03-05 08:38:29Z pm $
41 #include "vm/jit/s390/codegen.h"
42 #include "vm/jit/s390/emit.h"
44 #if defined(ENABLE_THREADS)
45 # include "threads/native/lock.h"
48 #include "vm/builtin.h"
49 #include "vm/jit/abi-asm.h"
50 #include "vm/jit/asmpart.h"
51 #include "vm/jit/codegen-common.h"
52 #include "vm/jit/emit-common.h"
53 #include "vm/jit/jit.h"
54 #include "vm/jit/replace.h"
55 #include "vm/global.h"
56 #include "mm/memory.h"
60 /* emit_load *******************************************************************
62 Emits a possible load of an operand.
64 *******************************************************************************/
66 __PORTED__ s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
72 /* get required compiler data */
76 if (IS_INMEMORY(src->flags)) {
79 disp = src->vv.regoff * 4;
81 if (IS_FLT_DBL_TYPE(src->type)) {
82 if (IS_2_WORD_TYPE(src->type))
83 M_DLD(tempreg, REG_SP, disp);
85 M_FLD(tempreg, REG_SP, disp);
88 if (IS_2_WORD_TYPE(src->type))
89 M_LLD(tempreg, REG_SP, disp);
91 M_ILD(tempreg, REG_SP, disp);
103 /* emit_store ******************************************************************
105 This function generates the code to store the result of an
106 operation back into a spilled pseudo-variable. If the
107 pseudo-variable has not been spilled in the first place, this
108 function will generate nothing.
110 *******************************************************************************/
112 __PORTED__ inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
116 /* get required compiler data */
120 if (IS_INMEMORY(dst->flags)) {
123 if (IS_FLT_DBL_TYPE(dst->type)) {
124 if (IS_2_WORD_TYPE(dst->type))
125 M_DST(d, REG_SP, dst->vv.regoff * 4);
127 M_FST(d, REG_SP, dst->vv.regoff * 4);
130 if (IS_2_WORD_TYPE(dst->type))
131 M_LST(d, REG_SP, dst->vv.regoff * 4);
133 M_IST(d, REG_SP, dst->vv.regoff * 4);
139 /* emit_copy *******************************************************************
141 Generates a register/memory to register/memory copy.
143 *******************************************************************************/
145 __PORTED__ void emit_copy(jitdata *jd, instruction *iptr, varinfo *src, varinfo *dst)
150 /* get required compiler data */
154 if ((src->vv.regoff != dst->vv.regoff) ||
155 ((src->flags ^ dst->flags) & INMEMORY)) {
157 /* If one of the variables resides in memory, we can eliminate
158 the register move from/to the temporary register with the
159 order of getting the destination register and the load. */
161 if (IS_INMEMORY(src->flags)) {
162 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
163 s1 = emit_load(jd, iptr, src, d);
166 s1 = emit_load(jd, iptr, src, REG_IFTMP);
167 d = codegen_reg_of_var(iptr->opc, dst, s1);
171 if (IS_FLT_DBL_TYPE(src->type))
177 emit_store(jd, iptr, dst, d);
182 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
185 switch (iptr->flags.fields.condition) {
209 /* emit_exception_stubs ********************************************************
211 Generates the code for the exception stubs.
213 *******************************************************************************/
215 void emit_exception_stubs(jitdata *jd)
225 /* get required compiler data */
230 /* generate exception stubs */
234 for (er = cd->exceptionrefs; er != NULL; er = er->next) {
235 /* back-patch the branch to this exception code */
237 branchmpc = er->branchpos;
238 targetmpc = cd->mcodeptr - cd->mcodebase;
240 md_codegen_patch_branch(cd, branchmpc, targetmpc);
244 /* Check if the exception is an
245 ArrayIndexOutOfBoundsException. If so, move index register
249 M_MOV(er->reg, rd->argintregs[4]);
251 /* calcuate exception address */
253 M_MOV_IMM(0, rd->argintregs[3]);
255 M_AADD_IMM32(er->branchpos - 6, rd->argintregs[3]);
257 /* move function to call into REG_ITMP3 */
259 M_MOV_IMM(er->function, REG_ITMP3);
261 if (targetdisp == 0) {
262 targetdisp = cd->mcodeptr - cd->mcodebase;
264 emit_lea_membase_reg(cd, RIP, -((cd->mcodeptr + 7) - cd->mcodebase), rd->argintregs[0]);
265 M_MOV(REG_SP, rd->argintregs[1]);
266 M_ALD(rd->argintregs[2], REG_SP, cd->stackframesize * 8);
268 M_ASUB_IMM(2 * 8, REG_SP);
269 M_AST(rd->argintregs[3], REG_SP, 0 * 8); /* store XPC */
273 M_ALD(REG_ITMP2_XPC, REG_SP, 0 * 8);
274 M_AADD_IMM(2 * 8, REG_SP);
276 M_MOV_IMM(asm_handle_exception, REG_ITMP3);
280 M_JMP_IMM((cd->mcodebase + targetdisp) -
281 (cd->mcodeptr + PATCHER_CALL_SIZE));
288 /* emit_patcher_stubs **********************************************************
290 Generates the code for the patcher stubs.
292 *******************************************************************************/
294 __PORTED__ void emit_patcher_stubs(jitdata *jd)
305 /* get required compiler data */
309 /* generate code patching stub call code */
313 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
314 /* check code segment size */
318 /* Get machine code which is patched back in later. The
319 call is 1 instruction word long. */
321 tmpmcodeptr = (u1 *) (cd->mcodebase + pref->branchpos);
323 mcode = *((u4 *) tmpmcodeptr);
325 /* Patch in the call to call the following code (done at
328 savedmcodeptr = cd->mcodeptr; /* save current mcodeptr */
329 cd->mcodeptr = tmpmcodeptr; /* set mcodeptr to patch position */
331 disp = (savedmcodeptr) - (tmpmcodeptr);
332 M_BSR(REG_ITMP3, disp);
334 cd->mcodeptr = savedmcodeptr; /* restore the current mcodeptr */
336 /* create stack frame */
338 M_ASUB_IMM(6 * 4, REG_SP);
340 /* move return address onto stack */
342 M_AST(REG_ITMP3, REG_SP, 5 * 4);
344 /* move pointer to java_objectheader onto stack */
346 #if defined(ENABLE_THREADS)
347 /* create a virtual java_objectheader */
349 (void) dseg_add_unique_address(cd, NULL); /* flcword */
350 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
351 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
353 M_LDA(REG_ITMP3, REG_PV, disp);
354 M_AST(REG_ITMP3, REG_SP, 4 * 4);
359 /* move machine code onto stack */
361 disp = dseg_add_s4(cd, mcode);
362 M_ILD(REG_ITMP3, REG_PV, disp);
363 M_IST(REG_ITMP3, REG_SP, 3 * 4);
365 /* move class/method/field reference onto stack */
367 disp = dseg_add_address(cd, pref->ref);
368 M_ALD(REG_ITMP3, REG_PV, disp);
369 M_AST(REG_ITMP3, REG_SP, 2 * 4);
371 /* move data segment displacement onto stack */
373 disp = dseg_add_s4(cd, pref->disp);
374 M_ILD(REG_ITMP3, REG_PV, disp);
375 M_IST(REG_ITMP3, REG_SP, 1 * 4);
377 /* move patcher function pointer onto stack */
379 disp = dseg_add_functionptr(cd, pref->patcher);
380 M_ALD(REG_ITMP3, REG_PV, disp);
381 M_AST(REG_ITMP3, REG_SP, 0 * 4);
383 if (targetdisp == 0) {
384 targetdisp = (cd->mcodeptr) - (cd->mcodebase);
386 disp = dseg_add_functionptr(cd, asm_patcher_wrapper);
387 M_ALD(REG_ITMP3, REG_PV, disp);
388 M_JMP(RN, REG_ITMP3);
391 disp = ((cd->mcodebase) + targetdisp) -
400 /* emit_replacement_stubs ******************************************************
402 Generates the code for the replacement stubs.
404 *******************************************************************************/
406 void emit_replacement_stubs(jitdata *jd)
415 /* get required compiler data */
420 rplp = code->rplpoints;
422 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
423 /* check code segment size */
427 /* note start of stub code */
429 rplp->outcode = (u1 *) (ptrint) (cd->mcodeptr - cd->mcodebase);
431 /* make machine code for patching */
433 disp = (ptrint) (rplp->outcode - rplp->pc) - 5;
435 rplp->mcode = 0xe9 | ((u8) disp << 8);
437 /* push address of `rplpoint` struct */
439 M_MOV_IMM(rplp, REG_ITMP3);
442 /* jump to replacement function */
444 M_MOV_IMM(asm_replacement_out, REG_ITMP3);
451 /* emit_verbosecall_enter ******************************************************
453 Generates the code for the call trace.
455 *******************************************************************************/
458 void emit_verbosecall_enter(jitdata *jd)
466 s4 stackframesize, off, foff, aoff, doff, t, iargctr, fargctr, disp;
468 /* get required compiler data */
476 /* mark trace code */
481 (6 * 8) + /* s8 on stack parameters x 6 */
482 (1 * 4) + /* methodinfo on stack parameter */
487 M_ASUB_IMM(stackframesize, REG_SP); /* allocate stackframe */
489 /* save argument registers */
491 off = (6 * 8) + (1 * 4);
493 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
494 M_IST(rd->argintregs[i], REG_SP, off);
496 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
497 M_DST(rd->argfltregs[i], REG_SP, off);
499 /* save temporary registers for leaf methods */
501 if (jd->isleafmethod) {
502 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
503 M_LST(rd->tmpintregs[i], REG_SP, off);
505 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
506 M_DST(rd->tmpfltregs[i], REG_SP, off);
509 /* Load arguments to new locations */
511 /* First move all arguments to stack
516 * (s8) a1 \ Auxilliary stack frame
521 M_ASUB_IMM(2 * 8, REG_SP);
523 /* offset to where first integer arg is saved on stack */
524 off = (2 * 8) + (6 * 8) + (1 * 4);
525 /* offset to where first float arg is saved on stack */
526 foff = off + (INT_ARG_CNT * 8);
527 /* offset to where first argument is passed on stack */
528 aoff = (2 * 8) + stackframesize + (cd->stackframesize * 4);
529 /* offset to destination on stack */
532 iargctr = fargctr = 0;
534 ICONST(REG_ITMP1, 0);
536 for (i = 0; i < md->paramcount && i < 8; i++) {
537 t = md->paramtypes[i].type;
539 M_IST(REG_ITMP1, REG_SP, doff);
540 M_IST(REG_ITMP1, REG_SP, doff + 4);
542 if (IS_FLT_DBL_TYPE(t)) {
543 if (fargctr < 2) { /* passed in register */
544 N_STD(REG_FA0 + fargctr, doff, RN, REG_SP);
546 } else { /* passed on stack */
547 if (IS_2_WORD_TYPE(t)) {
548 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
551 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
556 if (IS_2_WORD_TYPE(t)) {
557 if (iargctr < 4) { /* passed in 2 registers */
558 N_STM(REG_A0 + iargctr, REG_A0 + iargctr + 1, doff, REG_SP);
560 } else { /* passed on stack */
561 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
565 if (iargctr < 5) { /* passed in register */
566 N_ST(REG_A0 + iargctr, doff + 4, RN, REG_SP);
568 } else { /* passed on stack */
569 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
578 /* Now move a0 and a1 to registers
588 N_LM(REG_A0, REG_A1, 0, REG_SP);
589 N_LM(REG_A2, REG_A3, 8, REG_SP);
591 M_AADD_IMM(2 * 8, REG_SP);
593 /* Finally load methodinfo argument */
595 disp = dseg_add_address(cd, m);
596 M_ALD(REG_ITMP2, REG_PV, disp);
597 M_AST(REG_ITMP2, REG_SP, 6 * 8);
599 /* Call builtin_verbosecall_enter */
601 disp = dseg_add_address(cd, builtin_verbosecall_enter);
602 M_ALD(REG_ITMP2, REG_PV, disp);
603 M_ASUB_IMM(96, REG_SP);
605 M_AADD_IMM(96, REG_SP);
607 /* restore argument registers */
609 off = (6 * 8) + (1 * 4);
611 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
612 M_ILD(rd->argintregs[i], REG_SP, off);
614 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
615 M_DLD(rd->argfltregs[i], REG_SP, off);
617 /* restore temporary registers for leaf methods */
619 if (jd->isleafmethod) {
620 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
621 M_ILD(rd->tmpintregs[i], REG_SP, off);
623 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
624 M_DLD(rd->tmpfltregs[i], REG_SP, off);
627 /* remove stackframe */
629 M_AADD_IMM(stackframesize, REG_SP);
631 /* mark trace code */
635 #endif /* !defined(NDEBUG) */
638 /* emit_verbosecall_exit *******************************************************
640 Generates the code for the call trace.
642 *******************************************************************************/
645 void emit_verbosecall_exit(jitdata *jd)
652 /* get required compiler data */
658 /* mark trace code */
662 M_ASUB_IMM(2 * 8, REG_SP);
664 N_STM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
665 M_DST(REG_FRESULT, REG_SP, 1 * 8);
667 if (IS_2_WORD_TYPE(m->parseddesc->returntype.type)) {
668 /* (REG_A0, REG_A1) == (REG_RESULT, REG_RESULT2), se no need to move */
670 M_INTMOVE(REG_RESULT, REG_A1);
674 disp = dseg_add_address(cd, m);
675 M_ALD(REG_A2, REG_PV, disp);
677 /* REG_FRESULT is REG_FA0, so no need to move */
678 M_FLTMOVE(REG_FRESULT, REG_FA1);
680 disp = dseg_add_address(cd, builtin_verbosecall_exit);
681 M_ALD(REG_ITMP1, REG_PV, disp);
682 M_ASUB_IMM(96, REG_SP);
684 M_AADD_IMM(96, REG_SP);
686 N_LM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
687 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
689 M_AADD_IMM(2 * 8, REG_SP);
691 /* mark trace code */
695 #endif /* !defined(NDEBUG) */
698 /* code generation functions **************************************************/
700 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
702 if ((basereg == REG_SP) || (basereg == R12)) {
704 emit_address_byte(0, dreg, REG_SP);
705 emit_address_byte(0, REG_SP, REG_SP);
707 } else if (IS_IMM8(disp)) {
708 emit_address_byte(1, dreg, REG_SP);
709 emit_address_byte(0, REG_SP, REG_SP);
713 emit_address_byte(2, dreg, REG_SP);
714 emit_address_byte(0, REG_SP, REG_SP);
718 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
719 emit_address_byte(0,(dreg),(basereg));
721 } else if ((basereg) == RIP) {
722 emit_address_byte(0, dreg, RBP);
727 emit_address_byte(1, dreg, basereg);
731 emit_address_byte(2, dreg, basereg);
738 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
740 if ((basereg == REG_SP) || (basereg == R12)) {
741 emit_address_byte(2, dreg, REG_SP);
742 emit_address_byte(0, REG_SP, REG_SP);
746 emit_address_byte(2, dreg, basereg);
752 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
755 emit_address_byte(0, reg, 4);
756 emit_address_byte(scale, indexreg, 5);
759 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
760 emit_address_byte(0, reg, 4);
761 emit_address_byte(scale, indexreg, basereg);
763 else if (IS_IMM8(disp)) {
764 emit_address_byte(1, reg, 4);
765 emit_address_byte(scale, indexreg, basereg);
769 emit_address_byte(2, reg, 4);
770 emit_address_byte(scale, indexreg, basereg);
776 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
779 varinfo *v_s1,*v_s2,*v_dst;
782 /* get required compiler data */
786 v_s1 = VAROP(iptr->s1);
787 v_s2 = VAROP(iptr->sx.s23.s2);
788 v_dst = VAROP(iptr->dst);
790 s1 = v_s1->vv.regoff;
791 s2 = v_s2->vv.regoff;
792 d = v_dst->vv.regoff;
794 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
796 if (IS_INMEMORY(v_dst->flags)) {
797 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
799 M_ILD(RCX, REG_SP, s2 * 8);
800 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
803 M_ILD(RCX, REG_SP, s2 * 8);
804 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
805 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
806 M_IST(REG_ITMP2, REG_SP, d * 8);
809 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
810 /* s1 may be equal to RCX */
813 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
814 M_IST(s1, REG_SP, d * 8);
815 M_INTMOVE(REG_ITMP1, RCX);
818 M_IST(s1, REG_SP, d * 8);
819 M_ILD(RCX, REG_SP, s2 * 8);
823 M_ILD(RCX, REG_SP, s2 * 8);
824 M_IST(s1, REG_SP, d * 8);
827 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
829 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
832 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
836 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
837 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
838 M_IST(REG_ITMP2, REG_SP, d * 8);
842 /* s1 may be equal to RCX */
843 M_IST(s1, REG_SP, d * 8);
845 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
848 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
856 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
857 M_ILD(RCX, REG_SP, s2 * 8);
858 M_ILD(d, REG_SP, s1 * 8);
859 emit_shiftl_reg(cd, shift_op, d);
861 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
862 /* s1 may be equal to RCX */
864 M_ILD(RCX, REG_SP, s2 * 8);
865 emit_shiftl_reg(cd, shift_op, d);
867 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
869 M_ILD(d, REG_SP, s1 * 8);
870 emit_shiftl_reg(cd, shift_op, d);
873 /* s1 may be equal to RCX */
876 /* d cannot be used to backup s1 since this would
878 M_INTMOVE(s1, REG_ITMP3);
880 M_INTMOVE(REG_ITMP3, d);
888 /* d may be equal to s2 */
892 emit_shiftl_reg(cd, shift_op, d);
896 M_INTMOVE(REG_ITMP3, RCX);
898 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
903 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
906 varinfo *v_s1,*v_s2,*v_dst;
909 /* get required compiler data */
913 v_s1 = VAROP(iptr->s1);
914 v_s2 = VAROP(iptr->sx.s23.s2);
915 v_dst = VAROP(iptr->dst);
917 s1 = v_s1->vv.regoff;
918 s2 = v_s2->vv.regoff;
919 d = v_dst->vv.regoff;
921 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
923 if (IS_INMEMORY(v_dst->flags)) {
924 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
926 M_ILD(RCX, REG_SP, s2 * 8);
927 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
930 M_ILD(RCX, REG_SP, s2 * 8);
931 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
932 emit_shift_reg(cd, shift_op, REG_ITMP2);
933 M_LST(REG_ITMP2, REG_SP, d * 8);
936 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
937 /* s1 may be equal to RCX */
940 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
941 M_LST(s1, REG_SP, d * 8);
942 M_INTMOVE(REG_ITMP1, RCX);
945 M_LST(s1, REG_SP, d * 8);
946 M_ILD(RCX, REG_SP, s2 * 8);
950 M_ILD(RCX, REG_SP, s2 * 8);
951 M_LST(s1, REG_SP, d * 8);
954 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
956 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
959 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
963 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
964 emit_shift_reg(cd, shift_op, REG_ITMP2);
965 M_LST(REG_ITMP2, REG_SP, d * 8);
969 /* s1 may be equal to RCX */
970 M_LST(s1, REG_SP, d * 8);
972 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
975 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
983 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
984 M_ILD(RCX, REG_SP, s2 * 8);
985 M_LLD(d, REG_SP, s1 * 8);
986 emit_shift_reg(cd, shift_op, d);
988 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
989 /* s1 may be equal to RCX */
991 M_ILD(RCX, REG_SP, s2 * 8);
992 emit_shift_reg(cd, shift_op, d);
994 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
996 M_LLD(d, REG_SP, s1 * 8);
997 emit_shift_reg(cd, shift_op, d);
1000 /* s1 may be equal to RCX */
1003 /* d cannot be used to backup s1 since this would
1005 M_INTMOVE(s1, REG_ITMP3);
1007 M_INTMOVE(REG_ITMP3, d);
1015 /* d may be equal to s2 */
1019 emit_shift_reg(cd, shift_op, d);
1023 M_INTMOVE(REG_ITMP3, RCX);
1025 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1030 /* low-level code emitter functions *******************************************/
1032 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1034 emit_rex(1,(reg),0,(dreg));
1035 *(cd->mcodeptr++) = 0x89;
1036 emit_reg((reg),(dreg));
1040 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1042 emit_rex(1,0,0,(reg));
1043 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1048 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1050 emit_rex(0,(reg),0,(dreg));
1051 *(cd->mcodeptr++) = 0x89;
1052 emit_reg((reg),(dreg));
1056 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1057 emit_rex(0,0,0,(reg));
1058 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1063 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1064 emit_rex(1,(reg),0,(basereg));
1065 *(cd->mcodeptr++) = 0x8b;
1066 emit_membase(cd, (basereg),(disp),(reg));
1071 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1072 * constant membase immediate length of 32bit
1074 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1075 emit_rex(1,(reg),0,(basereg));
1076 *(cd->mcodeptr++) = 0x8b;
1077 emit_membase32(cd, (basereg),(disp),(reg));
1081 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1083 emit_rex(0,(reg),0,(basereg));
1084 *(cd->mcodeptr++) = 0x8b;
1085 emit_membase(cd, (basereg),(disp),(reg));
1089 /* ATTENTION: Always emit a REX byte, because the instruction size can
1090 be smaller when all register indexes are smaller than 7. */
1091 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1093 emit_byte_rex((reg),0,(basereg));
1094 *(cd->mcodeptr++) = 0x8b;
1095 emit_membase32(cd, (basereg),(disp),(reg));
1099 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1100 emit_rex(1,(reg),0,(basereg));
1101 *(cd->mcodeptr++) = 0x89;
1102 emit_membase(cd, (basereg),(disp),(reg));
1106 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1107 emit_rex(1,(reg),0,(basereg));
1108 *(cd->mcodeptr++) = 0x89;
1109 emit_membase32(cd, (basereg),(disp),(reg));
1113 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1114 emit_rex(0,(reg),0,(basereg));
1115 *(cd->mcodeptr++) = 0x89;
1116 emit_membase(cd, (basereg),(disp),(reg));
1120 /* Always emit a REX byte, because the instruction size can be smaller when */
1121 /* all register indexes are smaller than 7. */
1122 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1123 emit_byte_rex((reg),0,(basereg));
1124 *(cd->mcodeptr++) = 0x89;
1125 emit_membase32(cd, (basereg),(disp),(reg));
1129 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1130 emit_rex(1,(reg),(indexreg),(basereg));
1131 *(cd->mcodeptr++) = 0x8b;
1132 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1136 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1137 emit_rex(0,(reg),(indexreg),(basereg));
1138 *(cd->mcodeptr++) = 0x8b;
1139 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1143 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1144 emit_rex(1,(reg),(indexreg),(basereg));
1145 *(cd->mcodeptr++) = 0x89;
1146 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1150 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1151 emit_rex(0,(reg),(indexreg),(basereg));
1152 *(cd->mcodeptr++) = 0x89;
1153 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1157 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1158 *(cd->mcodeptr++) = 0x66;
1159 emit_rex(0,(reg),(indexreg),(basereg));
1160 *(cd->mcodeptr++) = 0x89;
1161 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1165 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1166 emit_byte_rex((reg),(indexreg),(basereg));
1167 *(cd->mcodeptr++) = 0x88;
1168 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1172 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1173 emit_rex(1,0,0,(basereg));
1174 *(cd->mcodeptr++) = 0xc7;
1175 emit_membase(cd, (basereg),(disp),0);
1180 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1181 emit_rex(1,0,0,(basereg));
1182 *(cd->mcodeptr++) = 0xc7;
1183 emit_membase32(cd, (basereg),(disp),0);
1188 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1189 emit_rex(0,0,0,(basereg));
1190 *(cd->mcodeptr++) = 0xc7;
1191 emit_membase(cd, (basereg),(disp),0);
1196 /* Always emit a REX byte, because the instruction size can be smaller when */
1197 /* all register indexes are smaller than 7. */
1198 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1199 emit_byte_rex(0,0,(basereg));
1200 *(cd->mcodeptr++) = 0xc7;
1201 emit_membase32(cd, (basereg),(disp),0);
1206 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1208 emit_rex(1,(dreg),0,(reg));
1209 *(cd->mcodeptr++) = 0x0f;
1210 *(cd->mcodeptr++) = 0xbe;
1211 /* XXX: why do reg and dreg have to be exchanged */
1212 emit_reg((dreg),(reg));
1216 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1218 emit_rex(1,(dreg),0,(reg));
1219 *(cd->mcodeptr++) = 0x0f;
1220 *(cd->mcodeptr++) = 0xbf;
1221 /* XXX: why do reg and dreg have to be exchanged */
1222 emit_reg((dreg),(reg));
1226 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1228 emit_rex(1,(dreg),0,(reg));
1229 *(cd->mcodeptr++) = 0x63;
1230 /* XXX: why do reg and dreg have to be exchanged */
1231 emit_reg((dreg),(reg));
1235 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1237 emit_rex(1,(dreg),0,(reg));
1238 *(cd->mcodeptr++) = 0x0f;
1239 *(cd->mcodeptr++) = 0xb7;
1240 /* XXX: why do reg and dreg have to be exchanged */
1241 emit_reg((dreg),(reg));
1245 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1246 emit_rex(1,(reg),(indexreg),(basereg));
1247 *(cd->mcodeptr++) = 0x0f;
1248 *(cd->mcodeptr++) = 0xbf;
1249 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1253 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1254 emit_rex(1,(reg),(indexreg),(basereg));
1255 *(cd->mcodeptr++) = 0x0f;
1256 *(cd->mcodeptr++) = 0xbe;
1257 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1261 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1262 emit_rex(1,(reg),(indexreg),(basereg));
1263 *(cd->mcodeptr++) = 0x0f;
1264 *(cd->mcodeptr++) = 0xb7;
1265 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1269 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1271 emit_rex(1,0,(indexreg),(basereg));
1272 *(cd->mcodeptr++) = 0xc7;
1273 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1278 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1280 emit_rex(0,0,(indexreg),(basereg));
1281 *(cd->mcodeptr++) = 0xc7;
1282 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1287 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1289 *(cd->mcodeptr++) = 0x66;
1290 emit_rex(0,0,(indexreg),(basereg));
1291 *(cd->mcodeptr++) = 0xc7;
1292 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1297 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1299 emit_rex(0,0,(indexreg),(basereg));
1300 *(cd->mcodeptr++) = 0xc6;
1301 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1309 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1311 emit_rex(1,(reg),0,(dreg));
1312 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1313 emit_reg((reg),(dreg));
1317 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1319 emit_rex(0,(reg),0,(dreg));
1320 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1321 emit_reg((reg),(dreg));
1325 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1327 emit_rex(1,(reg),0,(basereg));
1328 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1329 emit_membase(cd, (basereg),(disp),(reg));
1333 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1335 emit_rex(0,(reg),0,(basereg));
1336 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1337 emit_membase(cd, (basereg),(disp),(reg));
1341 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1343 emit_rex(1,(reg),0,(basereg));
1344 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1345 emit_membase(cd, (basereg),(disp),(reg));
1349 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1351 emit_rex(0,(reg),0,(basereg));
1352 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1353 emit_membase(cd, (basereg),(disp),(reg));
1357 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1359 emit_rex(1,0,0,(dreg));
1360 *(cd->mcodeptr++) = 0x83;
1361 emit_reg((opc),(dreg));
1364 emit_rex(1,0,0,(dreg));
1365 *(cd->mcodeptr++) = 0x81;
1366 emit_reg((opc),(dreg));
1372 void emit_alu_imm32_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1373 emit_rex(1,0,0,(dreg));
1374 *(cd->mcodeptr++) = 0x81;
1375 emit_reg((opc),(dreg));
1380 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1382 emit_rex(0,0,0,(dreg));
1383 *(cd->mcodeptr++) = 0x83;
1384 emit_reg((opc),(dreg));
1387 emit_rex(0,0,0,(dreg));
1388 *(cd->mcodeptr++) = 0x81;
1389 emit_reg((opc),(dreg));
1395 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1397 emit_rex(1,(basereg),0,0);
1398 *(cd->mcodeptr++) = 0x83;
1399 emit_membase(cd, (basereg),(disp),(opc));
1402 emit_rex(1,(basereg),0,0);
1403 *(cd->mcodeptr++) = 0x81;
1404 emit_membase(cd, (basereg),(disp),(opc));
1410 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1412 emit_rex(0,(basereg),0,0);
1413 *(cd->mcodeptr++) = 0x83;
1414 emit_membase(cd, (basereg),(disp),(opc));
1417 emit_rex(0,(basereg),0,0);
1418 *(cd->mcodeptr++) = 0x81;
1419 emit_membase(cd, (basereg),(disp),(opc));
1425 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1426 emit_rex(1,(reg),0,(dreg));
1427 *(cd->mcodeptr++) = 0x85;
1428 emit_reg((reg),(dreg));
1432 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1433 emit_rex(0,(reg),0,(dreg));
1434 *(cd->mcodeptr++) = 0x85;
1435 emit_reg((reg),(dreg));
1439 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1440 *(cd->mcodeptr++) = 0xf7;
1446 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1447 *(cd->mcodeptr++) = 0x66;
1448 *(cd->mcodeptr++) = 0xf7;
1454 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1455 *(cd->mcodeptr++) = 0xf6;
1461 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1462 emit_rex(1,(reg),0,(basereg));
1463 *(cd->mcodeptr++) = 0x8d;
1464 emit_membase(cd, (basereg),(disp),(reg));
1468 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1469 emit_rex(0,(reg),0,(basereg));
1470 *(cd->mcodeptr++) = 0x8d;
1471 emit_membase(cd, (basereg),(disp),(reg));
1476 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1478 emit_rex(0,0,0,(basereg));
1479 *(cd->mcodeptr++) = 0xff;
1480 emit_membase(cd, (basereg),(disp),0);
1485 void emit_cltd(codegendata *cd) {
1486 *(cd->mcodeptr++) = 0x99;
1490 void emit_cqto(codegendata *cd) {
1492 *(cd->mcodeptr++) = 0x99;
1497 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1498 emit_rex(1,(dreg),0,(reg));
1499 *(cd->mcodeptr++) = 0x0f;
1500 *(cd->mcodeptr++) = 0xaf;
1501 emit_reg((dreg),(reg));
1505 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1506 emit_rex(0,(dreg),0,(reg));
1507 *(cd->mcodeptr++) = 0x0f;
1508 *(cd->mcodeptr++) = 0xaf;
1509 emit_reg((dreg),(reg));
1513 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1514 emit_rex(1,(dreg),0,(basereg));
1515 *(cd->mcodeptr++) = 0x0f;
1516 *(cd->mcodeptr++) = 0xaf;
1517 emit_membase(cd, (basereg),(disp),(dreg));
1521 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1522 emit_rex(0,(dreg),0,(basereg));
1523 *(cd->mcodeptr++) = 0x0f;
1524 *(cd->mcodeptr++) = 0xaf;
1525 emit_membase(cd, (basereg),(disp),(dreg));
1529 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1530 if (IS_IMM8((imm))) {
1531 emit_rex(1,0,0,(dreg));
1532 *(cd->mcodeptr++) = 0x6b;
1536 emit_rex(1,0,0,(dreg));
1537 *(cd->mcodeptr++) = 0x69;
1544 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1545 if (IS_IMM8((imm))) {
1546 emit_rex(1,(dreg),0,(reg));
1547 *(cd->mcodeptr++) = 0x6b;
1548 emit_reg((dreg),(reg));
1551 emit_rex(1,(dreg),0,(reg));
1552 *(cd->mcodeptr++) = 0x69;
1553 emit_reg((dreg),(reg));
1559 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1560 if (IS_IMM8((imm))) {
1561 emit_rex(0,(dreg),0,(reg));
1562 *(cd->mcodeptr++) = 0x6b;
1563 emit_reg((dreg),(reg));
1566 emit_rex(0,(dreg),0,(reg));
1567 *(cd->mcodeptr++) = 0x69;
1568 emit_reg((dreg),(reg));
1574 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1575 if (IS_IMM8((imm))) {
1576 emit_rex(1,(dreg),0,(basereg));
1577 *(cd->mcodeptr++) = 0x6b;
1578 emit_membase(cd, (basereg),(disp),(dreg));
1581 emit_rex(1,(dreg),0,(basereg));
1582 *(cd->mcodeptr++) = 0x69;
1583 emit_membase(cd, (basereg),(disp),(dreg));
1589 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1590 if (IS_IMM8((imm))) {
1591 emit_rex(0,(dreg),0,(basereg));
1592 *(cd->mcodeptr++) = 0x6b;
1593 emit_membase(cd, (basereg),(disp),(dreg));
1596 emit_rex(0,(dreg),0,(basereg));
1597 *(cd->mcodeptr++) = 0x69;
1598 emit_membase(cd, (basereg),(disp),(dreg));
1604 void emit_idiv_reg(codegendata *cd, s8 reg) {
1605 emit_rex(1,0,0,(reg));
1606 *(cd->mcodeptr++) = 0xf7;
1611 void emit_idivl_reg(codegendata *cd, s8 reg) {
1612 emit_rex(0,0,0,(reg));
1613 *(cd->mcodeptr++) = 0xf7;
1619 void emit_ret(codegendata *cd) {
1620 *(cd->mcodeptr++) = 0xc3;
1628 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1629 emit_rex(1,0,0,(reg));
1630 *(cd->mcodeptr++) = 0xd3;
1631 emit_reg((opc),(reg));
1635 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1636 emit_rex(0,0,0,(reg));
1637 *(cd->mcodeptr++) = 0xd3;
1638 emit_reg((opc),(reg));
1642 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1643 emit_rex(1,0,0,(basereg));
1644 *(cd->mcodeptr++) = 0xd3;
1645 emit_membase(cd, (basereg),(disp),(opc));
1649 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1650 emit_rex(0,0,0,(basereg));
1651 *(cd->mcodeptr++) = 0xd3;
1652 emit_membase(cd, (basereg),(disp),(opc));
1656 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1658 emit_rex(1,0,0,(dreg));
1659 *(cd->mcodeptr++) = 0xd1;
1660 emit_reg((opc),(dreg));
1662 emit_rex(1,0,0,(dreg));
1663 *(cd->mcodeptr++) = 0xc1;
1664 emit_reg((opc),(dreg));
1670 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1672 emit_rex(0,0,0,(dreg));
1673 *(cd->mcodeptr++) = 0xd1;
1674 emit_reg((opc),(dreg));
1676 emit_rex(0,0,0,(dreg));
1677 *(cd->mcodeptr++) = 0xc1;
1678 emit_reg((opc),(dreg));
1684 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1686 emit_rex(1,0,0,(basereg));
1687 *(cd->mcodeptr++) = 0xd1;
1688 emit_membase(cd, (basereg),(disp),(opc));
1690 emit_rex(1,0,0,(basereg));
1691 *(cd->mcodeptr++) = 0xc1;
1692 emit_membase(cd, (basereg),(disp),(opc));
1698 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1700 emit_rex(0,0,0,(basereg));
1701 *(cd->mcodeptr++) = 0xd1;
1702 emit_membase(cd, (basereg),(disp),(opc));
1704 emit_rex(0,0,0,(basereg));
1705 *(cd->mcodeptr++) = 0xc1;
1706 emit_membase(cd, (basereg),(disp),(opc));
1716 void emit_jmp_imm(codegendata *cd, s8 imm) {
1717 *(cd->mcodeptr++) = 0xe9;
1722 void emit_jmp_reg(codegendata *cd, s8 reg) {
1723 emit_rex(0,0,0,(reg));
1724 *(cd->mcodeptr++) = 0xff;
1729 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1730 *(cd->mcodeptr++) = 0x0f;
1731 *(cd->mcodeptr++) = (0x80 + (opc));
1738 * conditional set and move operations
1741 /* we need the rex byte to get all low bytes */
1742 void emit_setcc_reg(codegendata *cd, s8 opc, s8 reg) {
1743 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1744 *(cd->mcodeptr++) = 0x0f;
1745 *(cd->mcodeptr++) = (0x90 + (opc));
1750 /* we need the rex byte to get all low bytes */
1751 void emit_setcc_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1752 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1753 *(cd->mcodeptr++) = 0x0f;
1754 *(cd->mcodeptr++) = (0x90 + (opc));
1755 emit_membase(cd, (basereg),(disp),0);
1759 void emit_cmovcc_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1761 emit_rex(1,(dreg),0,(reg));
1762 *(cd->mcodeptr++) = 0x0f;
1763 *(cd->mcodeptr++) = (0x40 + (opc));
1764 emit_reg((dreg),(reg));
1768 void emit_cmovccl_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1770 emit_rex(0,(dreg),0,(reg));
1771 *(cd->mcodeptr++) = 0x0f;
1772 *(cd->mcodeptr++) = (0x40 + (opc));
1773 emit_reg((dreg),(reg));
1778 void emit_neg_reg(codegendata *cd, s8 reg)
1780 emit_rex(1,0,0,(reg));
1781 *(cd->mcodeptr++) = 0xf7;
1786 void emit_negl_reg(codegendata *cd, s8 reg)
1788 emit_rex(0,0,0,(reg));
1789 *(cd->mcodeptr++) = 0xf7;
1794 void emit_push_reg(codegendata *cd, s8 reg) {
1795 emit_rex(0,0,0,(reg));
1796 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1800 void emit_push_imm(codegendata *cd, s8 imm) {
1801 *(cd->mcodeptr++) = 0x68;
1806 void emit_pop_reg(codegendata *cd, s8 reg) {
1807 emit_rex(0,0,0,(reg));
1808 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1812 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1813 emit_rex(1,(reg),0,(dreg));
1814 *(cd->mcodeptr++) = 0x87;
1815 emit_reg((reg),(dreg));
1819 void emit_nop(codegendata *cd) {
1820 *(cd->mcodeptr++) = 0x90;
1828 void emit_call_reg(codegendata *cd, s8 reg) {
1829 emit_rex(1,0,0,(reg));
1830 *(cd->mcodeptr++) = 0xff;
1835 void emit_call_imm(codegendata *cd, s8 imm) {
1836 *(cd->mcodeptr++) = 0xe8;
1841 void emit_call_mem(codegendata *cd, ptrint mem)
1843 *(cd->mcodeptr++) = 0xff;
1850 * floating point instructions (SSE2)
1852 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1853 *(cd->mcodeptr++) = 0xf2;
1854 emit_rex(0,(dreg),0,(reg));
1855 *(cd->mcodeptr++) = 0x0f;
1856 *(cd->mcodeptr++) = 0x58;
1857 emit_reg((dreg),(reg));
1861 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1862 *(cd->mcodeptr++) = 0xf3;
1863 emit_rex(0,(dreg),0,(reg));
1864 *(cd->mcodeptr++) = 0x0f;
1865 *(cd->mcodeptr++) = 0x58;
1866 emit_reg((dreg),(reg));
1870 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1871 *(cd->mcodeptr++) = 0xf3;
1872 emit_rex(1,(dreg),0,(reg));
1873 *(cd->mcodeptr++) = 0x0f;
1874 *(cd->mcodeptr++) = 0x2a;
1875 emit_reg((dreg),(reg));
1879 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1880 *(cd->mcodeptr++) = 0xf3;
1881 emit_rex(0,(dreg),0,(reg));
1882 *(cd->mcodeptr++) = 0x0f;
1883 *(cd->mcodeptr++) = 0x2a;
1884 emit_reg((dreg),(reg));
1888 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1889 *(cd->mcodeptr++) = 0xf2;
1890 emit_rex(1,(dreg),0,(reg));
1891 *(cd->mcodeptr++) = 0x0f;
1892 *(cd->mcodeptr++) = 0x2a;
1893 emit_reg((dreg),(reg));
1897 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1898 *(cd->mcodeptr++) = 0xf2;
1899 emit_rex(0,(dreg),0,(reg));
1900 *(cd->mcodeptr++) = 0x0f;
1901 *(cd->mcodeptr++) = 0x2a;
1902 emit_reg((dreg),(reg));
1906 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1907 *(cd->mcodeptr++) = 0xf3;
1908 emit_rex(0,(dreg),0,(reg));
1909 *(cd->mcodeptr++) = 0x0f;
1910 *(cd->mcodeptr++) = 0x5a;
1911 emit_reg((dreg),(reg));
1915 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1916 *(cd->mcodeptr++) = 0xf2;
1917 emit_rex(0,(dreg),0,(reg));
1918 *(cd->mcodeptr++) = 0x0f;
1919 *(cd->mcodeptr++) = 0x5a;
1920 emit_reg((dreg),(reg));
1924 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1925 *(cd->mcodeptr++) = 0xf3;
1926 emit_rex(1,(dreg),0,(reg));
1927 *(cd->mcodeptr++) = 0x0f;
1928 *(cd->mcodeptr++) = 0x2c;
1929 emit_reg((dreg),(reg));
1933 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1934 *(cd->mcodeptr++) = 0xf3;
1935 emit_rex(0,(dreg),0,(reg));
1936 *(cd->mcodeptr++) = 0x0f;
1937 *(cd->mcodeptr++) = 0x2c;
1938 emit_reg((dreg),(reg));
1942 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1943 *(cd->mcodeptr++) = 0xf2;
1944 emit_rex(1,(dreg),0,(reg));
1945 *(cd->mcodeptr++) = 0x0f;
1946 *(cd->mcodeptr++) = 0x2c;
1947 emit_reg((dreg),(reg));
1951 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1952 *(cd->mcodeptr++) = 0xf2;
1953 emit_rex(0,(dreg),0,(reg));
1954 *(cd->mcodeptr++) = 0x0f;
1955 *(cd->mcodeptr++) = 0x2c;
1956 emit_reg((dreg),(reg));
1960 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1961 *(cd->mcodeptr++) = 0xf3;
1962 emit_rex(0,(dreg),0,(reg));
1963 *(cd->mcodeptr++) = 0x0f;
1964 *(cd->mcodeptr++) = 0x5e;
1965 emit_reg((dreg),(reg));
1969 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1970 *(cd->mcodeptr++) = 0xf2;
1971 emit_rex(0,(dreg),0,(reg));
1972 *(cd->mcodeptr++) = 0x0f;
1973 *(cd->mcodeptr++) = 0x5e;
1974 emit_reg((dreg),(reg));
1978 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
1979 *(cd->mcodeptr++) = 0x66;
1980 emit_rex(1,(freg),0,(reg));
1981 *(cd->mcodeptr++) = 0x0f;
1982 *(cd->mcodeptr++) = 0x6e;
1983 emit_reg((freg),(reg));
1987 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
1988 *(cd->mcodeptr++) = 0x66;
1989 emit_rex(1,(freg),0,(reg));
1990 *(cd->mcodeptr++) = 0x0f;
1991 *(cd->mcodeptr++) = 0x7e;
1992 emit_reg((freg),(reg));
1996 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1997 *(cd->mcodeptr++) = 0x66;
1998 emit_rex(0,(reg),0,(basereg));
1999 *(cd->mcodeptr++) = 0x0f;
2000 *(cd->mcodeptr++) = 0x7e;
2001 emit_membase(cd, (basereg),(disp),(reg));
2005 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2006 *(cd->mcodeptr++) = 0x66;
2007 emit_rex(0,(reg),(indexreg),(basereg));
2008 *(cd->mcodeptr++) = 0x0f;
2009 *(cd->mcodeptr++) = 0x7e;
2010 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2014 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2015 *(cd->mcodeptr++) = 0x66;
2016 emit_rex(1,(dreg),0,(basereg));
2017 *(cd->mcodeptr++) = 0x0f;
2018 *(cd->mcodeptr++) = 0x6e;
2019 emit_membase(cd, (basereg),(disp),(dreg));
2023 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2024 *(cd->mcodeptr++) = 0x66;
2025 emit_rex(0,(dreg),0,(basereg));
2026 *(cd->mcodeptr++) = 0x0f;
2027 *(cd->mcodeptr++) = 0x6e;
2028 emit_membase(cd, (basereg),(disp),(dreg));
2032 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2033 *(cd->mcodeptr++) = 0x66;
2034 emit_rex(0,(dreg),(indexreg),(basereg));
2035 *(cd->mcodeptr++) = 0x0f;
2036 *(cd->mcodeptr++) = 0x6e;
2037 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2041 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2042 *(cd->mcodeptr++) = 0xf3;
2043 emit_rex(0,(dreg),0,(reg));
2044 *(cd->mcodeptr++) = 0x0f;
2045 *(cd->mcodeptr++) = 0x7e;
2046 emit_reg((dreg),(reg));
2050 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2051 *(cd->mcodeptr++) = 0x66;
2052 emit_rex(0,(reg),0,(basereg));
2053 *(cd->mcodeptr++) = 0x0f;
2054 *(cd->mcodeptr++) = 0xd6;
2055 emit_membase(cd, (basereg),(disp),(reg));
2059 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2060 *(cd->mcodeptr++) = 0xf3;
2061 emit_rex(0,(dreg),0,(basereg));
2062 *(cd->mcodeptr++) = 0x0f;
2063 *(cd->mcodeptr++) = 0x7e;
2064 emit_membase(cd, (basereg),(disp),(dreg));
2068 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2069 *(cd->mcodeptr++) = 0xf3;
2070 emit_rex(0,(reg),0,(dreg));
2071 *(cd->mcodeptr++) = 0x0f;
2072 *(cd->mcodeptr++) = 0x10;
2073 emit_reg((reg),(dreg));
2077 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2078 *(cd->mcodeptr++) = 0xf2;
2079 emit_rex(0,(reg),0,(dreg));
2080 *(cd->mcodeptr++) = 0x0f;
2081 *(cd->mcodeptr++) = 0x10;
2082 emit_reg((reg),(dreg));
2086 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2087 *(cd->mcodeptr++) = 0xf3;
2088 emit_rex(0,(reg),0,(basereg));
2089 *(cd->mcodeptr++) = 0x0f;
2090 *(cd->mcodeptr++) = 0x11;
2091 emit_membase(cd, (basereg),(disp),(reg));
2095 /* Always emit a REX byte, because the instruction size can be smaller when */
2096 /* all register indexes are smaller than 7. */
2097 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2098 *(cd->mcodeptr++) = 0xf3;
2099 emit_byte_rex((reg),0,(basereg));
2100 *(cd->mcodeptr++) = 0x0f;
2101 *(cd->mcodeptr++) = 0x11;
2102 emit_membase32(cd, (basereg),(disp),(reg));
2106 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2107 *(cd->mcodeptr++) = 0xf2;
2108 emit_rex(0,(reg),0,(basereg));
2109 *(cd->mcodeptr++) = 0x0f;
2110 *(cd->mcodeptr++) = 0x11;
2111 emit_membase(cd, (basereg),(disp),(reg));
2115 /* Always emit a REX byte, because the instruction size can be smaller when */
2116 /* all register indexes are smaller than 7. */
2117 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2118 *(cd->mcodeptr++) = 0xf2;
2119 emit_byte_rex((reg),0,(basereg));
2120 *(cd->mcodeptr++) = 0x0f;
2121 *(cd->mcodeptr++) = 0x11;
2122 emit_membase32(cd, (basereg),(disp),(reg));
2126 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2127 *(cd->mcodeptr++) = 0xf3;
2128 emit_rex(0,(dreg),0,(basereg));
2129 *(cd->mcodeptr++) = 0x0f;
2130 *(cd->mcodeptr++) = 0x10;
2131 emit_membase(cd, (basereg),(disp),(dreg));
2135 /* Always emit a REX byte, because the instruction size can be smaller when */
2136 /* all register indexes are smaller than 7. */
2137 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2138 *(cd->mcodeptr++) = 0xf3;
2139 emit_byte_rex((dreg),0,(basereg));
2140 *(cd->mcodeptr++) = 0x0f;
2141 *(cd->mcodeptr++) = 0x10;
2142 emit_membase32(cd, (basereg),(disp),(dreg));
2146 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2148 emit_rex(0,(dreg),0,(basereg));
2149 *(cd->mcodeptr++) = 0x0f;
2150 *(cd->mcodeptr++) = 0x12;
2151 emit_membase(cd, (basereg),(disp),(dreg));
2155 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2157 emit_rex(0,(reg),0,(basereg));
2158 *(cd->mcodeptr++) = 0x0f;
2159 *(cd->mcodeptr++) = 0x13;
2160 emit_membase(cd, (basereg),(disp),(reg));
2164 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2165 *(cd->mcodeptr++) = 0xf2;
2166 emit_rex(0,(dreg),0,(basereg));
2167 *(cd->mcodeptr++) = 0x0f;
2168 *(cd->mcodeptr++) = 0x10;
2169 emit_membase(cd, (basereg),(disp),(dreg));
2173 /* Always emit a REX byte, because the instruction size can be smaller when */
2174 /* all register indexes are smaller than 7. */
2175 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2176 *(cd->mcodeptr++) = 0xf2;
2177 emit_byte_rex((dreg),0,(basereg));
2178 *(cd->mcodeptr++) = 0x0f;
2179 *(cd->mcodeptr++) = 0x10;
2180 emit_membase32(cd, (basereg),(disp),(dreg));
2184 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2186 *(cd->mcodeptr++) = 0x66;
2187 emit_rex(0,(dreg),0,(basereg));
2188 *(cd->mcodeptr++) = 0x0f;
2189 *(cd->mcodeptr++) = 0x12;
2190 emit_membase(cd, (basereg),(disp),(dreg));
2194 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2196 *(cd->mcodeptr++) = 0x66;
2197 emit_rex(0,(reg),0,(basereg));
2198 *(cd->mcodeptr++) = 0x0f;
2199 *(cd->mcodeptr++) = 0x13;
2200 emit_membase(cd, (basereg),(disp),(reg));
2204 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2205 *(cd->mcodeptr++) = 0xf3;
2206 emit_rex(0,(reg),(indexreg),(basereg));
2207 *(cd->mcodeptr++) = 0x0f;
2208 *(cd->mcodeptr++) = 0x11;
2209 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2213 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2214 *(cd->mcodeptr++) = 0xf2;
2215 emit_rex(0,(reg),(indexreg),(basereg));
2216 *(cd->mcodeptr++) = 0x0f;
2217 *(cd->mcodeptr++) = 0x11;
2218 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2222 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2223 *(cd->mcodeptr++) = 0xf3;
2224 emit_rex(0,(dreg),(indexreg),(basereg));
2225 *(cd->mcodeptr++) = 0x0f;
2226 *(cd->mcodeptr++) = 0x10;
2227 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2231 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2232 *(cd->mcodeptr++) = 0xf2;
2233 emit_rex(0,(dreg),(indexreg),(basereg));
2234 *(cd->mcodeptr++) = 0x0f;
2235 *(cd->mcodeptr++) = 0x10;
2236 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2240 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2241 *(cd->mcodeptr++) = 0xf3;
2242 emit_rex(0,(dreg),0,(reg));
2243 *(cd->mcodeptr++) = 0x0f;
2244 *(cd->mcodeptr++) = 0x59;
2245 emit_reg((dreg),(reg));
2249 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2250 *(cd->mcodeptr++) = 0xf2;
2251 emit_rex(0,(dreg),0,(reg));
2252 *(cd->mcodeptr++) = 0x0f;
2253 *(cd->mcodeptr++) = 0x59;
2254 emit_reg((dreg),(reg));
2258 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2259 *(cd->mcodeptr++) = 0xf3;
2260 emit_rex(0,(dreg),0,(reg));
2261 *(cd->mcodeptr++) = 0x0f;
2262 *(cd->mcodeptr++) = 0x5c;
2263 emit_reg((dreg),(reg));
2267 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2268 *(cd->mcodeptr++) = 0xf2;
2269 emit_rex(0,(dreg),0,(reg));
2270 *(cd->mcodeptr++) = 0x0f;
2271 *(cd->mcodeptr++) = 0x5c;
2272 emit_reg((dreg),(reg));
2276 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2277 emit_rex(0,(dreg),0,(reg));
2278 *(cd->mcodeptr++) = 0x0f;
2279 *(cd->mcodeptr++) = 0x2e;
2280 emit_reg((dreg),(reg));
2284 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2285 *(cd->mcodeptr++) = 0x66;
2286 emit_rex(0,(dreg),0,(reg));
2287 *(cd->mcodeptr++) = 0x0f;
2288 *(cd->mcodeptr++) = 0x2e;
2289 emit_reg((dreg),(reg));
2293 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2294 emit_rex(0,(dreg),0,(reg));
2295 *(cd->mcodeptr++) = 0x0f;
2296 *(cd->mcodeptr++) = 0x57;
2297 emit_reg((dreg),(reg));
2301 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2302 emit_rex(0,(dreg),0,(basereg));
2303 *(cd->mcodeptr++) = 0x0f;
2304 *(cd->mcodeptr++) = 0x57;
2305 emit_membase(cd, (basereg),(disp),(dreg));
2309 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2310 *(cd->mcodeptr++) = 0x66;
2311 emit_rex(0,(dreg),0,(reg));
2312 *(cd->mcodeptr++) = 0x0f;
2313 *(cd->mcodeptr++) = 0x57;
2314 emit_reg((dreg),(reg));
2318 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2319 *(cd->mcodeptr++) = 0x66;
2320 emit_rex(0,(dreg),0,(basereg));
2321 *(cd->mcodeptr++) = 0x0f;
2322 *(cd->mcodeptr++) = 0x57;
2323 emit_membase(cd, (basereg),(disp),(dreg));
2327 /* system instructions ********************************************************/
2329 void emit_rdtsc(codegendata *cd)
2331 *(cd->mcodeptr++) = 0x0f;
2332 *(cd->mcodeptr++) = 0x31;
2335 /* emit_load_high **************************************************************
2337 Emits a possible load of the high 32-bits of an operand.
2339 *******************************************************************************/
2341 s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
2347 assert(src->type == TYPE_LNG);
2349 /* get required compiler data */
2353 if (IS_INMEMORY(src->flags)) {
2356 disp = src->vv.regoff * 4;
2358 M_ILD(tempreg, REG_SP, disp);
2363 reg = GET_HIGH_REG(src->vv.regoff);
2368 /* emit_load_low ***************************************************************
2370 Emits a possible load of the low 32-bits of an operand.
2372 *******************************************************************************/
2374 s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
2380 assert(src->type == TYPE_LNG);
2382 /* get required compiler data */
2386 if (IS_INMEMORY(src->flags)) {
2389 disp = src->vv.regoff * 4;
2391 M_ILD(tempreg, REG_SP, disp + 4);
2396 reg = GET_LOW_REG(src->vv.regoff);
2401 /* emit_nullpointer_check ******************************************************
2403 Emit a NullPointerException check.
2405 *******************************************************************************/
2407 __PORTED__ void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
2409 if (INSTRUCTION_MUST_CHECK(iptr)) {
2412 codegen_add_nullpointerexception_ref(cd);
2416 /* emit_arrayindexoutofbounds_check ********************************************
2418 Emit a ArrayIndexOutOfBoundsException check.
2420 *******************************************************************************/
2422 __PORTED__ void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
2424 if (INSTRUCTION_MUST_CHECK(iptr)) {
2425 N_C(s2, OFFSET(java_arrayheader, size), RN, s1);
2427 codegen_add_arrayindexoutofboundsexception_ref(cd, s2);
2431 s4 emit_load_s1_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
2432 codegendata *cd = jd->cd;
2433 s4 reg = emit_load_s1(jd, iptr, tempreg);
2435 M_MOV(reg, tempreg);
2442 s4 emit_load_s2_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
2443 codegendata *cd = jd->cd;
2444 s4 reg = emit_load_s2(jd, iptr, tempreg);
2446 M_MOV(reg, tempreg);
2454 * These are local overrides for various environment variables in Emacs.
2455 * Please do not remove this and leave it at the end of the file, where
2456 * Emacs will automagically detect them.
2457 * ---------------------------------------------------------------------
2460 * indent-tabs-mode: t