1 /* src/vm/jit/s390/emit.c - s390 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 7848 2007-05-01 21:40:26Z pm $
38 #include "vm/jit/s390/codegen.h"
39 #include "vm/jit/s390/emit.h"
41 #if defined(ENABLE_THREADS)
42 # include "threads/native/lock.h"
45 #include "vm/builtin.h"
46 #include "vm/jit/abi-asm.h"
47 #include "vm/jit/asmpart.h"
48 #include "vm/jit/codegen-common.h"
49 #include "vm/jit/emit-common.h"
50 #include "vm/jit/jit.h"
51 #include "vm/jit/replace.h"
52 #include "vm/jit/abi.h"
53 #include "vm/global.h"
54 #include "mm/memory.h"
55 #include "vm/exceptions.h"
59 /* emit_load *******************************************************************
61 Emits a possible load of an operand.
63 *******************************************************************************/
65 __PORTED__ s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
71 /* get required compiler data */
75 if (IS_INMEMORY(src->flags)) {
78 disp = src->vv.regoff * 4;
80 if (IS_FLT_DBL_TYPE(src->type)) {
81 if (IS_2_WORD_TYPE(src->type))
82 M_DLD(tempreg, REG_SP, disp);
84 M_FLD(tempreg, REG_SP, disp);
87 if (IS_2_WORD_TYPE(src->type))
88 M_LLD(tempreg, REG_SP, disp);
90 M_ILD(tempreg, REG_SP, disp);
102 /* emit_store ******************************************************************
104 This function generates the code to store the result of an
105 operation back into a spilled pseudo-variable. If the
106 pseudo-variable has not been spilled in the first place, this
107 function will generate nothing.
109 *******************************************************************************/
111 __PORTED__ inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
115 /* get required compiler data */
119 if (IS_INMEMORY(dst->flags)) {
122 if (IS_FLT_DBL_TYPE(dst->type)) {
123 if (IS_2_WORD_TYPE(dst->type))
124 M_DST(d, REG_SP, dst->vv.regoff * 4);
126 M_FST(d, REG_SP, dst->vv.regoff * 4);
129 if (IS_2_WORD_TYPE(dst->type))
130 M_LST(d, REG_SP, dst->vv.regoff * 4);
132 M_IST(d, REG_SP, dst->vv.regoff * 4);
138 /* emit_copy *******************************************************************
140 Generates a register/memory to register/memory copy.
142 *******************************************************************************/
144 __PORTED__ void emit_copy(jitdata *jd, instruction *iptr)
151 /* get required compiler data */
155 /* get source and destination variables */
157 src = VAROP(iptr->s1);
158 dst = VAROP(iptr->dst);
160 if ((src->vv.regoff != dst->vv.regoff) ||
161 ((src->flags ^ dst->flags) & INMEMORY)) {
163 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
164 /* emit nothing, as the value won't be used anyway */
168 /* If one of the variables resides in memory, we can eliminate
169 the register move from/to the temporary register with the
170 order of getting the destination register and the load. */
172 if (IS_INMEMORY(src->flags)) {
173 if (IS_FLT_DBL_TYPE(dst->type)) {
174 d = codegen_reg_of_var(iptr->opc, dst, REG_FTMP1);
176 if (IS_2_WORD_TYPE(dst->type)) {
177 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
179 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP1);
182 s1 = emit_load(jd, iptr, src, d);
185 if (IS_FLT_DBL_TYPE(src->type)) {
186 s1 = emit_load(jd, iptr, src, REG_FTMP1);
188 if (IS_2_WORD_TYPE(src->type)) {
189 s1 = emit_load(jd, iptr, src, REG_ITMP12_PACKED);
191 s1 = emit_load(jd, iptr, src, REG_ITMP1);
194 d = codegen_reg_of_var(iptr->opc, dst, s1);
198 if (IS_FLT_DBL_TYPE(src->type)) {
201 if (IS_2_WORD_TYPE(src->type)) {
209 emit_store(jd, iptr, dst, d);
214 /* emit_patcher_stubs **********************************************************
216 Generates the code for the patcher stubs.
218 *******************************************************************************/
220 __PORTED__ void emit_patcher_stubs(jitdata *jd)
231 /* get required compiler data */
235 /* generate code patching stub call code */
239 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
240 /* check code segment size */
244 /* Get machine code which is patched back in later. The
245 call is 1 instruction word long. */
247 tmpmcodeptr = (u1 *) (cd->mcodebase + pref->branchpos);
249 mcode = *((u4 *) tmpmcodeptr);
251 /* Patch in the call to call the following code (done at
254 savedmcodeptr = cd->mcodeptr; /* save current mcodeptr */
255 cd->mcodeptr = tmpmcodeptr; /* set mcodeptr to patch position */
257 disp = (savedmcodeptr) - (tmpmcodeptr);
258 M_BSR(REG_ITMP3, disp);
260 cd->mcodeptr = savedmcodeptr; /* restore the current mcodeptr */
262 /* create stack frame */
264 M_ASUB_IMM(6 * 4, REG_SP);
266 /* move return address onto stack */
268 M_AST(REG_ITMP3, REG_SP, 5 * 4);
270 /* move pointer to java_objectheader onto stack */
272 #if defined(ENABLE_THREADS)
273 /* create a virtual java_objectheader */
275 (void) dseg_add_unique_address(cd, NULL); /* flcword */
276 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
277 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
279 M_LDA(REG_ITMP3, REG_PV, disp);
280 M_AST(REG_ITMP3, REG_SP, 4 * 4);
285 /* move machine code onto stack */
287 disp = dseg_add_s4(cd, mcode);
288 M_ILD(REG_ITMP3, REG_PV, disp);
289 M_IST(REG_ITMP3, REG_SP, 3 * 4);
291 /* move class/method/field reference onto stack */
293 disp = dseg_add_address(cd, pref->ref);
294 M_ALD(REG_ITMP3, REG_PV, disp);
295 M_AST(REG_ITMP3, REG_SP, 2 * 4);
297 /* move data segment displacement onto stack */
299 disp = dseg_add_s4(cd, pref->disp);
300 M_ILD(REG_ITMP3, REG_PV, disp);
301 M_IST(REG_ITMP3, REG_SP, 1 * 4);
303 /* move patcher function pointer onto stack */
305 disp = dseg_add_functionptr(cd, pref->patcher);
306 M_ALD(REG_ITMP3, REG_PV, disp);
307 M_AST(REG_ITMP3, REG_SP, 0 * 4);
309 if (targetdisp == 0) {
310 targetdisp = (cd->mcodeptr) - (cd->mcodebase);
312 disp = dseg_add_functionptr(cd, asm_patcher_wrapper);
313 M_ALD(REG_ITMP3, REG_PV, disp);
314 M_JMP(RN, REG_ITMP3);
317 disp = ((cd->mcodebase) + targetdisp) -
326 /* emit_replacement_stubs ******************************************************
328 Generates the code for the replacement stubs.
330 *******************************************************************************/
332 void emit_replacement_stubs(jitdata *jd)
341 /* get required compiler data */
346 rplp = code->rplpoints;
348 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
349 /* check code segment size */
353 /* note start of stub code */
355 rplp->outcode = (u1 *) (ptrint) (cd->mcodeptr - cd->mcodebase);
357 /* make machine code for patching */
359 disp = (ptrint) (rplp->outcode - rplp->pc) - 5;
361 rplp->mcode = 0xe9 | ((u8) disp << 8);
363 /* push address of `rplpoint` struct */
365 M_MOV_IMM(rplp, REG_ITMP3);
368 /* jump to replacement function */
370 M_MOV_IMM(asm_replacement_out, REG_ITMP3);
377 /* emit_verbosecall_enter ******************************************************
379 Generates the code for the call trace.
381 *******************************************************************************/
384 void emit_verbosecall_enter(jitdata *jd)
391 s4 stackframesize, off, foff, aoff, doff, t, iargctr, fargctr, disp;
393 /* get required compiler data */
400 /* mark trace code */
405 (6 * 8) + /* s8 on stack parameters x 6 */
406 (1 * 4) + /* methodinfo on stack parameter */
411 M_ASUB_IMM(stackframesize, REG_SP); /* allocate stackframe */
413 /* save argument registers */
415 off = (6 * 8) + (1 * 4);
417 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
418 M_IST(abi_registers_integer_argument[i], REG_SP, off);
420 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
421 M_DST(abi_registers_float_argument[i], REG_SP, off);
423 /* save temporary registers for leaf methods */
425 if (jd->isleafmethod) {
426 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
427 M_LST(abi_registers_integer_temporary[i], REG_SP, off);
429 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
430 M_DST(abi_registers_float_temporary[i], REG_SP, off);
433 /* Load arguments to new locations */
435 /* First move all arguments to stack
440 * (s8) a1 \ Auxilliary stack frame
445 M_ASUB_IMM(2 * 8, REG_SP);
447 /* offset to where first integer arg is saved on stack */
448 off = (2 * 8) + (6 * 8) + (1 * 4);
449 /* offset to where first float arg is saved on stack */
450 foff = off + (INT_ARG_CNT * 8);
451 /* offset to where first argument is passed on stack */
452 aoff = (2 * 8) + stackframesize + (cd->stackframesize * 4);
453 /* offset to destination on stack */
456 iargctr = fargctr = 0;
458 ICONST(REG_ITMP1, 0);
460 for (i = 0; i < md->paramcount && i < 8; i++) {
461 t = md->paramtypes[i].type;
463 M_IST(REG_ITMP1, REG_SP, doff);
464 M_IST(REG_ITMP1, REG_SP, doff + 4);
466 if (IS_FLT_DBL_TYPE(t)) {
467 if (fargctr < 2) { /* passed in register */
468 N_STD(REG_FA0 + fargctr, doff, RN, REG_SP);
470 } else { /* passed on stack */
471 if (IS_2_WORD_TYPE(t)) {
472 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
475 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
480 if (IS_2_WORD_TYPE(t)) {
481 if (iargctr < 4) { /* passed in 2 registers */
482 N_STM(REG_A0 + iargctr, REG_A0 + iargctr + 1, doff, REG_SP);
484 } else { /* passed on stack */
485 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
489 if (iargctr < 5) { /* passed in register */
490 N_ST(REG_A0 + iargctr, doff + 4, RN, REG_SP);
492 } else { /* passed on stack */
493 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
502 /* Now move a0 and a1 to registers
512 N_LM(REG_A0, REG_A1, 0, REG_SP);
513 N_LM(REG_A2, REG_A3, 8, REG_SP);
515 M_AADD_IMM(2 * 8, REG_SP);
517 /* Finally load methodinfo argument */
519 disp = dseg_add_address(cd, m);
520 M_ALD(REG_ITMP2, REG_PV, disp);
521 M_AST(REG_ITMP2, REG_SP, 6 * 8);
523 /* Call builtin_verbosecall_enter */
525 disp = dseg_add_address(cd, builtin_verbosecall_enter);
526 M_ALD(REG_ITMP2, REG_PV, disp);
527 M_ASUB_IMM(96, REG_SP);
529 M_AADD_IMM(96, REG_SP);
531 /* restore argument registers */
533 off = (6 * 8) + (1 * 4);
535 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
536 M_ILD(abi_registers_integer_argument[i], REG_SP, off);
538 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
539 M_DLD(abi_registers_float_argument[i], REG_SP, off);
541 /* restore temporary registers for leaf methods */
543 if (jd->isleafmethod) {
544 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
545 M_ILD(abi_registers_integer_temporary[i], REG_SP, off);
547 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
548 M_DLD(abi_registers_float_temporary[i], REG_SP, off);
551 /* remove stackframe */
553 M_AADD_IMM(stackframesize, REG_SP);
555 /* mark trace code */
559 #endif /* !defined(NDEBUG) */
562 /* emit_verbosecall_exit *******************************************************
564 Generates the code for the call trace.
566 *******************************************************************************/
569 void emit_verbosecall_exit(jitdata *jd)
576 /* get required compiler data */
582 /* mark trace code */
586 M_ASUB_IMM(2 * 8, REG_SP);
588 N_STM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
589 M_DST(REG_FRESULT, REG_SP, 1 * 8);
591 if (IS_2_WORD_TYPE(m->parseddesc->returntype.type)) {
592 /* (REG_A0, REG_A1) == (REG_RESULT, REG_RESULT2), se no need to move */
594 M_INTMOVE(REG_RESULT, REG_A1);
598 disp = dseg_add_address(cd, m);
599 M_ALD(REG_A2, REG_PV, disp);
601 /* REG_FRESULT is REG_FA0, so no need to move */
602 M_FLTMOVE(REG_FRESULT, REG_FA1);
604 disp = dseg_add_address(cd, builtin_verbosecall_exit);
605 M_ALD(REG_ITMP1, REG_PV, disp);
606 M_ASUB_IMM(96, REG_SP);
608 M_AADD_IMM(96, REG_SP);
610 N_LM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
611 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
613 M_AADD_IMM(2 * 8, REG_SP);
615 /* mark trace code */
619 #endif /* !defined(NDEBUG) */
622 /* emit_load_high **************************************************************
624 Emits a possible load of the high 32-bits of an operand.
626 *******************************************************************************/
628 __PORTED__ s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
634 assert(src->type == TYPE_LNG);
636 /* get required compiler data */
640 if (IS_INMEMORY(src->flags)) {
643 disp = src->vv.regoff * 4;
645 M_ILD(tempreg, REG_SP, disp);
650 reg = GET_HIGH_REG(src->vv.regoff);
655 /* emit_load_low ***************************************************************
657 Emits a possible load of the low 32-bits of an operand.
659 *******************************************************************************/
661 __PORTED__ s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
667 assert(src->type == TYPE_LNG);
669 /* get required compiler data */
673 if (IS_INMEMORY(src->flags)) {
676 disp = src->vv.regoff * 4;
678 M_ILD(tempreg, REG_SP, disp + 4);
683 reg = GET_LOW_REG(src->vv.regoff);
688 s4 emit_load_s1_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
689 codegendata *cd = jd->cd;
690 s4 reg = emit_load_s1(jd, iptr, tempreg);
699 s4 emit_load_s2_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
700 codegendata *cd = jd->cd;
701 s4 reg = emit_load_s2(jd, iptr, tempreg);
710 s4 emit_load_s1_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
711 codegendata *cd = jd->cd;
712 s4 reg = emit_load_s1(jd, iptr, tempreg);
721 s4 emit_load_s2_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
722 codegendata *cd = jd->cd;
723 s4 reg = emit_load_s2(jd, iptr, tempreg);
732 s4 emit_alloc_dst_even_odd(jitdata *jd, instruction *iptr, s4 htmpreg, s4 ltmpreg, s4 breg) {
743 * (r12, r13) Illegal, because r13 is PV
744 * (r14, r15) Illegal, because r15 is SP
748 dst = VAROP(iptr->dst);
750 if (IS_INMEMORY(dst->flags)) {
751 if (! IS_REG_ITMP(ltmpreg)) {
752 M_INTMOVE(ltmpreg, breg);
754 if (! IS_REG_ITMP(htmpreg)) {
755 M_INTMOVE(htmpreg, breg);
757 return PACK_REGS(ltmpreg, htmpreg);
759 hr = GET_HIGH_REG(dst->vv.regoff);
760 lr = GET_LOW_REG(dst->vv.regoff);
761 if (((hr % 2) == 0) && lr == (hr + 1)) {
762 /* the result is already in a even-odd pair */
763 return dst->vv.regoff;
764 } else if (((hr % 2) == 0) && (hr < R12)) {
765 /* the high register is at a even position */
766 M_INTMOVE(hr + 1, breg);
767 return PACK_REGS(hr + 1, hr);
768 } else if (((lr % 2) == 1) && (lr < R12)) {
769 /* the low register is at a odd position */
770 M_INTMOVE(lr - 1, breg);
771 return PACK_REGS(lr, lr - 1);
773 /* no way to create an even-odd pair by 1 copy operation,
774 * Use the temporary register pair.
776 if (! IS_REG_ITMP(ltmpreg)) {
777 M_INTMOVE(ltmpreg, breg);
779 if (! IS_REG_ITMP(htmpreg)) {
780 M_INTMOVE(htmpreg, breg);
782 return PACK_REGS(ltmpreg, htmpreg);
787 void emit_restore_dst_even_odd(jitdata *jd, instruction *iptr, s4 htmpreg, s4 ltmpreg, s4 breg) {
793 dst = VAROP(iptr->dst);
795 if (IS_INMEMORY(dst->flags)) {
796 if (! IS_REG_ITMP(ltmpreg)) {
797 M_INTMOVE(breg, ltmpreg);
799 if (! IS_REG_ITMP(htmpreg)) {
800 M_INTMOVE(breg, htmpreg);
803 hr = GET_HIGH_REG(dst->vv.regoff);
804 lr = GET_LOW_REG(dst->vv.regoff);
805 if (((hr % 2) == 0) && lr == (hr + 1)) {
807 } else if (((hr % 2) == 0) && (hr < R12)) {
808 M_INTMOVE(breg, hr + 1);
809 } else if (((lr % 2) == 1) && (lr < R12)) {
810 M_INTMOVE(breg, lr - 1);
812 if (! IS_REG_ITMP(ltmpreg)) {
813 M_INTMOVE(breg, ltmpreg);
815 if (! IS_REG_ITMP(htmpreg)) {
816 M_INTMOVE(breg, htmpreg);
822 void emit_copy_dst(jitdata *jd, instruction *iptr, s4 dtmpreg) {
826 dst = VAROP(iptr->dst);
827 if (! IS_INMEMORY(dst->flags)) {
828 if (dst->vv.regoff != dtmpreg) {
829 if (IS_FLT_DBL_TYPE(dst->type)) {
830 M_FLTMOVE(dtmpreg, dst->vv.regoff);
831 } else if (IS_2_WORD_TYPE(dst->type)) {
832 M_LNGMOVE(dtmpreg, dst->vv.regoff);
834 M_INTMOVE(dtmpreg, dst->vv.regoff);
840 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 opt) {
842 s4 branchdisp = disp;
863 case BRANCH_UNCONDITIONAL:
867 vm_abort("emit_branch: unknown condition %d", condition);
871 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg) {
872 if (INSTRUCTION_MUST_CHECK(iptr)) {
874 M_BNE(SZ_BRC + SZ_ILL);
875 M_ILL(EXCEPTION_HARDWARE_ARITHMETIC);
879 /* emit_arrayindexoutofbounds_check ********************************************
881 Emit a ArrayIndexOutOfBoundsException check.
883 *******************************************************************************/
885 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
887 if (INSTRUCTION_MUST_CHECK(iptr)) {
889 * Do unsigned comparison to catch negative indexes.
891 N_CL(s2, OFFSET(java_arrayheader, size), RN, s1);
892 M_BLT(SZ_BRC + SZ_ILL);
893 M_ILL2(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
897 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1) {
898 if (INSTRUCTION_MUST_CHECK(iptr)) {
904 M_BGT(SZ_BRC + SZ_ILL);
907 M_BNE(SZ_BRC + SZ_ILL);
910 M_BLE(SZ_BRC + SZ_ILL);
913 vm_abort("emit_classcast_check: unknown condition %d", condition);
915 M_ILL2(s1, EXCEPTION_HARDWARE_CLASSCAST);
919 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg) {
920 if (INSTRUCTION_MUST_CHECK(iptr)) {
922 M_BNE(SZ_BRC + SZ_ILL);
923 M_ILL(EXCEPTION_HARDWARE_NULLPOINTER);
927 void emit_exception_check(codegendata *cd, instruction *iptr) {
928 if (INSTRUCTION_MUST_CHECK(iptr)) {
930 M_BNE(SZ_BRC + SZ_ILL);
931 M_ILL(EXCEPTION_HARDWARE_EXCEPTION);
935 void emit_restore_pv(codegendata *cd) {
940 disp = (s4) (cd->mcodeptr - cd->mcodebase);
941 M_ASUB_IMM32(disp, REG_ITMP1, REG_PV);
944 /* If the offset from the method start does not fit into an immediate
945 * value, we can't put it into the data segment!
948 /* Displacement from start of method to here */
950 offset = (s4) (cd->mcodeptr - cd->mcodebase);
952 if (N_VALID_IMM(-(offset + SZ_BASR))) {
953 /* Get program counter */
955 /* Substract displacement */
956 M_ASUB_IMM(offset + SZ_BASR, REG_PV);
958 /* Save program counter and jump over displacement in instruction flow */
959 N_BRAS(REG_PV, SZ_BRAS + SZ_LONG);
960 /* Place displacement here */
961 /* REG_PV points now exactly to this position */
962 N_LONG(offset + SZ_BRAS);
963 /* Substract *(REG_PV) from REG_PV */
964 N_S(REG_PV, 0, RN, REG_PV);
969 * These are local overrides for various environment variables in Emacs.
970 * Please do not remove this and leave it at the end of the file, where
971 * Emacs will automagically detect them.
972 * ---------------------------------------------------------------------
975 * indent-tabs-mode: t