1 /* src/vm/jit/s390/emit.c - s390 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 8304 2007-08-14 19:57:20Z pm $
34 #include "mm/memory.h"
35 #if defined(ENABLE_THREADS)
36 # include "threads/native/lock.h"
38 #include "vm/builtin.h"
39 #include "vm/exceptions.h"
40 #include "vm/global.h"
41 #include "vm/jit/abi.h"
42 #include "vm/jit/abi-asm.h"
43 #include "vm/jit/asmpart.h"
44 #include "vm/jit/codegen-common.h"
45 #include "vm/jit/emit-common.h"
46 #include "vm/jit/jit.h"
47 #include "vm/jit/patcher-common.h"
48 #include "vm/jit/replace.h"
49 #include "vm/jit/s390/codegen.h"
50 #include "vm/jit/s390/emit.h"
51 #include "vm/jit/s390/md-abi.h"
53 #include "vmcore/options.h"
55 /* emit_load *******************************************************************
57 Emits a possible load of an operand.
59 *******************************************************************************/
61 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
67 /* get required compiler data */
71 if (IS_INMEMORY(src->flags)) {
74 disp = src->vv.regoff;
76 if (IS_FLT_DBL_TYPE(src->type)) {
77 if (IS_2_WORD_TYPE(src->type))
78 M_DLD(tempreg, REG_SP, disp);
80 M_FLD(tempreg, REG_SP, disp);
83 if (IS_2_WORD_TYPE(src->type))
84 M_LLD(tempreg, REG_SP, disp);
86 M_ILD(tempreg, REG_SP, disp);
98 /* emit_store ******************************************************************
100 This function generates the code to store the result of an
101 operation back into a spilled pseudo-variable. If the
102 pseudo-variable has not been spilled in the first place, this
103 function will generate nothing.
105 *******************************************************************************/
107 void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
111 /* get required compiler data */
115 if (IS_INMEMORY(dst->flags)) {
118 if (IS_FLT_DBL_TYPE(dst->type)) {
119 if (IS_2_WORD_TYPE(dst->type))
120 M_DST(d, REG_SP, dst->vv.regoff);
122 M_FST(d, REG_SP, dst->vv.regoff);
125 if (IS_2_WORD_TYPE(dst->type))
126 M_LST(d, REG_SP, dst->vv.regoff);
128 M_IST(d, REG_SP, dst->vv.regoff);
134 /* emit_copy *******************************************************************
136 Generates a register/memory to register/memory copy.
138 *******************************************************************************/
140 void emit_copy(jitdata *jd, instruction *iptr)
147 /* get required compiler data */
151 /* get source and destination variables */
153 src = VAROP(iptr->s1);
154 dst = VAROP(iptr->dst);
156 if ((src->vv.regoff != dst->vv.regoff) ||
157 ((src->flags ^ dst->flags) & INMEMORY)) {
159 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
160 /* emit nothing, as the value won't be used anyway */
164 /* If one of the variables resides in memory, we can eliminate
165 the register move from/to the temporary register with the
166 order of getting the destination register and the load. */
168 if (IS_INMEMORY(src->flags)) {
169 if (IS_FLT_DBL_TYPE(dst->type)) {
170 d = codegen_reg_of_var(iptr->opc, dst, REG_FTMP1);
172 if (IS_2_WORD_TYPE(dst->type)) {
173 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
175 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP1);
178 s1 = emit_load(jd, iptr, src, d);
181 if (IS_FLT_DBL_TYPE(src->type)) {
182 s1 = emit_load(jd, iptr, src, REG_FTMP1);
184 if (IS_2_WORD_TYPE(src->type)) {
185 s1 = emit_load(jd, iptr, src, REG_ITMP12_PACKED);
187 s1 = emit_load(jd, iptr, src, REG_ITMP1);
190 d = codegen_reg_of_var(iptr->opc, dst, s1);
194 if (IS_FLT_DBL_TYPE(src->type)) {
197 if (IS_2_WORD_TYPE(src->type)) {
205 emit_store(jd, iptr, dst, d);
209 /* emit_trap *******************************************************************
211 Emit a trap instruction and return the original machine code.
213 *******************************************************************************/
215 uint32_t emit_trap(codegendata *cd)
219 /* Get machine code which is patched back in later. The
220 trap is 2 bytes long. */
222 mcode = *((u2 *) cd->mcodeptr);
224 M_ILL(EXCEPTION_HARDWARE_PATCHER);
230 /* emit_verbosecall_enter ******************************************************
232 Generates the code for the call trace.
234 *******************************************************************************/
237 #include "vm/jit/trace.h"
238 void emit_verbosecall_enter(jitdata *jd)
249 /* mark trace code */
253 /* allocate stack frame */
255 stackframesize = 96 + (ARG_CNT * 8);
256 M_ASUB_IMM(stackframesize, REG_SP);
258 /* store argument registers in array */
262 for (i = 0; i < INT_ARG_CNT; ++i, off += 8) {
263 M_IST(abi_registers_integer_argument[i], REG_SP, off + 4);
264 /* high bytes are sign extension */
265 M_SRA_IMM(31, abi_registers_integer_argument[i]);
266 M_IST(abi_registers_integer_argument[i], REG_SP, off);
269 for (i = 0; i < FLT_ARG_CNT; ++i, off += 8) {
270 M_DST(abi_registers_float_argument[i], REG_SP, off);
273 /* load arguments for trace_java_call_enter */
276 disp = dseg_add_address(cd, m);
277 M_ALD_DSEG(REG_A0, disp);
278 /* pointer to argument registers array */
279 M_LDA(REG_A1, REG_SP, 96);
280 /* pointer to on stack arguments */
281 M_LDA(REG_A2, REG_SP, stackframesize + (cd->stackframesize * 8));
283 /* call trace_java_call_enter */
285 disp = dseg_add_functionptr(cd, trace_java_call_enter);
286 M_ALD_DSEG(REG_ITMP3, disp);
289 /* restore argument registers */
293 for (i = 0; i < INT_ARG_CNT; ++i, off += 8) {
294 M_ILD(abi_registers_integer_argument[i], REG_SP, off + 4);
297 for (i = 0; i < FLT_ARG_CNT; ++i, off += 8) {
298 M_DLD(abi_registers_float_argument[i], REG_SP, off);
301 /* remove stack frame */
303 M_AADD_IMM(stackframesize, REG_SP);
305 /* mark trace code */
314 s4 stackframesize, off, foff, aoff, doff, t, iargctr, fargctr, disp;
316 /* get required compiler data */
323 /* mark trace code */
328 (6 * 8) + /* s8 on stack parameters x 6 */
329 (1 * 4) + /* methodinfo on stack parameter */
334 M_ASUB_IMM(stackframesize, REG_SP); /* allocate stackframe */
336 /* save argument registers */
338 off = (6 * 8) + (1 * 4);
340 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
341 M_IST(abi_registers_integer_argument[i], REG_SP, off);
343 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
344 M_DST(abi_registers_float_argument[i], REG_SP, off);
346 /* save temporary registers for leaf methods */
348 if (jd->isleafmethod) {
349 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
350 M_LST(abi_registers_integer_temporary[i], REG_SP, off);
352 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
353 M_DST(abi_registers_float_temporary[i], REG_SP, off);
356 /* Load arguments to new locations */
358 /* First move all arguments to stack
363 * (s8) a1 \ Auxilliary stack frame
368 M_ASUB_IMM(2 * 8, REG_SP);
370 /* offset to where first integer arg is saved on stack */
371 off = (2 * 8) + (6 * 8) + (1 * 4);
372 /* offset to where first float arg is saved on stack */
373 foff = off + (INT_ARG_CNT * 8);
374 /* offset to where first argument is passed on stack */
375 aoff = (2 * 8) + stackframesize + (cd->stackframesize * 8);
376 /* offset to destination on stack */
379 iargctr = fargctr = 0;
381 ICONST(REG_ITMP1, 0);
383 for (i = 0; i < md->paramcount && i < 8; i++) {
384 t = md->paramtypes[i].type;
386 M_IST(REG_ITMP1, REG_SP, doff);
387 M_IST(REG_ITMP1, REG_SP, doff + 4);
389 if (IS_FLT_DBL_TYPE(t)) {
390 if (fargctr < 2) { /* passed in register */
391 N_STD(abi_registers_float_argument[fargctr], doff, RN, REG_SP);
393 } else { /* passed on stack */
395 if (IS_2_WORD_TYPE(t)) {
396 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
398 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
401 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
405 if (IS_2_WORD_TYPE(t)) {
406 if (iargctr < 4) { /* passed in 2 registers */
407 N_STM(REG_A0 + iargctr, REG_A0 + iargctr + 1, doff, REG_SP);
409 } else { /* passed on stack */
410 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
414 if (iargctr < 5) { /* passed in register */
415 N_ST(REG_A0 + iargctr, doff + 4, RN, REG_SP);
417 } else { /* passed on stack */
418 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
427 /* Now move a0 and a1 to registers
437 N_LM(REG_A0, REG_A1, 0, REG_SP);
438 N_LM(REG_A2, REG_A3, 8, REG_SP);
440 M_AADD_IMM(2 * 8, REG_SP);
442 /* Finally load methodinfo argument */
444 disp = dseg_add_address(cd, m);
445 M_ALD_DSEG(REG_ITMP2, disp);
446 M_AST(REG_ITMP2, REG_SP, 6 * 8);
448 /* Call builtin_verbosecall_enter */
450 disp = dseg_add_address(cd, builtin_verbosecall_enter);
451 M_ALD_DSEG(REG_ITMP2, disp);
452 M_ASUB_IMM(96, REG_SP);
454 M_AADD_IMM(96, REG_SP);
456 /* restore argument registers */
458 off = (6 * 8) + (1 * 4);
460 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
461 M_ILD(abi_registers_integer_argument[i], REG_SP, off);
463 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
464 M_DLD(abi_registers_float_argument[i], REG_SP, off);
466 /* restore temporary registers for leaf methods */
468 if (jd->isleafmethod) {
469 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
470 M_ILD(abi_registers_integer_temporary[i], REG_SP, off);
472 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
473 M_DLD(abi_registers_float_temporary[i], REG_SP, off);
476 /* remove stackframe */
478 M_AADD_IMM(stackframesize, REG_SP);
480 /* mark trace code */
485 #endif /* !defined(NDEBUG) */
488 /* emit_verbosecall_exit *******************************************************
490 Generates the code for the call trace.
492 *******************************************************************************/
495 void emit_verbosecall_exit(jitdata *jd)
506 /* mark trace code */
510 /* allocate stackframe */
512 stackframesize = 96 + (3 * 8);
513 M_ASUB_IMM(stackframesize, REG_SP);
515 /* store return values in array and sign extend them */
517 M_IST(REG_RESULT, REG_SP, 96 + (0 * 8) + 4);
518 M_SRA_IMM(31, REG_RESULT);
519 M_IST(REG_RESULT, REG_SP, 96 + (0 * 8));
521 M_IST(REG_RESULT2, REG_SP, 96 + (1 * 8) + 4);
522 M_SRA_IMM(31, REG_RESULT2);
523 M_IST(REG_RESULT2, REG_SP, 96 + (1 * 8));
525 M_DST(REG_FRESULT, REG_SP, 96 + (2 * 8));
527 /* call trace_java_call_exit */
529 disp = dseg_add_address(cd, m);
530 M_ALD_DSEG(REG_A0, disp);
531 M_LDA(REG_A1, REG_SP, 96);
532 disp = dseg_add_functionptr(cd, trace_java_call_exit);
533 M_ALD_DSEG(REG_ITMP3, disp);
536 /* restore return values */
538 M_ILD(REG_RESULT, REG_SP, 96 + (0 * 8) + 4);
539 M_ILD(REG_RESULT2, REG_SP, 96 + (1 * 8) + 4);
540 M_DLD(REG_FRESULT, REG_SP, 96 + (2 * 8));
542 /* remove stackframe */
544 M_AADD_IMM(stackframesize, REG_SP);
546 /* mark trace code */
557 /* get required compiler data */
563 /* mark trace code */
567 M_ASUB_IMM(2 * 8, REG_SP);
569 N_STM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
570 M_DST(REG_FRESULT, REG_SP, 1 * 8);
572 if (IS_2_WORD_TYPE(m->parseddesc->returntype.type)) {
573 /* (REG_A0, REG_A1) == (REG_RESULT, REG_RESULT2), se no need to move */
575 M_INTMOVE(REG_RESULT, REG_A1);
579 disp = dseg_add_address(cd, m);
580 M_ALD_DSEG(REG_A2, disp);
582 /* REG_FRESULT is REG_FA0, so no need to move */
583 M_FLTMOVE(REG_FRESULT, REG_FA1);
585 disp = dseg_add_address(cd, builtin_verbosecall_exit);
586 M_ALD_DSEG(REG_ITMP1, disp);
587 M_ASUB_IMM(96, REG_SP);
589 M_AADD_IMM(96, REG_SP);
591 N_LM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
592 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
594 M_AADD_IMM(2 * 8, REG_SP);
596 /* mark trace code */
601 #endif /* !defined(NDEBUG) */
604 /* emit_load_high **************************************************************
606 Emits a possible load of the high 32-bits of an operand.
608 *******************************************************************************/
610 s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
616 assert(src->type == TYPE_LNG);
618 /* get required compiler data */
622 if (IS_INMEMORY(src->flags)) {
625 disp = src->vv.regoff;
627 M_ILD(tempreg, REG_SP, disp);
632 reg = GET_HIGH_REG(src->vv.regoff);
637 /* emit_load_low ***************************************************************
639 Emits a possible load of the low 32-bits of an operand.
641 *******************************************************************************/
643 s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
649 assert(src->type == TYPE_LNG);
651 /* get required compiler data */
655 if (IS_INMEMORY(src->flags)) {
658 disp = src->vv.regoff;
660 M_ILD(tempreg, REG_SP, disp + 4);
665 reg = GET_LOW_REG(src->vv.regoff);
670 s4 emit_load_s1_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
671 codegendata *cd = jd->cd;
672 s4 reg = emit_load_s1(jd, iptr, tempreg);
681 s4 emit_load_s2_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
682 codegendata *cd = jd->cd;
683 s4 reg = emit_load_s2(jd, iptr, tempreg);
685 if (IS_FLT_DBL_TYPE(VAROP(iptr->sx.s23.s2)->type)) {
686 M_FMOV(reg, tempreg);
696 s4 emit_load_s1_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
697 codegendata *cd = jd->cd;
698 s4 reg = emit_load_s1(jd, iptr, tempreg);
700 if (IS_FLT_DBL_TYPE(VAROP(iptr->s1)->type)) {
701 M_FMOV(reg, tempreg);
711 s4 emit_load_s2_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
712 codegendata *cd = jd->cd;
713 s4 reg = emit_load_s2(jd, iptr, tempreg);
715 if (IS_FLT_DBL_TYPE(VAROP(iptr->sx.s23.s2)->type)) {
716 M_FMOV(reg, tempreg);
726 s4 emit_alloc_dst_even_odd(jitdata *jd, instruction *iptr, s4 htmpreg, s4 ltmpreg, s4 breg) {
737 * (r12, r13) Illegal, because r13 is PV
738 * (r14, r15) Illegal, because r15 is SP
742 dst = VAROP(iptr->dst);
744 if (IS_INMEMORY(dst->flags)) {
745 if (! IS_REG_ITMP(ltmpreg)) {
746 M_INTMOVE(ltmpreg, breg);
748 if (! IS_REG_ITMP(htmpreg)) {
749 M_INTMOVE(htmpreg, breg);
751 return PACK_REGS(ltmpreg, htmpreg);
753 hr = GET_HIGH_REG(dst->vv.regoff);
754 lr = GET_LOW_REG(dst->vv.regoff);
755 if (((hr % 2) == 0) && lr == (hr + 1)) {
756 /* the result is already in a even-odd pair */
757 return dst->vv.regoff;
758 } else if (((hr % 2) == 0) && (hr < R12)) {
759 /* the high register is at a even position */
760 M_INTMOVE(hr + 1, breg);
761 return PACK_REGS(hr + 1, hr);
762 } else if (((lr % 2) == 1) && (lr < R12)) {
763 /* the low register is at a odd position */
764 M_INTMOVE(lr - 1, breg);
765 return PACK_REGS(lr, lr - 1);
767 /* no way to create an even-odd pair by 1 copy operation,
768 * Use the temporary register pair.
770 if (! IS_REG_ITMP(ltmpreg)) {
771 M_INTMOVE(ltmpreg, breg);
773 if (! IS_REG_ITMP(htmpreg)) {
774 M_INTMOVE(htmpreg, breg);
776 return PACK_REGS(ltmpreg, htmpreg);
781 void emit_restore_dst_even_odd(jitdata *jd, instruction *iptr, s4 htmpreg, s4 ltmpreg, s4 breg) {
787 dst = VAROP(iptr->dst);
789 if (IS_INMEMORY(dst->flags)) {
790 if (! IS_REG_ITMP(ltmpreg)) {
791 M_INTMOVE(breg, ltmpreg);
793 if (! IS_REG_ITMP(htmpreg)) {
794 M_INTMOVE(breg, htmpreg);
797 hr = GET_HIGH_REG(dst->vv.regoff);
798 lr = GET_LOW_REG(dst->vv.regoff);
799 if (((hr % 2) == 0) && lr == (hr + 1)) {
801 } else if (((hr % 2) == 0) && (hr < R12)) {
802 M_INTMOVE(breg, hr + 1);
803 } else if (((lr % 2) == 1) && (lr < R12)) {
804 M_INTMOVE(breg, lr - 1);
806 if (! IS_REG_ITMP(ltmpreg)) {
807 M_INTMOVE(breg, ltmpreg);
809 if (! IS_REG_ITMP(htmpreg)) {
810 M_INTMOVE(breg, htmpreg);
816 void emit_copy_dst(jitdata *jd, instruction *iptr, s4 dtmpreg) {
820 dst = VAROP(iptr->dst);
821 if (! IS_INMEMORY(dst->flags)) {
822 if (dst->vv.regoff != dtmpreg) {
823 if (IS_FLT_DBL_TYPE(dst->type)) {
824 M_FLTMOVE(dtmpreg, dst->vv.regoff);
825 } else if (IS_2_WORD_TYPE(dst->type)) {
826 M_LNGMOVE(dtmpreg, dst->vv.regoff);
828 M_INTMOVE(dtmpreg, dst->vv.regoff);
834 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 opt) {
836 s4 branchdisp = disp;
840 if (N_VALID_BRANCH(branchdisp)) {
842 /* valid displacement */
863 case BRANCH_UNCONDITIONAL:
867 vm_abort("emit_branch: unknown condition %d", condition);
871 /* If LONGBRANCHES is not set, the flag and the error flag */
873 if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
874 cd->flags |= (CODEGENDATA_FLAG_ERROR |
875 CODEGENDATA_FLAG_LONGBRANCHES);
878 /* If error flag is set, do nothing. The method has to be recompiled. */
880 if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd) && CODEGENDATA_HAS_FLAG_ERROR(cd)) {
884 /* Patch the displacement to branch over the actual branch manually
885 * to not get yet more nops.
888 branchmpc = cd->mcodeptr - cd->mcodebase;
910 case BRANCH_UNCONDITIONAL:
911 /* fall through, no displacement to patch */
915 vm_abort("emit_branch: unknown condition %d", condition);
918 /* The actual long branch */
920 disp = dseg_add_s4(cd, branchmpc + disp - N_PV_OFFSET);
921 M_ILD_DSEG(REG_ITMP3, disp);
922 M_AADD(REG_PV, REG_ITMP3);
923 M_JMP(RN, REG_ITMP3);
925 /* Patch back the displacement */
928 *(u4 *)ref |= (u4)((cd->mcodeptr - ref) / 2);
933 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg) {
934 if (INSTRUCTION_MUST_CHECK(iptr)) {
936 M_BNE(SZ_BRC + SZ_ILL);
937 M_ILL(EXCEPTION_HARDWARE_ARITHMETIC);
941 /* emit_arrayindexoutofbounds_check ********************************************
943 Emit a ArrayIndexOutOfBoundsException check.
945 *******************************************************************************/
947 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
949 if (INSTRUCTION_MUST_CHECK(iptr)) {
951 * Do unsigned comparison to catch negative indexes.
953 N_CL(s2, OFFSET(java_arrayheader, size), RN, s1);
954 M_BLT(SZ_BRC + SZ_ILL);
955 M_ILL2(s2, EXCEPTION_HARDWARE_ARRAYINDEXOUTOFBOUNDS);
959 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1) {
960 if (INSTRUCTION_MUST_CHECK(iptr)) {
966 M_BGT(SZ_BRC + SZ_ILL);
969 M_BNE(SZ_BRC + SZ_ILL);
972 M_BLE(SZ_BRC + SZ_ILL);
975 vm_abort("emit_classcast_check: unknown condition %d", condition);
977 M_ILL2(s1, EXCEPTION_HARDWARE_CLASSCAST);
981 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg) {
982 if (INSTRUCTION_MUST_CHECK(iptr)) {
984 M_BNE(SZ_BRC + SZ_ILL);
985 M_ILL(EXCEPTION_HARDWARE_NULLPOINTER);
989 void emit_exception_check(codegendata *cd, instruction *iptr) {
990 if (INSTRUCTION_MUST_CHECK(iptr)) {
992 M_BNE(SZ_BRC + SZ_ILL);
993 M_ILL(EXCEPTION_HARDWARE_EXCEPTION);
997 void emit_restore_pv(codegendata *cd) {
998 s4 offset, offset_imm;
1002 disp = (s4) (cd->mcodeptr - cd->mcodebase);
1003 M_ASUB_IMM32(disp, REG_ITMP1, REG_PV);
1006 /* If the offset from the method start does not fit into an immediate
1007 * value, we can't put it into the data segment!
1010 /* Displacement from start of method to here */
1012 offset = (s4) (cd->mcodeptr - cd->mcodebase);
1013 offset_imm = -offset - SZ_BASR + N_PV_OFFSET;
1015 if (N_VALID_IMM(offset_imm)) {
1016 /* Get program counter */
1018 /* Substract displacement */
1019 M_AADD_IMM(offset_imm, REG_PV);
1021 /* Save program counter and jump over displacement in instruction flow */
1022 N_BRAS(REG_PV, SZ_BRAS + SZ_LONG);
1023 /* Place displacement here */
1024 /* REG_PV points now exactly to this position */
1025 N_LONG(-offset - SZ_BRAS + N_PV_OFFSET);
1026 /* Substract *(REG_PV) from REG_PV */
1027 N_A(REG_PV, 0, RN, REG_PV);
1032 * These are local overrides for various environment variables in Emacs.
1033 * Please do not remove this and leave it at the end of the file, where
1034 * Emacs will automagically detect them.
1035 * ---------------------------------------------------------------------
1038 * indent-tabs-mode: t