1 /* src/vm/jit/s390/emit.c - s390 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: emit.c 7766 2007-04-19 13:24:48Z michi $
38 #include "vm/jit/s390/codegen.h"
39 #include "vm/jit/s390/emit.h"
41 #if defined(ENABLE_THREADS)
42 # include "threads/native/lock.h"
45 #include "vm/builtin.h"
46 #include "vm/jit/abi-asm.h"
47 #include "vm/jit/asmpart.h"
48 #include "vm/jit/codegen-common.h"
49 #include "vm/jit/emit-common.h"
50 #include "vm/jit/jit.h"
51 #include "vm/jit/replace.h"
52 #include "vm/global.h"
53 #include "mm/memory.h"
57 /* emit_load *******************************************************************
59 Emits a possible load of an operand.
61 *******************************************************************************/
63 __PORTED__ s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
69 /* get required compiler data */
73 if (IS_INMEMORY(src->flags)) {
76 disp = src->vv.regoff * 4;
78 if (IS_FLT_DBL_TYPE(src->type)) {
79 if (IS_2_WORD_TYPE(src->type))
80 M_DLD(tempreg, REG_SP, disp);
82 M_FLD(tempreg, REG_SP, disp);
85 if (IS_2_WORD_TYPE(src->type))
86 M_LLD(tempreg, REG_SP, disp);
88 M_ILD(tempreg, REG_SP, disp);
100 /* emit_store ******************************************************************
102 This function generates the code to store the result of an
103 operation back into a spilled pseudo-variable. If the
104 pseudo-variable has not been spilled in the first place, this
105 function will generate nothing.
107 *******************************************************************************/
109 __PORTED__ inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
113 /* get required compiler data */
117 if (IS_INMEMORY(dst->flags)) {
120 if (IS_FLT_DBL_TYPE(dst->type)) {
121 if (IS_2_WORD_TYPE(dst->type))
122 M_DST(d, REG_SP, dst->vv.regoff * 4);
124 M_FST(d, REG_SP, dst->vv.regoff * 4);
127 if (IS_2_WORD_TYPE(dst->type))
128 M_LST(d, REG_SP, dst->vv.regoff * 4);
130 M_IST(d, REG_SP, dst->vv.regoff * 4);
136 /* emit_copy *******************************************************************
138 Generates a register/memory to register/memory copy.
140 *******************************************************************************/
142 __PORTED__ void emit_copy(jitdata *jd, instruction *iptr)
149 /* get required compiler data */
153 /* get source and destination variables */
155 src = VAROP(iptr->s1);
156 dst = VAROP(iptr->dst);
158 if ((src->vv.regoff != dst->vv.regoff) ||
159 ((src->flags ^ dst->flags) & INMEMORY)) {
161 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
162 /* emit nothing, as the value won't be used anyway */
166 /* If one of the variables resides in memory, we can eliminate
167 the register move from/to the temporary register with the
168 order of getting the destination register and the load. */
170 if (IS_INMEMORY(src->flags)) {
171 if (IS_FLT_DBL_TYPE(dst->type))
172 d = codegen_reg_of_var(iptr->opc, dst, REG_FTMP1);
174 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP1);
175 s1 = emit_load(jd, iptr, src, d);
178 if (IS_FLT_DBL_TYPE(src->type))
179 s1 = emit_load(jd, iptr, src, REG_FTMP1);
181 s1 = emit_load(jd, iptr, src, REG_ITMP1);
182 d = codegen_reg_of_var(iptr->opc, dst, s1);
186 if (IS_FLT_DBL_TYPE(src->type))
192 emit_store(jd, iptr, dst, d);
197 void emit_cmovxx(codegendata *cd, instruction *iptr, s4 s, s4 d)
200 switch (iptr->flags.fields.condition) {
224 /* emit_exception_stubs ********************************************************
226 Generates the code for the exception stubs.
228 *******************************************************************************/
230 __PORTED__ void emit_exception_stubs(jitdata *jd)
240 /* get required compiler data */
245 /* generate exception stubs */
249 for (er = cd->exceptionrefs; er != NULL; er = er->next) {
250 /* back-patch the branch to this exception code */
252 branchmpc = er->branchpos;
253 targetmpc = cd->mcodeptr - cd->mcodebase;
255 md_codegen_patch_branch(cd, branchmpc, targetmpc);
259 /* move index register into REG_ITMP1 */
261 /* Check if the exception is an
262 ArrayIndexOutOfBoundsException. If so, move index register
266 M_MOV(er->reg, rd->argintregs[4]);
268 /* calcuate exception address */
270 if (N_VALID_DISP(er->branchpos - 4)) {
271 M_LDA(rd->argintregs[3], REG_PV, er->branchpos - 4);
273 M_INTMOVE(REG_PV, rd->argintregs[3]);
274 M_AADD_IMM(er->branchpos - 4, rd->argintregs[3]);
277 /* move function to call into REG_ITMP! */
279 disp = dseg_add_functionptr(cd, er->function);
280 M_ALD(REG_ITMP1, REG_PV, disp);
282 if (targetdisp == 0) {
283 targetdisp = (cd->mcodeptr) - (cd->mcodebase);
285 M_MOV(REG_PV, rd->argintregs[0]);
286 M_MOV(REG_SP, rd->argintregs[1]);
288 M_ALD(rd->argintregs[2],
289 REG_SP, cd->stackframesize * 4 - SIZEOF_VOID_P);
291 M_ASUB_IMM((2 * 4) + 96, REG_SP);
293 M_AST(rd->argintregs[3], REG_SP, (0 * 4) + 96); /* store XPC */
295 M_JSR(REG_RA, REG_ITMP1);
297 M_MOV(REG_RESULT, REG_ITMP1_XPTR);
299 M_ALD(REG_ITMP2_XPC, REG_SP, (0 * 4) + 96);
300 M_AADD_IMM((2 * 4) + 96, REG_SP);
302 disp = dseg_add_functionptr(cd, asm_handle_exception);
303 M_ALD(REG_ITMP3, REG_PV, disp);
304 M_JMP(RN, REG_ITMP3);
307 disp = ((cd->mcodebase) + targetdisp) -
317 /* emit_patcher_stubs **********************************************************
319 Generates the code for the patcher stubs.
321 *******************************************************************************/
323 __PORTED__ void emit_patcher_stubs(jitdata *jd)
334 /* get required compiler data */
338 /* generate code patching stub call code */
342 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
343 /* check code segment size */
347 /* Get machine code which is patched back in later. The
348 call is 1 instruction word long. */
350 tmpmcodeptr = (u1 *) (cd->mcodebase + pref->branchpos);
352 mcode = *((u4 *) tmpmcodeptr);
354 /* Patch in the call to call the following code (done at
357 savedmcodeptr = cd->mcodeptr; /* save current mcodeptr */
358 cd->mcodeptr = tmpmcodeptr; /* set mcodeptr to patch position */
360 disp = (savedmcodeptr) - (tmpmcodeptr);
361 M_BSR(REG_ITMP3, disp);
363 cd->mcodeptr = savedmcodeptr; /* restore the current mcodeptr */
365 /* create stack frame */
367 M_ASUB_IMM(6 * 4, REG_SP);
369 /* move return address onto stack */
371 M_AST(REG_ITMP3, REG_SP, 5 * 4);
373 /* move pointer to java_objectheader onto stack */
375 #if defined(ENABLE_THREADS)
376 /* create a virtual java_objectheader */
378 (void) dseg_add_unique_address(cd, NULL); /* flcword */
379 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
380 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
382 M_LDA(REG_ITMP3, REG_PV, disp);
383 M_AST(REG_ITMP3, REG_SP, 4 * 4);
388 /* move machine code onto stack */
390 disp = dseg_add_s4(cd, mcode);
391 M_ILD(REG_ITMP3, REG_PV, disp);
392 M_IST(REG_ITMP3, REG_SP, 3 * 4);
394 /* move class/method/field reference onto stack */
396 disp = dseg_add_address(cd, pref->ref);
397 M_ALD(REG_ITMP3, REG_PV, disp);
398 M_AST(REG_ITMP3, REG_SP, 2 * 4);
400 /* move data segment displacement onto stack */
402 disp = dseg_add_s4(cd, pref->disp);
403 M_ILD(REG_ITMP3, REG_PV, disp);
404 M_IST(REG_ITMP3, REG_SP, 1 * 4);
406 /* move patcher function pointer onto stack */
408 disp = dseg_add_functionptr(cd, pref->patcher);
409 M_ALD(REG_ITMP3, REG_PV, disp);
410 M_AST(REG_ITMP3, REG_SP, 0 * 4);
412 if (targetdisp == 0) {
413 targetdisp = (cd->mcodeptr) - (cd->mcodebase);
415 disp = dseg_add_functionptr(cd, asm_patcher_wrapper);
416 M_ALD(REG_ITMP3, REG_PV, disp);
417 M_JMP(RN, REG_ITMP3);
420 disp = ((cd->mcodebase) + targetdisp) -
429 /* emit_replacement_stubs ******************************************************
431 Generates the code for the replacement stubs.
433 *******************************************************************************/
435 void emit_replacement_stubs(jitdata *jd)
444 /* get required compiler data */
449 rplp = code->rplpoints;
451 for (i = 0; i < code->rplpointcount; ++i, ++rplp) {
452 /* check code segment size */
456 /* note start of stub code */
458 rplp->outcode = (u1 *) (ptrint) (cd->mcodeptr - cd->mcodebase);
460 /* make machine code for patching */
462 disp = (ptrint) (rplp->outcode - rplp->pc) - 5;
464 rplp->mcode = 0xe9 | ((u8) disp << 8);
466 /* push address of `rplpoint` struct */
468 M_MOV_IMM(rplp, REG_ITMP3);
471 /* jump to replacement function */
473 M_MOV_IMM(asm_replacement_out, REG_ITMP3);
480 /* emit_verbosecall_enter ******************************************************
482 Generates the code for the call trace.
484 *******************************************************************************/
487 void emit_verbosecall_enter(jitdata *jd)
495 s4 stackframesize, off, foff, aoff, doff, t, iargctr, fargctr, disp;
497 /* get required compiler data */
505 /* mark trace code */
510 (6 * 8) + /* s8 on stack parameters x 6 */
511 (1 * 4) + /* methodinfo on stack parameter */
516 M_ASUB_IMM(stackframesize, REG_SP); /* allocate stackframe */
518 /* save argument registers */
520 off = (6 * 8) + (1 * 4);
522 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
523 M_IST(rd->argintregs[i], REG_SP, off);
525 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
526 M_DST(rd->argfltregs[i], REG_SP, off);
528 /* save temporary registers for leaf methods */
530 if (jd->isleafmethod) {
531 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
532 M_LST(rd->tmpintregs[i], REG_SP, off);
534 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
535 M_DST(rd->tmpfltregs[i], REG_SP, off);
538 /* Load arguments to new locations */
540 /* First move all arguments to stack
545 * (s8) a1 \ Auxilliary stack frame
550 M_ASUB_IMM(2 * 8, REG_SP);
552 /* offset to where first integer arg is saved on stack */
553 off = (2 * 8) + (6 * 8) + (1 * 4);
554 /* offset to where first float arg is saved on stack */
555 foff = off + (INT_ARG_CNT * 8);
556 /* offset to where first argument is passed on stack */
557 aoff = (2 * 8) + stackframesize + (cd->stackframesize * 4);
558 /* offset to destination on stack */
561 iargctr = fargctr = 0;
563 ICONST(REG_ITMP1, 0);
565 for (i = 0; i < md->paramcount && i < 8; i++) {
566 t = md->paramtypes[i].type;
568 M_IST(REG_ITMP1, REG_SP, doff);
569 M_IST(REG_ITMP1, REG_SP, doff + 4);
571 if (IS_FLT_DBL_TYPE(t)) {
572 if (fargctr < 2) { /* passed in register */
573 N_STD(REG_FA0 + fargctr, doff, RN, REG_SP);
575 } else { /* passed on stack */
576 if (IS_2_WORD_TYPE(t)) {
577 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
580 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
585 if (IS_2_WORD_TYPE(t)) {
586 if (iargctr < 4) { /* passed in 2 registers */
587 N_STM(REG_A0 + iargctr, REG_A0 + iargctr + 1, doff, REG_SP);
589 } else { /* passed on stack */
590 N_MVC(doff, 8, REG_SP, aoff, REG_SP);
594 if (iargctr < 5) { /* passed in register */
595 N_ST(REG_A0 + iargctr, doff + 4, RN, REG_SP);
597 } else { /* passed on stack */
598 N_MVC(doff + 4, 4, REG_SP, aoff, REG_SP);
607 /* Now move a0 and a1 to registers
617 N_LM(REG_A0, REG_A1, 0, REG_SP);
618 N_LM(REG_A2, REG_A3, 8, REG_SP);
620 M_AADD_IMM(2 * 8, REG_SP);
622 /* Finally load methodinfo argument */
624 disp = dseg_add_address(cd, m);
625 M_ALD(REG_ITMP2, REG_PV, disp);
626 M_AST(REG_ITMP2, REG_SP, 6 * 8);
628 /* Call builtin_verbosecall_enter */
630 disp = dseg_add_address(cd, builtin_verbosecall_enter);
631 M_ALD(REG_ITMP2, REG_PV, disp);
632 M_ASUB_IMM(96, REG_SP);
634 M_AADD_IMM(96, REG_SP);
636 /* restore argument registers */
638 off = (6 * 8) + (1 * 4);
640 for (i = 0; i < INT_ARG_CNT; i++, off += 8)
641 M_ILD(rd->argintregs[i], REG_SP, off);
643 for (i = 0; i < FLT_ARG_CNT; i++, off += 8)
644 M_DLD(rd->argfltregs[i], REG_SP, off);
646 /* restore temporary registers for leaf methods */
648 if (jd->isleafmethod) {
649 for (i = 0; i < INT_TMP_CNT; i++, off += 8)
650 M_ILD(rd->tmpintregs[i], REG_SP, off);
652 for (i = 0; i < FLT_TMP_CNT; i++, off += 8)
653 M_DLD(rd->tmpfltregs[i], REG_SP, off);
656 /* remove stackframe */
658 M_AADD_IMM(stackframesize, REG_SP);
660 /* mark trace code */
664 #endif /* !defined(NDEBUG) */
667 /* emit_verbosecall_exit *******************************************************
669 Generates the code for the call trace.
671 *******************************************************************************/
674 void emit_verbosecall_exit(jitdata *jd)
681 /* get required compiler data */
687 /* mark trace code */
691 M_ASUB_IMM(2 * 8, REG_SP);
693 N_STM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
694 M_DST(REG_FRESULT, REG_SP, 1 * 8);
696 if (IS_2_WORD_TYPE(m->parseddesc->returntype.type)) {
697 /* (REG_A0, REG_A1) == (REG_RESULT, REG_RESULT2), se no need to move */
699 M_INTMOVE(REG_RESULT, REG_A1);
703 disp = dseg_add_address(cd, m);
704 M_ALD(REG_A2, REG_PV, disp);
706 /* REG_FRESULT is REG_FA0, so no need to move */
707 M_FLTMOVE(REG_FRESULT, REG_FA1);
709 disp = dseg_add_address(cd, builtin_verbosecall_exit);
710 M_ALD(REG_ITMP1, REG_PV, disp);
711 M_ASUB_IMM(96, REG_SP);
713 M_AADD_IMM(96, REG_SP);
715 N_LM(REG_RESULT, REG_RESULT2, 0 * 8, REG_SP);
716 M_DLD(REG_FRESULT, REG_SP, 1 * 8);
718 M_AADD_IMM(2 * 8, REG_SP);
720 /* mark trace code */
724 #endif /* !defined(NDEBUG) */
727 /* code generation functions **************************************************/
729 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
731 if ((basereg == REG_SP) || (basereg == R12)) {
733 emit_address_byte(0, dreg, REG_SP);
734 emit_address_byte(0, REG_SP, REG_SP);
736 } else if (IS_IMM8(disp)) {
737 emit_address_byte(1, dreg, REG_SP);
738 emit_address_byte(0, REG_SP, REG_SP);
742 emit_address_byte(2, dreg, REG_SP);
743 emit_address_byte(0, REG_SP, REG_SP);
747 } else if ((disp) == 0 && (basereg) != RBP && (basereg) != R13) {
748 emit_address_byte(0,(dreg),(basereg));
750 } else if ((basereg) == RIP) {
751 emit_address_byte(0, dreg, RBP);
756 emit_address_byte(1, dreg, basereg);
760 emit_address_byte(2, dreg, basereg);
767 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
769 if ((basereg == REG_SP) || (basereg == R12)) {
770 emit_address_byte(2, dreg, REG_SP);
771 emit_address_byte(0, REG_SP, REG_SP);
775 emit_address_byte(2, dreg, basereg);
781 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
784 emit_address_byte(0, reg, 4);
785 emit_address_byte(scale, indexreg, 5);
788 else if ((disp == 0) && (basereg != RBP) && (basereg != R13)) {
789 emit_address_byte(0, reg, 4);
790 emit_address_byte(scale, indexreg, basereg);
792 else if (IS_IMM8(disp)) {
793 emit_address_byte(1, reg, 4);
794 emit_address_byte(scale, indexreg, basereg);
798 emit_address_byte(2, reg, 4);
799 emit_address_byte(scale, indexreg, basereg);
805 void emit_ishift(jitdata *jd, s4 shift_op, instruction *iptr)
808 varinfo *v_s1,*v_s2,*v_dst;
811 /* get required compiler data */
815 v_s1 = VAROP(iptr->s1);
816 v_s2 = VAROP(iptr->sx.s23.s2);
817 v_dst = VAROP(iptr->dst);
819 s1 = v_s1->vv.regoff;
820 s2 = v_s2->vv.regoff;
821 d = v_dst->vv.regoff;
823 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
825 if (IS_INMEMORY(v_dst->flags)) {
826 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
828 M_ILD(RCX, REG_SP, s2 * 8);
829 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
832 M_ILD(RCX, REG_SP, s2 * 8);
833 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
834 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
835 M_IST(REG_ITMP2, REG_SP, d * 8);
838 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
839 /* s1 may be equal to RCX */
842 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
843 M_IST(s1, REG_SP, d * 8);
844 M_INTMOVE(REG_ITMP1, RCX);
847 M_IST(s1, REG_SP, d * 8);
848 M_ILD(RCX, REG_SP, s2 * 8);
852 M_ILD(RCX, REG_SP, s2 * 8);
853 M_IST(s1, REG_SP, d * 8);
856 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
858 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
861 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
865 M_ILD(REG_ITMP2, REG_SP, s1 * 8);
866 emit_shiftl_reg(cd, shift_op, REG_ITMP2);
867 M_IST(REG_ITMP2, REG_SP, d * 8);
871 /* s1 may be equal to RCX */
872 M_IST(s1, REG_SP, d * 8);
874 emit_shiftl_membase(cd, shift_op, REG_SP, d * 8);
877 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
885 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
886 M_ILD(RCX, REG_SP, s2 * 8);
887 M_ILD(d, REG_SP, s1 * 8);
888 emit_shiftl_reg(cd, shift_op, d);
890 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
891 /* s1 may be equal to RCX */
893 M_ILD(RCX, REG_SP, s2 * 8);
894 emit_shiftl_reg(cd, shift_op, d);
896 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
898 M_ILD(d, REG_SP, s1 * 8);
899 emit_shiftl_reg(cd, shift_op, d);
902 /* s1 may be equal to RCX */
905 /* d cannot be used to backup s1 since this would
907 M_INTMOVE(s1, REG_ITMP3);
909 M_INTMOVE(REG_ITMP3, d);
917 /* d may be equal to s2 */
921 emit_shiftl_reg(cd, shift_op, d);
925 M_INTMOVE(REG_ITMP3, RCX);
927 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
932 void emit_lshift(jitdata *jd, s4 shift_op, instruction *iptr)
935 varinfo *v_s1,*v_s2,*v_dst;
938 /* get required compiler data */
942 v_s1 = VAROP(iptr->s1);
943 v_s2 = VAROP(iptr->sx.s23.s2);
944 v_dst = VAROP(iptr->dst);
946 s1 = v_s1->vv.regoff;
947 s2 = v_s2->vv.regoff;
948 d = v_dst->vv.regoff;
950 M_INTMOVE(RCX, REG_ITMP1); /* save RCX */
952 if (IS_INMEMORY(v_dst->flags)) {
953 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
955 M_ILD(RCX, REG_SP, s2 * 8);
956 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
959 M_ILD(RCX, REG_SP, s2 * 8);
960 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
961 emit_shift_reg(cd, shift_op, REG_ITMP2);
962 M_LST(REG_ITMP2, REG_SP, d * 8);
965 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
966 /* s1 may be equal to RCX */
969 M_ILD(REG_ITMP1, REG_SP, s2 * 8);
970 M_LST(s1, REG_SP, d * 8);
971 M_INTMOVE(REG_ITMP1, RCX);
974 M_LST(s1, REG_SP, d * 8);
975 M_ILD(RCX, REG_SP, s2 * 8);
979 M_ILD(RCX, REG_SP, s2 * 8);
980 M_LST(s1, REG_SP, d * 8);
983 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
985 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
988 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
992 M_LLD(REG_ITMP2, REG_SP, s1 * 8);
993 emit_shift_reg(cd, shift_op, REG_ITMP2);
994 M_LST(REG_ITMP2, REG_SP, d * 8);
998 /* s1 may be equal to RCX */
999 M_LST(s1, REG_SP, d * 8);
1001 emit_shift_membase(cd, shift_op, REG_SP, d * 8);
1004 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1012 if (IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1013 M_ILD(RCX, REG_SP, s2 * 8);
1014 M_LLD(d, REG_SP, s1 * 8);
1015 emit_shift_reg(cd, shift_op, d);
1017 } else if (IS_INMEMORY(v_s2->flags) && !IS_INMEMORY(v_s1->flags)) {
1018 /* s1 may be equal to RCX */
1020 M_ILD(RCX, REG_SP, s2 * 8);
1021 emit_shift_reg(cd, shift_op, d);
1023 } else if (!IS_INMEMORY(v_s2->flags) && IS_INMEMORY(v_s1->flags)) {
1025 M_LLD(d, REG_SP, s1 * 8);
1026 emit_shift_reg(cd, shift_op, d);
1029 /* s1 may be equal to RCX */
1032 /* d cannot be used to backup s1 since this would
1034 M_INTMOVE(s1, REG_ITMP3);
1036 M_INTMOVE(REG_ITMP3, d);
1044 /* d may be equal to s2 */
1048 emit_shift_reg(cd, shift_op, d);
1052 M_INTMOVE(REG_ITMP3, RCX);
1054 M_INTMOVE(REG_ITMP1, RCX); /* restore RCX */
1059 /* low-level code emitter functions *******************************************/
1061 void emit_mov_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1063 emit_rex(1,(reg),0,(dreg));
1064 *(cd->mcodeptr++) = 0x89;
1065 emit_reg((reg),(dreg));
1069 void emit_mov_imm_reg(codegendata *cd, s8 imm, s8 reg)
1071 emit_rex(1,0,0,(reg));
1072 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1077 void emit_movl_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1079 emit_rex(0,(reg),0,(dreg));
1080 *(cd->mcodeptr++) = 0x89;
1081 emit_reg((reg),(dreg));
1085 void emit_movl_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1086 emit_rex(0,0,0,(reg));
1087 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
1092 void emit_mov_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1093 emit_rex(1,(reg),0,(basereg));
1094 *(cd->mcodeptr++) = 0x8b;
1095 emit_membase(cd, (basereg),(disp),(reg));
1100 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
1101 * constant membase immediate length of 32bit
1103 void emit_mov_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1104 emit_rex(1,(reg),0,(basereg));
1105 *(cd->mcodeptr++) = 0x8b;
1106 emit_membase32(cd, (basereg),(disp),(reg));
1110 void emit_movl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1112 emit_rex(0,(reg),0,(basereg));
1113 *(cd->mcodeptr++) = 0x8b;
1114 emit_membase(cd, (basereg),(disp),(reg));
1118 /* ATTENTION: Always emit a REX byte, because the instruction size can
1119 be smaller when all register indexes are smaller than 7. */
1120 void emit_movl_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg)
1122 emit_byte_rex((reg),0,(basereg));
1123 *(cd->mcodeptr++) = 0x8b;
1124 emit_membase32(cd, (basereg),(disp),(reg));
1128 void emit_mov_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1129 emit_rex(1,(reg),0,(basereg));
1130 *(cd->mcodeptr++) = 0x89;
1131 emit_membase(cd, (basereg),(disp),(reg));
1135 void emit_mov_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1136 emit_rex(1,(reg),0,(basereg));
1137 *(cd->mcodeptr++) = 0x89;
1138 emit_membase32(cd, (basereg),(disp),(reg));
1142 void emit_movl_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1143 emit_rex(0,(reg),0,(basereg));
1144 *(cd->mcodeptr++) = 0x89;
1145 emit_membase(cd, (basereg),(disp),(reg));
1149 /* Always emit a REX byte, because the instruction size can be smaller when */
1150 /* all register indexes are smaller than 7. */
1151 void emit_movl_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
1152 emit_byte_rex((reg),0,(basereg));
1153 *(cd->mcodeptr++) = 0x89;
1154 emit_membase32(cd, (basereg),(disp),(reg));
1158 void emit_mov_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1159 emit_rex(1,(reg),(indexreg),(basereg));
1160 *(cd->mcodeptr++) = 0x8b;
1161 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1165 void emit_movl_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1166 emit_rex(0,(reg),(indexreg),(basereg));
1167 *(cd->mcodeptr++) = 0x8b;
1168 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1172 void emit_mov_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1173 emit_rex(1,(reg),(indexreg),(basereg));
1174 *(cd->mcodeptr++) = 0x89;
1175 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1179 void emit_movl_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1180 emit_rex(0,(reg),(indexreg),(basereg));
1181 *(cd->mcodeptr++) = 0x89;
1182 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1186 void emit_movw_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1187 *(cd->mcodeptr++) = 0x66;
1188 emit_rex(0,(reg),(indexreg),(basereg));
1189 *(cd->mcodeptr++) = 0x89;
1190 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1194 void emit_movb_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
1195 emit_byte_rex((reg),(indexreg),(basereg));
1196 *(cd->mcodeptr++) = 0x88;
1197 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1201 void emit_mov_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1202 emit_rex(1,0,0,(basereg));
1203 *(cd->mcodeptr++) = 0xc7;
1204 emit_membase(cd, (basereg),(disp),0);
1209 void emit_mov_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1210 emit_rex(1,0,0,(basereg));
1211 *(cd->mcodeptr++) = 0xc7;
1212 emit_membase32(cd, (basereg),(disp),0);
1217 void emit_movl_imm_membase(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1218 emit_rex(0,0,0,(basereg));
1219 *(cd->mcodeptr++) = 0xc7;
1220 emit_membase(cd, (basereg),(disp),0);
1225 /* Always emit a REX byte, because the instruction size can be smaller when */
1226 /* all register indexes are smaller than 7. */
1227 void emit_movl_imm_membase32(codegendata *cd, s8 imm, s8 basereg, s8 disp) {
1228 emit_byte_rex(0,0,(basereg));
1229 *(cd->mcodeptr++) = 0xc7;
1230 emit_membase32(cd, (basereg),(disp),0);
1235 void emit_movsbq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1237 emit_rex(1,(dreg),0,(reg));
1238 *(cd->mcodeptr++) = 0x0f;
1239 *(cd->mcodeptr++) = 0xbe;
1240 /* XXX: why do reg and dreg have to be exchanged */
1241 emit_reg((dreg),(reg));
1245 void emit_movswq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1247 emit_rex(1,(dreg),0,(reg));
1248 *(cd->mcodeptr++) = 0x0f;
1249 *(cd->mcodeptr++) = 0xbf;
1250 /* XXX: why do reg and dreg have to be exchanged */
1251 emit_reg((dreg),(reg));
1255 void emit_movslq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1257 emit_rex(1,(dreg),0,(reg));
1258 *(cd->mcodeptr++) = 0x63;
1259 /* XXX: why do reg and dreg have to be exchanged */
1260 emit_reg((dreg),(reg));
1264 void emit_movzwq_reg_reg(codegendata *cd, s8 reg, s8 dreg)
1266 emit_rex(1,(dreg),0,(reg));
1267 *(cd->mcodeptr++) = 0x0f;
1268 *(cd->mcodeptr++) = 0xb7;
1269 /* XXX: why do reg and dreg have to be exchanged */
1270 emit_reg((dreg),(reg));
1274 void emit_movswq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1275 emit_rex(1,(reg),(indexreg),(basereg));
1276 *(cd->mcodeptr++) = 0x0f;
1277 *(cd->mcodeptr++) = 0xbf;
1278 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1282 void emit_movsbq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1283 emit_rex(1,(reg),(indexreg),(basereg));
1284 *(cd->mcodeptr++) = 0x0f;
1285 *(cd->mcodeptr++) = 0xbe;
1286 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1290 void emit_movzwq_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 reg) {
1291 emit_rex(1,(reg),(indexreg),(basereg));
1292 *(cd->mcodeptr++) = 0x0f;
1293 *(cd->mcodeptr++) = 0xb7;
1294 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1298 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1300 emit_rex(1,0,(indexreg),(basereg));
1301 *(cd->mcodeptr++) = 0xc7;
1302 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1307 void emit_movl_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1309 emit_rex(0,0,(indexreg),(basereg));
1310 *(cd->mcodeptr++) = 0xc7;
1311 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1316 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1318 *(cd->mcodeptr++) = 0x66;
1319 emit_rex(0,0,(indexreg),(basereg));
1320 *(cd->mcodeptr++) = 0xc7;
1321 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1326 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1328 emit_rex(0,0,(indexreg),(basereg));
1329 *(cd->mcodeptr++) = 0xc6;
1330 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1338 void emit_alu_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1340 emit_rex(1,(reg),0,(dreg));
1341 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1342 emit_reg((reg),(dreg));
1346 void emit_alul_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1348 emit_rex(0,(reg),0,(dreg));
1349 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1350 emit_reg((reg),(dreg));
1354 void emit_alu_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1356 emit_rex(1,(reg),0,(basereg));
1357 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1358 emit_membase(cd, (basereg),(disp),(reg));
1362 void emit_alul_reg_membase(codegendata *cd, s8 opc, s8 reg, s8 basereg, s8 disp)
1364 emit_rex(0,(reg),0,(basereg));
1365 *(cd->mcodeptr++) = (((opc)) << 3) + 1;
1366 emit_membase(cd, (basereg),(disp),(reg));
1370 void emit_alu_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1372 emit_rex(1,(reg),0,(basereg));
1373 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1374 emit_membase(cd, (basereg),(disp),(reg));
1378 void emit_alul_membase_reg(codegendata *cd, s8 opc, s8 basereg, s8 disp, s8 reg)
1380 emit_rex(0,(reg),0,(basereg));
1381 *(cd->mcodeptr++) = (((opc)) << 3) + 3;
1382 emit_membase(cd, (basereg),(disp),(reg));
1386 void emit_alu_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1388 emit_rex(1,0,0,(dreg));
1389 *(cd->mcodeptr++) = 0x83;
1390 emit_reg((opc),(dreg));
1393 emit_rex(1,0,0,(dreg));
1394 *(cd->mcodeptr++) = 0x81;
1395 emit_reg((opc),(dreg));
1401 void emit_alu_imm32_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1402 emit_rex(1,0,0,(dreg));
1403 *(cd->mcodeptr++) = 0x81;
1404 emit_reg((opc),(dreg));
1409 void emit_alul_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1411 emit_rex(0,0,0,(dreg));
1412 *(cd->mcodeptr++) = 0x83;
1413 emit_reg((opc),(dreg));
1416 emit_rex(0,0,0,(dreg));
1417 *(cd->mcodeptr++) = 0x81;
1418 emit_reg((opc),(dreg));
1424 void emit_alu_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1426 emit_rex(1,(basereg),0,0);
1427 *(cd->mcodeptr++) = 0x83;
1428 emit_membase(cd, (basereg),(disp),(opc));
1431 emit_rex(1,(basereg),0,0);
1432 *(cd->mcodeptr++) = 0x81;
1433 emit_membase(cd, (basereg),(disp),(opc));
1439 void emit_alul_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1441 emit_rex(0,(basereg),0,0);
1442 *(cd->mcodeptr++) = 0x83;
1443 emit_membase(cd, (basereg),(disp),(opc));
1446 emit_rex(0,(basereg),0,0);
1447 *(cd->mcodeptr++) = 0x81;
1448 emit_membase(cd, (basereg),(disp),(opc));
1454 void emit_test_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1455 emit_rex(1,(reg),0,(dreg));
1456 *(cd->mcodeptr++) = 0x85;
1457 emit_reg((reg),(dreg));
1461 void emit_testl_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1462 emit_rex(0,(reg),0,(dreg));
1463 *(cd->mcodeptr++) = 0x85;
1464 emit_reg((reg),(dreg));
1468 void emit_test_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1469 *(cd->mcodeptr++) = 0xf7;
1475 void emit_testw_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1476 *(cd->mcodeptr++) = 0x66;
1477 *(cd->mcodeptr++) = 0xf7;
1483 void emit_testb_imm_reg(codegendata *cd, s8 imm, s8 reg) {
1484 *(cd->mcodeptr++) = 0xf6;
1490 void emit_lea_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1491 emit_rex(1,(reg),0,(basereg));
1492 *(cd->mcodeptr++) = 0x8d;
1493 emit_membase(cd, (basereg),(disp),(reg));
1497 void emit_leal_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 reg) {
1498 emit_rex(0,(reg),0,(basereg));
1499 *(cd->mcodeptr++) = 0x8d;
1500 emit_membase(cd, (basereg),(disp),(reg));
1505 void emit_incl_membase(codegendata *cd, s8 basereg, s8 disp)
1507 emit_rex(0,0,0,(basereg));
1508 *(cd->mcodeptr++) = 0xff;
1509 emit_membase(cd, (basereg),(disp),0);
1514 void emit_cltd(codegendata *cd) {
1515 *(cd->mcodeptr++) = 0x99;
1519 void emit_cqto(codegendata *cd) {
1521 *(cd->mcodeptr++) = 0x99;
1526 void emit_imul_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1527 emit_rex(1,(dreg),0,(reg));
1528 *(cd->mcodeptr++) = 0x0f;
1529 *(cd->mcodeptr++) = 0xaf;
1530 emit_reg((dreg),(reg));
1534 void emit_imull_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1535 emit_rex(0,(dreg),0,(reg));
1536 *(cd->mcodeptr++) = 0x0f;
1537 *(cd->mcodeptr++) = 0xaf;
1538 emit_reg((dreg),(reg));
1542 void emit_imul_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1543 emit_rex(1,(dreg),0,(basereg));
1544 *(cd->mcodeptr++) = 0x0f;
1545 *(cd->mcodeptr++) = 0xaf;
1546 emit_membase(cd, (basereg),(disp),(dreg));
1550 void emit_imull_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
1551 emit_rex(0,(dreg),0,(basereg));
1552 *(cd->mcodeptr++) = 0x0f;
1553 *(cd->mcodeptr++) = 0xaf;
1554 emit_membase(cd, (basereg),(disp),(dreg));
1558 void emit_imul_imm_reg(codegendata *cd, s8 imm, s8 dreg) {
1559 if (IS_IMM8((imm))) {
1560 emit_rex(1,0,0,(dreg));
1561 *(cd->mcodeptr++) = 0x6b;
1565 emit_rex(1,0,0,(dreg));
1566 *(cd->mcodeptr++) = 0x69;
1573 void emit_imul_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1574 if (IS_IMM8((imm))) {
1575 emit_rex(1,(dreg),0,(reg));
1576 *(cd->mcodeptr++) = 0x6b;
1577 emit_reg((dreg),(reg));
1580 emit_rex(1,(dreg),0,(reg));
1581 *(cd->mcodeptr++) = 0x69;
1582 emit_reg((dreg),(reg));
1588 void emit_imull_imm_reg_reg(codegendata *cd, s8 imm, s8 reg, s8 dreg) {
1589 if (IS_IMM8((imm))) {
1590 emit_rex(0,(dreg),0,(reg));
1591 *(cd->mcodeptr++) = 0x6b;
1592 emit_reg((dreg),(reg));
1595 emit_rex(0,(dreg),0,(reg));
1596 *(cd->mcodeptr++) = 0x69;
1597 emit_reg((dreg),(reg));
1603 void emit_imul_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1604 if (IS_IMM8((imm))) {
1605 emit_rex(1,(dreg),0,(basereg));
1606 *(cd->mcodeptr++) = 0x6b;
1607 emit_membase(cd, (basereg),(disp),(dreg));
1610 emit_rex(1,(dreg),0,(basereg));
1611 *(cd->mcodeptr++) = 0x69;
1612 emit_membase(cd, (basereg),(disp),(dreg));
1618 void emit_imull_imm_membase_reg(codegendata *cd, s8 imm, s8 basereg, s8 disp, s8 dreg) {
1619 if (IS_IMM8((imm))) {
1620 emit_rex(0,(dreg),0,(basereg));
1621 *(cd->mcodeptr++) = 0x6b;
1622 emit_membase(cd, (basereg),(disp),(dreg));
1625 emit_rex(0,(dreg),0,(basereg));
1626 *(cd->mcodeptr++) = 0x69;
1627 emit_membase(cd, (basereg),(disp),(dreg));
1633 void emit_idiv_reg(codegendata *cd, s8 reg) {
1634 emit_rex(1,0,0,(reg));
1635 *(cd->mcodeptr++) = 0xf7;
1640 void emit_idivl_reg(codegendata *cd, s8 reg) {
1641 emit_rex(0,0,0,(reg));
1642 *(cd->mcodeptr++) = 0xf7;
1648 void emit_ret(codegendata *cd) {
1649 *(cd->mcodeptr++) = 0xc3;
1657 void emit_shift_reg(codegendata *cd, s8 opc, s8 reg) {
1658 emit_rex(1,0,0,(reg));
1659 *(cd->mcodeptr++) = 0xd3;
1660 emit_reg((opc),(reg));
1664 void emit_shiftl_reg(codegendata *cd, s8 opc, s8 reg) {
1665 emit_rex(0,0,0,(reg));
1666 *(cd->mcodeptr++) = 0xd3;
1667 emit_reg((opc),(reg));
1671 void emit_shift_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1672 emit_rex(1,0,0,(basereg));
1673 *(cd->mcodeptr++) = 0xd3;
1674 emit_membase(cd, (basereg),(disp),(opc));
1678 void emit_shiftl_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1679 emit_rex(0,0,0,(basereg));
1680 *(cd->mcodeptr++) = 0xd3;
1681 emit_membase(cd, (basereg),(disp),(opc));
1685 void emit_shift_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1687 emit_rex(1,0,0,(dreg));
1688 *(cd->mcodeptr++) = 0xd1;
1689 emit_reg((opc),(dreg));
1691 emit_rex(1,0,0,(dreg));
1692 *(cd->mcodeptr++) = 0xc1;
1693 emit_reg((opc),(dreg));
1699 void emit_shiftl_imm_reg(codegendata *cd, s8 opc, s8 imm, s8 dreg) {
1701 emit_rex(0,0,0,(dreg));
1702 *(cd->mcodeptr++) = 0xd1;
1703 emit_reg((opc),(dreg));
1705 emit_rex(0,0,0,(dreg));
1706 *(cd->mcodeptr++) = 0xc1;
1707 emit_reg((opc),(dreg));
1713 void emit_shift_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1715 emit_rex(1,0,0,(basereg));
1716 *(cd->mcodeptr++) = 0xd1;
1717 emit_membase(cd, (basereg),(disp),(opc));
1719 emit_rex(1,0,0,(basereg));
1720 *(cd->mcodeptr++) = 0xc1;
1721 emit_membase(cd, (basereg),(disp),(opc));
1727 void emit_shiftl_imm_membase(codegendata *cd, s8 opc, s8 imm, s8 basereg, s8 disp) {
1729 emit_rex(0,0,0,(basereg));
1730 *(cd->mcodeptr++) = 0xd1;
1731 emit_membase(cd, (basereg),(disp),(opc));
1733 emit_rex(0,0,0,(basereg));
1734 *(cd->mcodeptr++) = 0xc1;
1735 emit_membase(cd, (basereg),(disp),(opc));
1745 void emit_jmp_imm(codegendata *cd, s8 imm) {
1746 *(cd->mcodeptr++) = 0xe9;
1751 void emit_jmp_reg(codegendata *cd, s8 reg) {
1752 emit_rex(0,0,0,(reg));
1753 *(cd->mcodeptr++) = 0xff;
1758 void emit_jcc(codegendata *cd, s8 opc, s8 imm) {
1759 *(cd->mcodeptr++) = 0x0f;
1760 *(cd->mcodeptr++) = (0x80 + (opc));
1767 * conditional set and move operations
1770 /* we need the rex byte to get all low bytes */
1771 void emit_setcc_reg(codegendata *cd, s8 opc, s8 reg) {
1772 *(cd->mcodeptr++) = (0x40 | (((reg) >> 3) & 0x01));
1773 *(cd->mcodeptr++) = 0x0f;
1774 *(cd->mcodeptr++) = (0x90 + (opc));
1779 /* we need the rex byte to get all low bytes */
1780 void emit_setcc_membase(codegendata *cd, s8 opc, s8 basereg, s8 disp) {
1781 *(cd->mcodeptr++) = (0x40 | (((basereg) >> 3) & 0x01));
1782 *(cd->mcodeptr++) = 0x0f;
1783 *(cd->mcodeptr++) = (0x90 + (opc));
1784 emit_membase(cd, (basereg),(disp),0);
1788 void emit_cmovcc_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1790 emit_rex(1,(dreg),0,(reg));
1791 *(cd->mcodeptr++) = 0x0f;
1792 *(cd->mcodeptr++) = (0x40 + (opc));
1793 emit_reg((dreg),(reg));
1797 void emit_cmovccl_reg_reg(codegendata *cd, s8 opc, s8 reg, s8 dreg)
1799 emit_rex(0,(dreg),0,(reg));
1800 *(cd->mcodeptr++) = 0x0f;
1801 *(cd->mcodeptr++) = (0x40 + (opc));
1802 emit_reg((dreg),(reg));
1807 void emit_neg_reg(codegendata *cd, s8 reg)
1809 emit_rex(1,0,0,(reg));
1810 *(cd->mcodeptr++) = 0xf7;
1815 void emit_negl_reg(codegendata *cd, s8 reg)
1817 emit_rex(0,0,0,(reg));
1818 *(cd->mcodeptr++) = 0xf7;
1823 void emit_push_reg(codegendata *cd, s8 reg) {
1824 emit_rex(0,0,0,(reg));
1825 *(cd->mcodeptr++) = 0x50 + (0x07 & (reg));
1829 void emit_push_imm(codegendata *cd, s8 imm) {
1830 *(cd->mcodeptr++) = 0x68;
1835 void emit_pop_reg(codegendata *cd, s8 reg) {
1836 emit_rex(0,0,0,(reg));
1837 *(cd->mcodeptr++) = 0x58 + (0x07 & (reg));
1841 void emit_xchg_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1842 emit_rex(1,(reg),0,(dreg));
1843 *(cd->mcodeptr++) = 0x87;
1844 emit_reg((reg),(dreg));
1848 void emit_nop(codegendata *cd) {
1849 *(cd->mcodeptr++) = 0x90;
1857 void emit_call_reg(codegendata *cd, s8 reg) {
1858 emit_rex(1,0,0,(reg));
1859 *(cd->mcodeptr++) = 0xff;
1864 void emit_call_imm(codegendata *cd, s8 imm) {
1865 *(cd->mcodeptr++) = 0xe8;
1870 void emit_call_mem(codegendata *cd, ptrint mem)
1872 *(cd->mcodeptr++) = 0xff;
1879 * floating point instructions (SSE2)
1881 void emit_addsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1882 *(cd->mcodeptr++) = 0xf2;
1883 emit_rex(0,(dreg),0,(reg));
1884 *(cd->mcodeptr++) = 0x0f;
1885 *(cd->mcodeptr++) = 0x58;
1886 emit_reg((dreg),(reg));
1890 void emit_addss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1891 *(cd->mcodeptr++) = 0xf3;
1892 emit_rex(0,(dreg),0,(reg));
1893 *(cd->mcodeptr++) = 0x0f;
1894 *(cd->mcodeptr++) = 0x58;
1895 emit_reg((dreg),(reg));
1899 void emit_cvtsi2ssq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1900 *(cd->mcodeptr++) = 0xf3;
1901 emit_rex(1,(dreg),0,(reg));
1902 *(cd->mcodeptr++) = 0x0f;
1903 *(cd->mcodeptr++) = 0x2a;
1904 emit_reg((dreg),(reg));
1908 void emit_cvtsi2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1909 *(cd->mcodeptr++) = 0xf3;
1910 emit_rex(0,(dreg),0,(reg));
1911 *(cd->mcodeptr++) = 0x0f;
1912 *(cd->mcodeptr++) = 0x2a;
1913 emit_reg((dreg),(reg));
1917 void emit_cvtsi2sdq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1918 *(cd->mcodeptr++) = 0xf2;
1919 emit_rex(1,(dreg),0,(reg));
1920 *(cd->mcodeptr++) = 0x0f;
1921 *(cd->mcodeptr++) = 0x2a;
1922 emit_reg((dreg),(reg));
1926 void emit_cvtsi2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1927 *(cd->mcodeptr++) = 0xf2;
1928 emit_rex(0,(dreg),0,(reg));
1929 *(cd->mcodeptr++) = 0x0f;
1930 *(cd->mcodeptr++) = 0x2a;
1931 emit_reg((dreg),(reg));
1935 void emit_cvtss2sd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1936 *(cd->mcodeptr++) = 0xf3;
1937 emit_rex(0,(dreg),0,(reg));
1938 *(cd->mcodeptr++) = 0x0f;
1939 *(cd->mcodeptr++) = 0x5a;
1940 emit_reg((dreg),(reg));
1944 void emit_cvtsd2ss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1945 *(cd->mcodeptr++) = 0xf2;
1946 emit_rex(0,(dreg),0,(reg));
1947 *(cd->mcodeptr++) = 0x0f;
1948 *(cd->mcodeptr++) = 0x5a;
1949 emit_reg((dreg),(reg));
1953 void emit_cvttss2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1954 *(cd->mcodeptr++) = 0xf3;
1955 emit_rex(1,(dreg),0,(reg));
1956 *(cd->mcodeptr++) = 0x0f;
1957 *(cd->mcodeptr++) = 0x2c;
1958 emit_reg((dreg),(reg));
1962 void emit_cvttss2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1963 *(cd->mcodeptr++) = 0xf3;
1964 emit_rex(0,(dreg),0,(reg));
1965 *(cd->mcodeptr++) = 0x0f;
1966 *(cd->mcodeptr++) = 0x2c;
1967 emit_reg((dreg),(reg));
1971 void emit_cvttsd2siq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1972 *(cd->mcodeptr++) = 0xf2;
1973 emit_rex(1,(dreg),0,(reg));
1974 *(cd->mcodeptr++) = 0x0f;
1975 *(cd->mcodeptr++) = 0x2c;
1976 emit_reg((dreg),(reg));
1980 void emit_cvttsd2si_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1981 *(cd->mcodeptr++) = 0xf2;
1982 emit_rex(0,(dreg),0,(reg));
1983 *(cd->mcodeptr++) = 0x0f;
1984 *(cd->mcodeptr++) = 0x2c;
1985 emit_reg((dreg),(reg));
1989 void emit_divss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1990 *(cd->mcodeptr++) = 0xf3;
1991 emit_rex(0,(dreg),0,(reg));
1992 *(cd->mcodeptr++) = 0x0f;
1993 *(cd->mcodeptr++) = 0x5e;
1994 emit_reg((dreg),(reg));
1998 void emit_divsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
1999 *(cd->mcodeptr++) = 0xf2;
2000 emit_rex(0,(dreg),0,(reg));
2001 *(cd->mcodeptr++) = 0x0f;
2002 *(cd->mcodeptr++) = 0x5e;
2003 emit_reg((dreg),(reg));
2007 void emit_movd_reg_freg(codegendata *cd, s8 reg, s8 freg) {
2008 *(cd->mcodeptr++) = 0x66;
2009 emit_rex(1,(freg),0,(reg));
2010 *(cd->mcodeptr++) = 0x0f;
2011 *(cd->mcodeptr++) = 0x6e;
2012 emit_reg((freg),(reg));
2016 void emit_movd_freg_reg(codegendata *cd, s8 freg, s8 reg) {
2017 *(cd->mcodeptr++) = 0x66;
2018 emit_rex(1,(freg),0,(reg));
2019 *(cd->mcodeptr++) = 0x0f;
2020 *(cd->mcodeptr++) = 0x7e;
2021 emit_reg((freg),(reg));
2025 void emit_movd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2026 *(cd->mcodeptr++) = 0x66;
2027 emit_rex(0,(reg),0,(basereg));
2028 *(cd->mcodeptr++) = 0x0f;
2029 *(cd->mcodeptr++) = 0x7e;
2030 emit_membase(cd, (basereg),(disp),(reg));
2034 void emit_movd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2035 *(cd->mcodeptr++) = 0x66;
2036 emit_rex(0,(reg),(indexreg),(basereg));
2037 *(cd->mcodeptr++) = 0x0f;
2038 *(cd->mcodeptr++) = 0x7e;
2039 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2043 void emit_movd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2044 *(cd->mcodeptr++) = 0x66;
2045 emit_rex(1,(dreg),0,(basereg));
2046 *(cd->mcodeptr++) = 0x0f;
2047 *(cd->mcodeptr++) = 0x6e;
2048 emit_membase(cd, (basereg),(disp),(dreg));
2052 void emit_movdl_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2053 *(cd->mcodeptr++) = 0x66;
2054 emit_rex(0,(dreg),0,(basereg));
2055 *(cd->mcodeptr++) = 0x0f;
2056 *(cd->mcodeptr++) = 0x6e;
2057 emit_membase(cd, (basereg),(disp),(dreg));
2061 void emit_movd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2062 *(cd->mcodeptr++) = 0x66;
2063 emit_rex(0,(dreg),(indexreg),(basereg));
2064 *(cd->mcodeptr++) = 0x0f;
2065 *(cd->mcodeptr++) = 0x6e;
2066 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2070 void emit_movq_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2071 *(cd->mcodeptr++) = 0xf3;
2072 emit_rex(0,(dreg),0,(reg));
2073 *(cd->mcodeptr++) = 0x0f;
2074 *(cd->mcodeptr++) = 0x7e;
2075 emit_reg((dreg),(reg));
2079 void emit_movq_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2080 *(cd->mcodeptr++) = 0x66;
2081 emit_rex(0,(reg),0,(basereg));
2082 *(cd->mcodeptr++) = 0x0f;
2083 *(cd->mcodeptr++) = 0xd6;
2084 emit_membase(cd, (basereg),(disp),(reg));
2088 void emit_movq_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2089 *(cd->mcodeptr++) = 0xf3;
2090 emit_rex(0,(dreg),0,(basereg));
2091 *(cd->mcodeptr++) = 0x0f;
2092 *(cd->mcodeptr++) = 0x7e;
2093 emit_membase(cd, (basereg),(disp),(dreg));
2097 void emit_movss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2098 *(cd->mcodeptr++) = 0xf3;
2099 emit_rex(0,(reg),0,(dreg));
2100 *(cd->mcodeptr++) = 0x0f;
2101 *(cd->mcodeptr++) = 0x10;
2102 emit_reg((reg),(dreg));
2106 void emit_movsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2107 *(cd->mcodeptr++) = 0xf2;
2108 emit_rex(0,(reg),0,(dreg));
2109 *(cd->mcodeptr++) = 0x0f;
2110 *(cd->mcodeptr++) = 0x10;
2111 emit_reg((reg),(dreg));
2115 void emit_movss_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2116 *(cd->mcodeptr++) = 0xf3;
2117 emit_rex(0,(reg),0,(basereg));
2118 *(cd->mcodeptr++) = 0x0f;
2119 *(cd->mcodeptr++) = 0x11;
2120 emit_membase(cd, (basereg),(disp),(reg));
2124 /* Always emit a REX byte, because the instruction size can be smaller when */
2125 /* all register indexes are smaller than 7. */
2126 void emit_movss_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2127 *(cd->mcodeptr++) = 0xf3;
2128 emit_byte_rex((reg),0,(basereg));
2129 *(cd->mcodeptr++) = 0x0f;
2130 *(cd->mcodeptr++) = 0x11;
2131 emit_membase32(cd, (basereg),(disp),(reg));
2135 void emit_movsd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2136 *(cd->mcodeptr++) = 0xf2;
2137 emit_rex(0,(reg),0,(basereg));
2138 *(cd->mcodeptr++) = 0x0f;
2139 *(cd->mcodeptr++) = 0x11;
2140 emit_membase(cd, (basereg),(disp),(reg));
2144 /* Always emit a REX byte, because the instruction size can be smaller when */
2145 /* all register indexes are smaller than 7. */
2146 void emit_movsd_reg_membase32(codegendata *cd, s8 reg, s8 basereg, s8 disp) {
2147 *(cd->mcodeptr++) = 0xf2;
2148 emit_byte_rex((reg),0,(basereg));
2149 *(cd->mcodeptr++) = 0x0f;
2150 *(cd->mcodeptr++) = 0x11;
2151 emit_membase32(cd, (basereg),(disp),(reg));
2155 void emit_movss_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2156 *(cd->mcodeptr++) = 0xf3;
2157 emit_rex(0,(dreg),0,(basereg));
2158 *(cd->mcodeptr++) = 0x0f;
2159 *(cd->mcodeptr++) = 0x10;
2160 emit_membase(cd, (basereg),(disp),(dreg));
2164 /* Always emit a REX byte, because the instruction size can be smaller when */
2165 /* all register indexes are smaller than 7. */
2166 void emit_movss_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2167 *(cd->mcodeptr++) = 0xf3;
2168 emit_byte_rex((dreg),0,(basereg));
2169 *(cd->mcodeptr++) = 0x0f;
2170 *(cd->mcodeptr++) = 0x10;
2171 emit_membase32(cd, (basereg),(disp),(dreg));
2175 void emit_movlps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2177 emit_rex(0,(dreg),0,(basereg));
2178 *(cd->mcodeptr++) = 0x0f;
2179 *(cd->mcodeptr++) = 0x12;
2180 emit_membase(cd, (basereg),(disp),(dreg));
2184 void emit_movlps_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2186 emit_rex(0,(reg),0,(basereg));
2187 *(cd->mcodeptr++) = 0x0f;
2188 *(cd->mcodeptr++) = 0x13;
2189 emit_membase(cd, (basereg),(disp),(reg));
2193 void emit_movsd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2194 *(cd->mcodeptr++) = 0xf2;
2195 emit_rex(0,(dreg),0,(basereg));
2196 *(cd->mcodeptr++) = 0x0f;
2197 *(cd->mcodeptr++) = 0x10;
2198 emit_membase(cd, (basereg),(disp),(dreg));
2202 /* Always emit a REX byte, because the instruction size can be smaller when */
2203 /* all register indexes are smaller than 7. */
2204 void emit_movsd_membase32_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2205 *(cd->mcodeptr++) = 0xf2;
2206 emit_byte_rex((dreg),0,(basereg));
2207 *(cd->mcodeptr++) = 0x0f;
2208 *(cd->mcodeptr++) = 0x10;
2209 emit_membase32(cd, (basereg),(disp),(dreg));
2213 void emit_movlpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg)
2215 *(cd->mcodeptr++) = 0x66;
2216 emit_rex(0,(dreg),0,(basereg));
2217 *(cd->mcodeptr++) = 0x0f;
2218 *(cd->mcodeptr++) = 0x12;
2219 emit_membase(cd, (basereg),(disp),(dreg));
2223 void emit_movlpd_reg_membase(codegendata *cd, s8 reg, s8 basereg, s8 disp)
2225 *(cd->mcodeptr++) = 0x66;
2226 emit_rex(0,(reg),0,(basereg));
2227 *(cd->mcodeptr++) = 0x0f;
2228 *(cd->mcodeptr++) = 0x13;
2229 emit_membase(cd, (basereg),(disp),(reg));
2233 void emit_movss_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2234 *(cd->mcodeptr++) = 0xf3;
2235 emit_rex(0,(reg),(indexreg),(basereg));
2236 *(cd->mcodeptr++) = 0x0f;
2237 *(cd->mcodeptr++) = 0x11;
2238 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2242 void emit_movsd_reg_memindex(codegendata *cd, s8 reg, s8 disp, s8 basereg, s8 indexreg, s8 scale) {
2243 *(cd->mcodeptr++) = 0xf2;
2244 emit_rex(0,(reg),(indexreg),(basereg));
2245 *(cd->mcodeptr++) = 0x0f;
2246 *(cd->mcodeptr++) = 0x11;
2247 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
2251 void emit_movss_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2252 *(cd->mcodeptr++) = 0xf3;
2253 emit_rex(0,(dreg),(indexreg),(basereg));
2254 *(cd->mcodeptr++) = 0x0f;
2255 *(cd->mcodeptr++) = 0x10;
2256 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2260 void emit_movsd_memindex_reg(codegendata *cd, s8 disp, s8 basereg, s8 indexreg, s8 scale, s8 dreg) {
2261 *(cd->mcodeptr++) = 0xf2;
2262 emit_rex(0,(dreg),(indexreg),(basereg));
2263 *(cd->mcodeptr++) = 0x0f;
2264 *(cd->mcodeptr++) = 0x10;
2265 emit_memindex(cd, (dreg),(disp),(basereg),(indexreg),(scale));
2269 void emit_mulss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2270 *(cd->mcodeptr++) = 0xf3;
2271 emit_rex(0,(dreg),0,(reg));
2272 *(cd->mcodeptr++) = 0x0f;
2273 *(cd->mcodeptr++) = 0x59;
2274 emit_reg((dreg),(reg));
2278 void emit_mulsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2279 *(cd->mcodeptr++) = 0xf2;
2280 emit_rex(0,(dreg),0,(reg));
2281 *(cd->mcodeptr++) = 0x0f;
2282 *(cd->mcodeptr++) = 0x59;
2283 emit_reg((dreg),(reg));
2287 void emit_subss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2288 *(cd->mcodeptr++) = 0xf3;
2289 emit_rex(0,(dreg),0,(reg));
2290 *(cd->mcodeptr++) = 0x0f;
2291 *(cd->mcodeptr++) = 0x5c;
2292 emit_reg((dreg),(reg));
2296 void emit_subsd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2297 *(cd->mcodeptr++) = 0xf2;
2298 emit_rex(0,(dreg),0,(reg));
2299 *(cd->mcodeptr++) = 0x0f;
2300 *(cd->mcodeptr++) = 0x5c;
2301 emit_reg((dreg),(reg));
2305 void emit_ucomiss_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2306 emit_rex(0,(dreg),0,(reg));
2307 *(cd->mcodeptr++) = 0x0f;
2308 *(cd->mcodeptr++) = 0x2e;
2309 emit_reg((dreg),(reg));
2313 void emit_ucomisd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2314 *(cd->mcodeptr++) = 0x66;
2315 emit_rex(0,(dreg),0,(reg));
2316 *(cd->mcodeptr++) = 0x0f;
2317 *(cd->mcodeptr++) = 0x2e;
2318 emit_reg((dreg),(reg));
2322 void emit_xorps_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2323 emit_rex(0,(dreg),0,(reg));
2324 *(cd->mcodeptr++) = 0x0f;
2325 *(cd->mcodeptr++) = 0x57;
2326 emit_reg((dreg),(reg));
2330 void emit_xorps_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2331 emit_rex(0,(dreg),0,(basereg));
2332 *(cd->mcodeptr++) = 0x0f;
2333 *(cd->mcodeptr++) = 0x57;
2334 emit_membase(cd, (basereg),(disp),(dreg));
2338 void emit_xorpd_reg_reg(codegendata *cd, s8 reg, s8 dreg) {
2339 *(cd->mcodeptr++) = 0x66;
2340 emit_rex(0,(dreg),0,(reg));
2341 *(cd->mcodeptr++) = 0x0f;
2342 *(cd->mcodeptr++) = 0x57;
2343 emit_reg((dreg),(reg));
2347 void emit_xorpd_membase_reg(codegendata *cd, s8 basereg, s8 disp, s8 dreg) {
2348 *(cd->mcodeptr++) = 0x66;
2349 emit_rex(0,(dreg),0,(basereg));
2350 *(cd->mcodeptr++) = 0x0f;
2351 *(cd->mcodeptr++) = 0x57;
2352 emit_membase(cd, (basereg),(disp),(dreg));
2356 /* system instructions ********************************************************/
2358 void emit_rdtsc(codegendata *cd)
2360 *(cd->mcodeptr++) = 0x0f;
2361 *(cd->mcodeptr++) = 0x31;
2364 /* emit_load_high **************************************************************
2366 Emits a possible load of the high 32-bits of an operand.
2368 *******************************************************************************/
2370 __PORTED__ s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
2376 assert(src->type == TYPE_LNG);
2378 /* get required compiler data */
2382 if (IS_INMEMORY(src->flags)) {
2385 disp = src->vv.regoff * 4;
2387 M_ILD(tempreg, REG_SP, disp);
2392 reg = GET_HIGH_REG(src->vv.regoff);
2397 /* emit_load_low ***************************************************************
2399 Emits a possible load of the low 32-bits of an operand.
2401 *******************************************************************************/
2403 __PORTED__ s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
2409 assert(src->type == TYPE_LNG);
2411 /* get required compiler data */
2415 if (IS_INMEMORY(src->flags)) {
2418 disp = src->vv.regoff * 4;
2420 M_ILD(tempreg, REG_SP, disp + 4);
2425 reg = GET_LOW_REG(src->vv.regoff);
2430 /* emit_nullpointer_check ******************************************************
2432 Emit a NullPointerException check.
2434 *******************************************************************************/
2436 __PORTED__ void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
2438 if (INSTRUCTION_MUST_CHECK(iptr)) {
2441 codegen_add_nullpointerexception_ref(cd);
2445 /* emit_arrayindexoutofbounds_check ********************************************
2447 Emit a ArrayIndexOutOfBoundsException check.
2449 *******************************************************************************/
2451 __PORTED__ void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
2453 if (INSTRUCTION_MUST_CHECK(iptr)) {
2455 * Do unsigned comparison to catch negative indexes.
2457 N_CL(s2, OFFSET(java_arrayheader, size), RN, s1);
2459 codegen_add_arrayindexoutofboundsexception_ref(cd, s2);
2463 s4 emit_load_s1_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
2464 codegendata *cd = jd->cd;
2465 s4 reg = emit_load_s1(jd, iptr, tempreg);
2467 M_MOV(reg, tempreg);
2474 s4 emit_load_s2_notzero(jitdata *jd, instruction *iptr, s4 tempreg) {
2475 codegendata *cd = jd->cd;
2476 s4 reg = emit_load_s2(jd, iptr, tempreg);
2478 M_MOV(reg, tempreg);
2485 s4 emit_load_s1_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
2486 codegendata *cd = jd->cd;
2487 s4 reg = emit_load_s1(jd, iptr, tempreg);
2488 if (reg == notreg) {
2489 M_MOV(reg, tempreg);
2496 s4 emit_load_s2_but(jitdata *jd, instruction *iptr, s4 tempreg, s4 notreg) {
2497 codegendata *cd = jd->cd;
2498 s4 reg = emit_load_s2(jd, iptr, tempreg);
2499 if (reg == notreg) {
2500 M_MOV(reg, tempreg);
2507 s4 emit_alloc_dst_even_odd(jitdata *jd, instruction *iptr, s4 htmpreg, s4 ltmpreg, s4 breg) {
2518 * (r12, r13) Illegal, because r13 is PV
2519 * (r14, r15) Illegal, because r15 is SP
2523 dst = VAROP(iptr->dst);
2525 if (IS_INMEMORY(dst->flags)) {
2526 if (! IS_REG_ITMP(ltmpreg)) {
2527 M_INTMOVE(ltmpreg, breg);
2529 if (! IS_REG_ITMP(htmpreg)) {
2530 M_INTMOVE(htmpreg, breg);
2532 return PACK_REGS(ltmpreg, htmpreg);
2534 hr = GET_HIGH_REG(dst->vv.regoff);
2535 lr = GET_LOW_REG(dst->vv.regoff);
2536 if (((hr % 2) == 0) && lr == (hr + 1)) {
2537 /* the result is already in a even-odd pair */
2538 return dst->vv.regoff;
2539 } else if (((hr % 2) == 0) && (hr < R12)) {
2540 /* the high register is at a even position */
2541 M_INTMOVE(hr + 1, breg);
2542 return PACK_REGS(hr + 1, hr);
2543 } else if (((lr % 2) == 1) && (lr < R12)) {
2544 /* the low register is at a odd position */
2545 M_INTMOVE(lr - 1, breg);
2546 return PACK_REGS(lr, lr - 1);
2548 /* no way to create an even-odd pair by 1 copy operation,
2549 * Use the temporary register pair.
2551 if (! IS_REG_ITMP(ltmpreg)) {
2552 M_INTMOVE(ltmpreg, breg);
2554 if (! IS_REG_ITMP(htmpreg)) {
2555 M_INTMOVE(htmpreg, breg);
2557 return PACK_REGS(ltmpreg, htmpreg);
2562 void emit_restore_dst_even_odd(jitdata *jd, instruction *iptr, s4 htmpreg, s4 ltmpreg, s4 breg) {
2568 dst = VAROP(iptr->dst);
2570 if (IS_INMEMORY(dst->flags)) {
2571 if (! IS_REG_ITMP(ltmpreg)) {
2572 M_INTMOVE(breg, ltmpreg);
2574 if (! IS_REG_ITMP(htmpreg)) {
2575 M_INTMOVE(breg, htmpreg);
2578 hr = GET_HIGH_REG(dst->vv.regoff);
2579 lr = GET_LOW_REG(dst->vv.regoff);
2580 if (((hr % 2) == 0) && lr == (hr + 1)) {
2582 } else if (((hr % 2) == 0) && (hr < R12)) {
2583 M_INTMOVE(breg, hr + 1);
2584 } else if (((lr % 2) == 1) && (lr < R12)) {
2585 M_INTMOVE(breg, lr - 1);
2587 if (! IS_REG_ITMP(ltmpreg)) {
2588 M_INTMOVE(breg, ltmpreg);
2590 if (! IS_REG_ITMP(htmpreg)) {
2591 M_INTMOVE(breg, htmpreg);
2597 void emit_copy_dst(jitdata *jd, instruction *iptr, s4 dtmpreg) {
2601 dst = VAROP(iptr->dst);
2602 if (! IS_INMEMORY(dst->flags)) {
2603 if (dst->vv.regoff != dtmpreg) {
2604 if (IS_FLT_DBL_TYPE(dst->type)) {
2605 M_FLTMOVE(dtmpreg, dst->vv.regoff);
2606 } else if (IS_2_WORD_TYPE(dst->type)) {
2607 M_LNGMOVE(dtmpreg, dst->vv.regoff);
2609 M_INTMOVE(dtmpreg, dst->vv.regoff);
2616 * These are local overrides for various environment variables in Emacs.
2617 * Please do not remove this and leave it at the end of the file, where
2618 * Emacs will automagically detect them.
2619 * ---------------------------------------------------------------------
2622 * indent-tabs-mode: t