1 /* src/vm/jit/powerpc/codegen.c - machine code generator for 32-bit PowerPC
3 Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 Contact: cacao@cacaojvm.org
27 Authors: Andreas Krall
30 Changes: Christian Thalinger
33 $Id: codegen.c 4357 2006-01-22 23:33:38Z twisti $
48 #include "vm/jit/powerpc/arch.h"
49 #include "vm/jit/powerpc/codegen.h"
51 #include "cacao/cacao.h"
52 #include "native/native.h"
53 #include "vm/builtin.h"
54 #include "vm/exceptions.h"
55 #include "vm/global.h"
56 #include "vm/loader.h"
57 #include "vm/options.h"
58 #include "vm/stringlocal.h"
59 #include "vm/jit/asmpart.h"
60 #include "vm/jit/codegen-common.h"
61 #include "vm/jit/dseg.h"
62 #include "vm/jit/jit.h"
63 #include "vm/jit/parse.h"
64 #include "vm/jit/patcher.h"
65 #include "vm/jit/reg.h"
67 #if defined(ENABLE_LSRA)
68 # include "vm/jit/allocator/lsra.h"
74 s4 *codegen_trace_args( methodinfo *m, codegendata *cd, registerdata *rd,
75 s4 *mcodeptr, s4 parentargs_base, bool nativestub);
77 /* codegen *********************************************************************
79 Generates machine code.
81 *******************************************************************************/
83 bool codegen(methodinfo *m, codegendata *cd, registerdata *rd)
85 s4 len, s1, s2, s3, d, disp;
95 methodinfo *lm; /* local methodinfo for ICMD_INVOKE* */
96 builtintable_entry *bte;
99 /* prevent compiler warnings */
111 /* space to save used callee saved registers */
113 savedregs_num += (INT_SAV_CNT - rd->savintreguse);
114 savedregs_num += 2 * (FLT_SAV_CNT - rd->savfltreguse);
116 parentargs_base = rd->memuse + savedregs_num;
118 #if defined(USE_THREADS)
119 /* space to save argument of monitor_enter and Return Values to survive */
120 /* monitor_exit. The stack position for the argument can not be shared */
121 /* with place to save the return register on PPC, since both values */
123 if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
124 /* reserve 2 slots for long/double return values for monitorexit */
126 if (IS_2_WORD_TYPE(m->parseddesc->returntype.type))
127 parentargs_base += 3;
129 parentargs_base += 2;
134 /* create method header */
136 parentargs_base = (parentargs_base + 3) & ~3;
138 (void) dseg_addaddress(cd, m); /* MethodPointer */
139 (void) dseg_adds4(cd, parentargs_base * 4); /* FrameSize */
141 #if defined(USE_THREADS)
142 /* IsSync contains the offset relative to the stack pointer for the
143 argument of monitor_exit used in the exception handler. Since the
144 offset could be zero and give a wrong meaning of the flag it is
148 if (checksync && (m->flags & ACC_SYNCHRONIZED))
149 (void) dseg_adds4(cd, (rd->memuse + 1) * 4); /* IsSync */
152 (void) dseg_adds4(cd, 0); /* IsSync */
154 (void) dseg_adds4(cd, m->isleafmethod); /* IsLeaf */
155 (void) dseg_adds4(cd, INT_SAV_CNT - rd->savintreguse); /* IntSave */
156 (void) dseg_adds4(cd, FLT_SAV_CNT - rd->savfltreguse); /* FltSave */
158 dseg_addlinenumbertablesize(cd);
160 (void) dseg_adds4(cd, cd->exceptiontablelength); /* ExTableSize */
162 /* create exception table */
164 for (ex = cd->exceptiontable; ex != NULL; ex = ex->down) {
165 dseg_addtarget(cd, ex->start);
166 dseg_addtarget(cd, ex->end);
167 dseg_addtarget(cd, ex->handler);
168 (void) dseg_addaddress(cd, ex->catchtype.cls);
171 /* initialize mcode variables */
173 mcodeptr = (s4 *) cd->mcodeptr;
175 MCODECHECK(128 + m->paramcount);
177 /* create stack frame (if necessary) */
179 if (!m->isleafmethod) {
181 M_AST(REG_ZERO, REG_SP, LA_LR_OFFSET);
184 if (parentargs_base) {
185 M_STWU(REG_SP, REG_SP, -parentargs_base * 4);
188 /* save return address and used callee saved registers */
191 for (i = INT_SAV_CNT - 1; i >= rd->savintreguse; i--) {
192 p--; M_IST(rd->savintregs[i], REG_SP, p * 4);
194 for (i = FLT_SAV_CNT - 1; i >= rd->savfltreguse; i--) {
195 p -= 2; M_DST(rd->savfltregs[i], REG_SP, p * 4);
198 /* take arguments out of register or stack frame */
202 for (p = 0, l = 0; p < md->paramcount; p++) {
203 t = md->paramtypes[p].type;
204 var = &(rd->locals[l][t]);
206 if (IS_2_WORD_TYPE(t)) /* increment local counter for 2 word types */
210 s1 = md->params[p].regoff;
211 if (IS_INT_LNG_TYPE(t)) { /* integer args */
212 if (IS_2_WORD_TYPE(t))
213 s2 = PACK_REGS(rd->argintregs[GET_LOW_REG(s1)],
214 rd->argintregs[GET_HIGH_REG(s1)]);
216 s2 = rd->argintregs[s1];
217 if (!md->params[p].inmemory) { /* register arguments */
218 if (!(var->flags & INMEMORY)) { /* reg arg -> register */
219 M_TINTMOVE(t, s2, var->regoff);
221 } else { /* reg arg -> spilled */
222 if (IS_2_WORD_TYPE(t)) {
223 M_IST(GET_HIGH_REG(s2), REG_SP, var->regoff * 4);
224 M_IST(GET_LOW_REG(s2), REG_SP, var->regoff * 4 + 4);
226 M_IST(s2, REG_SP, var->regoff * 4);
230 } else { /* stack arguments */
231 if (!(var->flags & INMEMORY)) { /* stack arg -> register */
232 if (IS_2_WORD_TYPE(t)) {
233 M_ILD(GET_HIGH_REG(var->regoff), REG_SP,
234 (parentargs_base + s1) * 4);
235 M_ILD(GET_LOW_REG(var->regoff), REG_SP,
236 (parentargs_base + s1) * 4 + 4);
238 M_ILD(var->regoff, REG_SP, (parentargs_base + s1) * 4);
241 } else { /* stack arg -> spilled */
243 M_ILD(REG_ITMP1, REG_SP, (parentargs_base + s1) * 4);
244 M_IST(REG_ITMP1, REG_SP, var->regoff * 4);
245 if (IS_2_WORD_TYPE(t)) {
246 M_ILD(REG_ITMP1, REG_SP, (parentargs_base + s1) * 4 +4);
247 M_IST(REG_ITMP1, REG_SP, var->regoff * 4 + 4);
250 /* Reuse Memory Position on Caller Stack */
251 var->regoff = parentargs_base + s1;
256 } else { /* floating args */
257 if (!md->params[p].inmemory) { /* register arguments */
258 s2 = rd->argfltregs[s1];
259 if (!(var->flags & INMEMORY)) { /* reg arg -> register */
260 M_FLTMOVE(s2, var->regoff);
262 } else { /* reg arg -> spilled */
263 if (IS_2_WORD_TYPE(t))
264 M_DST(s2, REG_SP, var->regoff * 4);
266 M_FST(s2, REG_SP, var->regoff * 4);
269 } else { /* stack arguments */
270 if (!(var->flags & INMEMORY)) { /* stack-arg -> register */
271 if (IS_2_WORD_TYPE(t))
272 M_DLD(var->regoff, REG_SP, (parentargs_base + s1) * 4);
275 M_FLD(var->regoff, REG_SP, (parentargs_base + s1) * 4);
277 } else { /* stack-arg -> spilled */
279 if (IS_2_WORD_TYPE(t)) {
280 M_DLD(REG_FTMP1, REG_SP, (parentargs_base + s1) * 4);
281 M_DST(REG_FTMP1, REG_SP, var->regoff * 4);
282 var->regoff = parentargs_base + s1;
285 M_FLD(REG_FTMP1, REG_SP, (parentargs_base + s1) * 4);
286 M_FST(REG_FTMP1, REG_SP, var->regoff * 4);
289 /* Reuse Memory Position on Caller Stack */
290 var->regoff = parentargs_base + s1;
297 /* save monitorenter argument */
299 #if defined(USE_THREADS)
300 if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
301 /* stack offset for monitor argument */
307 M_LDA(REG_SP, REG_SP, -(INT_ARG_CNT * 4 + FLT_ARG_CNT * 8));
309 for (p = 0; p < INT_ARG_CNT; p++)
310 M_IST(rd->argintregs[p], REG_SP, p * 4);
312 for (p = 0; p < FLT_ARG_CNT * 2; p += 2)
313 M_DST(rd->argfltregs[p], REG_SP, (INT_ARG_CNT + p) * 4);
315 s1 += INT_ARG_CNT + FLT_ARG_CNT;
319 /* decide which monitor enter function to call */
321 if (m->flags & ACC_STATIC) {
322 p = dseg_addaddress(cd, m->class);
323 M_ALD(rd->argintregs[0], REG_PV, p);
324 M_AST(rd->argintregs[0], REG_SP, s1 * 4);
325 p = dseg_addaddress(cd, BUILTIN_staticmonitorenter);
326 M_ALD(REG_ITMP3, REG_PV, p);
331 M_TST(rd->argintregs[0]);
333 codegen_addxnullrefs(cd, mcodeptr);
334 M_AST(rd->argintregs[0], REG_SP, s1 * 4);
335 p = dseg_addaddress(cd, BUILTIN_monitorenter);
336 M_ALD(REG_ITMP3, REG_PV, p);
343 for (p = 0; p < INT_ARG_CNT; p++)
344 M_ILD(rd->argintregs[p], REG_SP, p * 4);
346 for (p = 0; p < FLT_ARG_CNT; p++)
347 M_DLD(rd->argfltregs[p], REG_SP, (INT_ARG_CNT + p) * 4);
350 M_LDA(REG_SP, REG_SP, (INT_ARG_CNT + FLT_ARG_CNT) * 8);
356 /* call trace function */
359 mcodeptr = codegen_trace_args(m, cd, rd, mcodeptr, parentargs_base, false);
361 } /* if (runverbose) */
364 /* end of header generation */
366 /* walk through all basic blocks */
367 for (bptr = m->basicblocks; bptr != NULL; bptr = bptr->next) {
369 bptr->mpc = (s4) ((u1 *) mcodeptr - cd->mcodebase);
371 if (bptr->flags >= BBREACHED) {
373 /* branch resolving */
377 for (brefs = bptr->branchrefs; brefs != NULL; brefs = brefs->next) {
378 gen_resolvebranch((u1*) cd->mcodebase + brefs->branchpos,
384 /* copy interface registers to their destination */
390 #if defined(ENABLE_LSRA)
392 while (src != NULL) {
394 if ((len == 0) && (bptr->type != BBTYPE_STD)) {
395 /* d = reg_of_var(m, src, REG_ITMP1); */
396 if (!(src->flags & INMEMORY))
400 M_INTMOVE(REG_ITMP1, d);
401 store_reg_to_var_int(src, d);
407 while (src != NULL) {
409 if ((len == 0) && (bptr->type != BBTYPE_STD)) {
410 d = reg_of_var(rd, src, REG_ITMP1);
411 M_INTMOVE(REG_ITMP1, d);
412 store_reg_to_var_int(src, d);
414 if (src->type == TYPE_LNG)
415 d = reg_of_var(rd, src, PACK_REGS(REG_ITMP2, REG_ITMP1));
417 d = reg_of_var(rd, src, REG_IFTMP);
418 if ((src->varkind != STACKVAR)) {
420 if (IS_FLT_DBL_TYPE(s2)) {
421 if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
422 s1 = rd->interfaces[len][s2].regoff;
425 if (IS_2_WORD_TYPE(s2)) {
427 rd->interfaces[len][s2].regoff * 4);
430 rd->interfaces[len][s2].regoff * 4);
434 if (IS_2_WORD_TYPE(s2)) {
435 store_reg_to_var_dbl(src, d);
437 store_reg_to_var_flt(src, d);
440 if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
441 s1 = rd->interfaces[len][s2].regoff;
442 M_TINTMOVE(s2, s1, d);
444 if (IS_2_WORD_TYPE(s2)) {
445 M_ILD(GET_HIGH_REG(d), REG_SP,
446 rd->interfaces[len][s2].regoff * 4);
447 M_ILD(GET_LOW_REG(d), REG_SP,
448 rd->interfaces[len][s2].regoff * 4 + 4);
451 rd->interfaces[len][s2].regoff * 4);
455 if (IS_2_WORD_TYPE(s2)) {
456 store_reg_to_var_lng(src, d);
458 store_reg_to_var_int(src, d);
466 #if defined(ENABLE_LSRA)
469 /* walk through all instructions */
475 for (iptr = bptr->iinstr; len > 0; src = iptr->dst, len--, iptr++) {
476 if (iptr->line != currentline) {
477 dseg_addlinenumber(cd, iptr->line, (u1 *) mcodeptr);
478 currentline = iptr->line;
481 MCODECHECK(64); /* an instruction usually needs < 64 words */
484 case ICMD_NOP: /* ... ==> ... */
485 case ICMD_INLINE_START:
486 case ICMD_INLINE_END:
489 case ICMD_CHECKNULL: /* ..., objectref ==> ..., objectref */
491 var_to_reg_int(s1, src, REG_ITMP1);
494 codegen_addxnullrefs(cd, mcodeptr);
497 /* constant operations ************************************************/
499 case ICMD_ICONST: /* ... ==> ..., constant */
500 /* op1 = 0, val.i = constant */
502 d = reg_of_var(rd, iptr->dst, REG_ITMP1);
503 ICONST(d, iptr->val.i);
504 store_reg_to_var_int(iptr->dst, d);
507 case ICMD_LCONST: /* ... ==> ..., constant */
508 /* op1 = 0, val.l = constant */
510 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
511 LCONST(d, iptr->val.l);
512 store_reg_to_var_lng(iptr->dst, d);
515 case ICMD_FCONST: /* ... ==> ..., constant */
516 /* op1 = 0, val.f = constant */
518 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
519 a = dseg_addfloat(cd, iptr->val.f);
521 store_reg_to_var_flt(iptr->dst, d);
524 case ICMD_DCONST: /* ... ==> ..., constant */
525 /* op1 = 0, val.d = constant */
527 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
528 a = dseg_adddouble(cd, iptr->val.d);
530 store_reg_to_var_dbl(iptr->dst, d);
533 case ICMD_ACONST: /* ... ==> ..., constant */
534 /* op1 = 0, val.a = constant */
536 d = reg_of_var(rd, iptr->dst, REG_ITMP1);
537 disp = dseg_addaddress(cd, iptr->val.a);
539 if ((iptr->target != NULL) && (iptr->val.a == NULL)) {
540 codegen_addpatchref(cd, mcodeptr,
542 (unresolved_class *) iptr->target, disp);
544 if (opt_showdisassemble)
548 M_ALD(d, REG_PV, disp);
549 store_reg_to_var_adr(iptr->dst, d);
553 /* load/store operations **********************************************/
555 case ICMD_ILOAD: /* ... ==> ..., content of local variable */
556 case ICMD_ALOAD: /* op1 = local variable */
558 var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
559 d = reg_of_var(rd, iptr->dst, REG_ITMP1);
560 if ((iptr->dst->varkind == LOCALVAR) &&
561 (iptr->dst->varnum == iptr->op1))
563 if (var->flags & INMEMORY) {
564 M_ILD(d, REG_SP, var->regoff * 4);
566 M_TINTMOVE(var->type, var->regoff, d);
568 store_reg_to_var_int(iptr->dst, d);
571 case ICMD_LLOAD: /* ... ==> ..., content of local variable */
572 /* op1 = local variable */
574 var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
575 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
576 if ((iptr->dst->varkind == LOCALVAR) &&
577 (iptr->dst->varnum == iptr->op1))
579 if (var->flags & INMEMORY) {
580 M_ILD(GET_HIGH_REG(d), REG_SP, var->regoff * 4);
581 M_ILD(GET_LOW_REG(d), REG_SP, var->regoff * 4 + 4);
583 M_TINTMOVE(var->type, var->regoff, d);
585 store_reg_to_var_lng(iptr->dst, d);
588 case ICMD_FLOAD: /* ... ==> ..., content of local variable */
589 /* op1 = local variable */
591 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
592 if ((iptr->dst->varkind == LOCALVAR) &&
593 (iptr->dst->varnum == iptr->op1))
595 var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
596 if (var->flags & INMEMORY) {
597 M_FLD(d, REG_SP, var->regoff * 4);
599 M_FLTMOVE(var->regoff, d);
601 store_reg_to_var_flt(iptr->dst, d);
604 case ICMD_DLOAD: /* ... ==> ..., content of local variable */
605 /* op1 = local variable */
607 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
608 if ((iptr->dst->varkind == LOCALVAR) &&
609 (iptr->dst->varnum == iptr->op1))
611 var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ILOAD]);
612 if (var->flags & INMEMORY) {
613 M_DLD(d, REG_SP, var->regoff * 4);
615 M_FLTMOVE(var->regoff, d);
617 store_reg_to_var_dbl(iptr->dst, d);
621 case ICMD_ISTORE: /* ..., value ==> ... */
622 case ICMD_ASTORE: /* op1 = local variable */
624 if ((src->varkind == LOCALVAR) && (src->varnum == iptr->op1))
626 var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
627 if (var->flags & INMEMORY) {
628 var_to_reg_int(s1, src, REG_ITMP1);
629 M_IST(s1, REG_SP, var->regoff * 4);
631 var_to_reg_int(s1, src, var->regoff);
632 M_TINTMOVE(var->type, s1, var->regoff);
636 case ICMD_LSTORE: /* ..., value ==> ... */
637 /* op1 = local variable */
639 if ((src->varkind == LOCALVAR) && (src->varnum == iptr->op1))
641 var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
642 if (var->flags & INMEMORY) {
643 var_to_reg_int(s1, src, PACK_REGS(REG_ITMP2, REG_ITMP1));
644 M_IST(GET_HIGH_REG(s1), REG_SP, var->regoff * 4);
645 M_IST(GET_LOW_REG(s1), REG_SP, var->regoff * 4 + 4);
647 var_to_reg_int(s1, src, var->regoff);
648 M_TINTMOVE(var->type, s1, var->regoff);
652 case ICMD_FSTORE: /* ..., value ==> ... */
653 case ICMD_DSTORE: /* op1 = local variable */
655 if ((src->varkind == LOCALVAR) && (src->varnum == iptr->op1))
657 var = &(rd->locals[iptr->op1][iptr->opc - ICMD_ISTORE]);
658 if (var->flags & INMEMORY) {
659 var_to_reg_flt(s1, src, REG_FTMP1);
660 if (var->type == TYPE_DBL)
661 M_DST(s1, REG_SP, var->regoff * 4);
663 M_FST(s1, REG_SP, var->regoff * 4);
665 var_to_reg_flt(s1, src, var->regoff);
666 M_FLTMOVE(s1, var->regoff);
671 /* pop/dup/swap operations ********************************************/
673 /* attention: double and longs are only one entry in CACAO ICMDs */
675 case ICMD_POP: /* ..., value ==> ... */
676 case ICMD_POP2: /* ..., value, value ==> ... */
679 case ICMD_DUP: /* ..., a ==> ..., a, a */
680 M_COPY(src, iptr->dst);
683 case ICMD_DUP_X1: /* ..., a, b ==> ..., b, a, b */
685 M_COPY(src, iptr->dst);
686 M_COPY(src->prev, iptr->dst->prev);
687 M_COPY(iptr->dst, iptr->dst->prev->prev);
690 case ICMD_DUP_X2: /* ..., a, b, c ==> ..., c, a, b, c */
692 M_COPY(src, iptr->dst);
693 M_COPY(src->prev, iptr->dst->prev);
694 M_COPY(src->prev->prev, iptr->dst->prev->prev);
695 M_COPY(iptr->dst, iptr->dst->prev->prev->prev);
698 case ICMD_DUP2: /* ..., a, b ==> ..., a, b, a, b */
700 M_COPY(src, iptr->dst);
701 M_COPY(src->prev, iptr->dst->prev);
704 case ICMD_DUP2_X1: /* ..., a, b, c ==> ..., b, c, a, b, c */
706 M_COPY(src, iptr->dst);
707 M_COPY(src->prev, iptr->dst->prev);
708 M_COPY(src->prev->prev, iptr->dst->prev->prev);
709 M_COPY(iptr->dst, iptr->dst->prev->prev->prev);
710 M_COPY(iptr->dst->prev, iptr->dst->prev->prev->prev->prev);
713 case ICMD_DUP2_X2: /* ..., a, b, c, d ==> ..., c, d, a, b, c, d */
715 M_COPY(src, iptr->dst);
716 M_COPY(src->prev, iptr->dst->prev);
717 M_COPY(src->prev->prev, iptr->dst->prev->prev);
718 M_COPY(src->prev->prev->prev, iptr->dst->prev->prev->prev);
719 M_COPY(iptr->dst, iptr->dst->prev->prev->prev->prev);
720 M_COPY(iptr->dst->prev, iptr->dst->prev->prev->prev->prev->prev);
723 case ICMD_SWAP: /* ..., a, b ==> ..., b, a */
725 M_COPY(src, iptr->dst->prev);
726 M_COPY(src->prev, iptr->dst);
730 /* integer operations *************************************************/
732 case ICMD_INEG: /* ..., value ==> ..., - value */
734 var_to_reg_int(s1, src, REG_ITMP1);
735 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
737 store_reg_to_var_int(iptr->dst, d);
740 case ICMD_LNEG: /* ..., value ==> ..., - value */
742 var_to_reg_int(s1, src, PACK_REGS(REG_ITMP2, REG_ITMP1));
743 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
744 M_SUBFIC(GET_LOW_REG(s1), 0, GET_LOW_REG(d));
745 M_SUBFZE(GET_HIGH_REG(s1), GET_HIGH_REG(d));
746 store_reg_to_var_lng(iptr->dst, d);
749 case ICMD_I2L: /* ..., value ==> ..., value */
751 var_to_reg_int(s1, src, REG_ITMP2);
752 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
753 M_INTMOVE(s1, GET_LOW_REG(d));
754 M_SRA_IMM(GET_LOW_REG(d), 31, GET_HIGH_REG(d));
755 store_reg_to_var_lng(iptr->dst, d);
758 case ICMD_L2I: /* ..., value ==> ..., value */
760 var_to_reg_lng_low(s1, src, REG_ITMP2);
761 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
763 store_reg_to_var_int(iptr->dst, d);
766 case ICMD_INT2BYTE: /* ..., value ==> ..., value */
768 var_to_reg_int(s1, src, REG_ITMP1);
769 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
771 store_reg_to_var_int(iptr->dst, d);
774 case ICMD_INT2CHAR: /* ..., value ==> ..., value */
776 var_to_reg_int(s1, src, REG_ITMP1);
777 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
779 store_reg_to_var_int(iptr->dst, d);
782 case ICMD_INT2SHORT: /* ..., value ==> ..., value */
784 var_to_reg_int(s1, src, REG_ITMP1);
785 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
787 store_reg_to_var_int(iptr->dst, d);
791 case ICMD_IADD: /* ..., val1, val2 ==> ..., val1 + val2 */
793 var_to_reg_int(s1, src->prev, REG_ITMP1);
794 var_to_reg_int(s2, src, REG_ITMP2);
795 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
797 store_reg_to_var_int(iptr->dst, d);
800 case ICMD_IADDCONST: /* ..., value ==> ..., value + constant */
801 /* val.i = constant */
803 var_to_reg_int(s1, src, REG_ITMP1);
804 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
805 if ((iptr->val.i >= -32768) && (iptr->val.i <= 32767)) {
806 M_IADD_IMM(s1, iptr->val.i, d);
808 ICONST(REG_ITMP2, iptr->val.i);
809 M_IADD(s1, REG_ITMP2, d);
811 store_reg_to_var_int(iptr->dst, d);
814 case ICMD_LADD: /* ..., val1, val2 ==> ..., val1 + val2 */
816 var_to_reg_lng_low(s1, src->prev, REG_ITMP1);
817 var_to_reg_lng_low(s2, src, REG_ITMP2);
818 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
819 M_ADDC(s1, s2, GET_LOW_REG(d));
820 var_to_reg_lng_high(s1, src->prev, REG_ITMP1);
821 var_to_reg_lng_high(s2, src, REG_ITMP3); /* don't use REG_ITMP2 */
822 M_ADDE(s1, s2, GET_HIGH_REG(d));
823 store_reg_to_var_lng(iptr->dst, d);
826 case ICMD_LADDCONST: /* ..., value ==> ..., value + constant */
827 /* val.l = constant */
829 s3 = iptr->val.l & 0xffffffff;
830 var_to_reg_lng_low(s1, src, REG_ITMP1);
831 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
832 if ((s3 >= -32768) && (s3 <= 32767)) {
833 M_ADDIC(s1, s3, GET_LOW_REG(d));
835 ICONST(REG_ITMP2, s3);
836 M_ADDC(s1, REG_ITMP2, GET_LOW_REG(d));
838 var_to_reg_lng_high(s1, src, REG_ITMP1);
839 s3 = iptr->val.l >> 32;
841 M_ADDME(s1, GET_HIGH_REG(d));
842 } else if (s3 == 0) {
843 M_ADDZE(s1, GET_HIGH_REG(d));
845 ICONST(REG_ITMP3, s3); /* don't use REG_ITMP2 */
846 M_ADDE(s1, REG_ITMP3, GET_HIGH_REG(d));
848 store_reg_to_var_lng(iptr->dst, d);
851 case ICMD_ISUB: /* ..., val1, val2 ==> ..., val1 - val2 */
853 var_to_reg_int(s1, src->prev, REG_ITMP1);
854 var_to_reg_int(s2, src, REG_ITMP2);
855 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
857 store_reg_to_var_int(iptr->dst, d);
860 case ICMD_ISUBCONST: /* ..., value ==> ..., value + constant */
861 /* val.i = constant */
863 var_to_reg_int(s1, src, REG_ITMP1);
864 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
865 if ((iptr->val.i >= -32767) && (iptr->val.i <= 32768)) {
866 M_IADD_IMM(s1, -iptr->val.i, d);
868 ICONST(REG_ITMP2, -iptr->val.i);
869 M_IADD(s1, REG_ITMP2, d);
871 store_reg_to_var_int(iptr->dst, d);
874 case ICMD_LSUB: /* ..., val1, val2 ==> ..., val1 - val2 */
876 var_to_reg_lng_low(s1, src->prev, REG_ITMP1);
877 var_to_reg_lng_low(s2, src, REG_ITMP2);
878 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
879 M_SUBC(s1, s2, GET_LOW_REG(d));
880 var_to_reg_lng_high(s1, src->prev, REG_ITMP1);
881 var_to_reg_lng_high(s2, src, REG_ITMP3); /* don't use REG_ITMP2 */
882 M_SUBE(s1, s2, GET_HIGH_REG(d));
883 store_reg_to_var_lng(iptr->dst, d);
886 case ICMD_LSUBCONST: /* ..., value ==> ..., value - constant */
887 /* val.l = constant */
889 s3 = (-iptr->val.l) & 0xffffffff;
890 var_to_reg_lng_low(s1, src, REG_ITMP1);
891 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
892 if ((s3 >= -32768) && (s3 <= 32767)) {
893 M_ADDIC(s1, s3, GET_LOW_REG(d));
895 ICONST(REG_ITMP2, s3);
896 M_ADDC(s1, REG_ITMP2, GET_LOW_REG(d));
898 var_to_reg_lng_high(s1, src, REG_ITMP1);
899 s3 = (-iptr->val.l) >> 32;
901 M_ADDME(s1, GET_HIGH_REG(d));
903 M_ADDZE(s1, GET_HIGH_REG(d));
905 ICONST(REG_ITMP3, s3); /* don't use REG_ITMP2 */
906 M_ADDE(s1, REG_ITMP3, GET_HIGH_REG(d));
908 store_reg_to_var_lng(iptr->dst, d);
911 case ICMD_IDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
913 var_to_reg_int(s1, src->prev, REG_ITMP1);
914 var_to_reg_int(s2, src, REG_ITMP2);
915 d = reg_of_var(rd, iptr->dst, REG_ITMP1);
918 codegen_addxdivrefs(cd, mcodeptr);
919 M_LDAH(REG_ITMP3, REG_ZERO, 0x8000);
920 M_CMP(REG_ITMP3, s1);
921 M_BNE(3 + (s1 != d));
923 M_BNE(1 + (s1 != d));
927 store_reg_to_var_int(iptr->dst, d);
930 case ICMD_IREM: /* ..., val1, val2 ==> ..., val1 % val2 */
932 var_to_reg_int(s1, src->prev, REG_ITMP1);
933 var_to_reg_int(s2, src, REG_ITMP2);
934 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
937 codegen_addxdivrefs(cd, mcodeptr);
938 M_LDAH(REG_ITMP3, REG_ZERO, 0x8000);
939 M_CMP(REG_ITMP3, s1);
945 M_IDIV(s1, s2, REG_ITMP3);
946 M_IMUL(REG_ITMP3, s2, REG_ITMP3);
947 M_ISUB(s1, REG_ITMP3, d);
948 store_reg_to_var_int(iptr->dst, d);
951 case ICMD_LDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
952 case ICMD_LREM: /* ..., val1, val2 ==> ..., val1 % val2 */
957 var_to_reg_int(s2, src, PACK_REGS(REG_ITMP2, REG_ITMP1));
958 M_OR_TST(GET_HIGH_REG(s2), GET_LOW_REG(s2), REG_ITMP3);
960 codegen_addxdivrefs(cd, mcodeptr);
962 s3 = PACK_REGS(rd->argintregs[GET_LOW_REG(md->params[1].regoff)],
963 rd->argintregs[GET_HIGH_REG(md->params[1].regoff)]);
964 M_TINTMOVE(TYPE_LNG, s2, s3);
966 var_to_reg_int(s1, src->prev, PACK_REGS(REG_ITMP2, REG_ITMP1));
967 s3 = PACK_REGS(rd->argintregs[GET_LOW_REG(md->params[0].regoff)],
968 rd->argintregs[GET_HIGH_REG(md->params[0].regoff)]);
969 M_TINTMOVE(TYPE_LNG, s1, s3);
971 disp = dseg_addaddress(cd, bte->fp);
972 M_ALD(REG_ITMP1, REG_PV, disp);
976 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_RESULT2, REG_RESULT));
977 M_TINTMOVE(TYPE_LNG, PACK_REGS(REG_RESULT2, REG_RESULT), d);
978 store_reg_to_var_lng(iptr->dst, d);
981 case ICMD_IMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
983 var_to_reg_int(s1, src->prev, REG_ITMP1);
984 var_to_reg_int(s2, src, REG_ITMP2);
985 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
987 store_reg_to_var_int(iptr->dst, d);
990 case ICMD_IMULCONST: /* ..., value ==> ..., value * constant */
991 /* val.i = constant */
993 var_to_reg_int(s1, src, REG_ITMP1);
994 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
995 if ((iptr->val.i >= -32768) && (iptr->val.i <= 32767)) {
996 M_IMUL_IMM(s1, iptr->val.i, d);
998 ICONST(REG_ITMP3, iptr->val.i);
999 M_IMUL(s1, REG_ITMP3, d);
1001 store_reg_to_var_int(iptr->dst, d);
1004 case ICMD_IDIVPOW2: /* ..., value ==> ..., value << constant */
1006 var_to_reg_int(s1, src, REG_ITMP1);
1007 d = reg_of_var(rd, iptr->dst, REG_ITMP3);
1008 M_SRA_IMM(s1, iptr->val.i, d);
1010 store_reg_to_var_int(iptr->dst, d);
1013 case ICMD_ISHL: /* ..., val1, val2 ==> ..., val1 << val2 */
1015 var_to_reg_int(s1, src->prev, REG_ITMP1);
1016 var_to_reg_int(s2, src, REG_ITMP2);
1017 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1018 M_AND_IMM(s2, 0x1f, REG_ITMP3);
1019 M_SLL(s1, REG_ITMP3, d);
1020 store_reg_to_var_int(iptr->dst, d);
1023 case ICMD_ISHLCONST: /* ..., value ==> ..., value << constant */
1024 /* val.i = constant */
1026 var_to_reg_int(s1, src, REG_ITMP1);
1027 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1028 M_SLL_IMM(s1, iptr->val.i & 0x1f, d);
1029 store_reg_to_var_int(iptr->dst, d);
1032 case ICMD_ISHR: /* ..., val1, val2 ==> ..., val1 >> val2 */
1034 var_to_reg_int(s1, src->prev, REG_ITMP1);
1035 var_to_reg_int(s2, src, REG_ITMP2);
1036 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1037 M_AND_IMM(s2, 0x1f, REG_ITMP3);
1038 M_SRA(s1, REG_ITMP3, d);
1039 store_reg_to_var_int(iptr->dst, d);
1042 case ICMD_ISHRCONST: /* ..., value ==> ..., value >> constant */
1043 /* val.i = constant */
1045 var_to_reg_int(s1, src, REG_ITMP1);
1046 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1047 M_SRA_IMM(s1, iptr->val.i & 0x1f, d);
1048 store_reg_to_var_int(iptr->dst, d);
1051 case ICMD_IUSHR: /* ..., val1, val2 ==> ..., val1 >>> val2 */
1053 var_to_reg_int(s1, src->prev, REG_ITMP1);
1054 var_to_reg_int(s2, src, REG_ITMP2);
1055 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1056 M_AND_IMM(s2, 0x1f, REG_ITMP2);
1057 M_SRL(s1, REG_ITMP2, d);
1058 store_reg_to_var_int(iptr->dst, d);
1061 case ICMD_IUSHRCONST: /* ..., value ==> ..., value >>> constant */
1062 /* val.i = constant */
1064 var_to_reg_int(s1, src, REG_ITMP1);
1065 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1066 if (iptr->val.i & 0x1f) {
1067 M_SRL_IMM(s1, iptr->val.i & 0x1f, d);
1071 store_reg_to_var_int(iptr->dst, d);
1074 case ICMD_IAND: /* ..., val1, val2 ==> ..., val1 & val2 */
1076 var_to_reg_int(s1, src->prev, REG_ITMP1);
1077 var_to_reg_int(s2, src, REG_ITMP2);
1078 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1080 store_reg_to_var_int(iptr->dst, d);
1083 case ICMD_IANDCONST: /* ..., value ==> ..., value & constant */
1084 /* val.i = constant */
1086 var_to_reg_int(s1, src, REG_ITMP1);
1087 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1088 if ((iptr->val.i >= 0) && (iptr->val.i <= 65535)) {
1089 M_AND_IMM(s1, iptr->val.i, d);
1092 else if (iptr->val.i == 0xffffff) {
1093 M_RLWINM(s1, 0, 8, 31, d);
1097 ICONST(REG_ITMP3, iptr->val.i);
1098 M_AND(s1, REG_ITMP3, d);
1100 store_reg_to_var_int(iptr->dst, d);
1103 case ICMD_LAND: /* ..., val1, val2 ==> ..., val1 & val2 */
1105 var_to_reg_lng_low(s1, src->prev, REG_ITMP1);
1106 var_to_reg_lng_low(s2, src, REG_ITMP2);
1107 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
1108 M_AND(s1, s2, GET_LOW_REG(d));
1109 var_to_reg_lng_high(s1, src->prev, REG_ITMP1);
1110 var_to_reg_lng_high(s2, src, REG_ITMP3); /* don't use REG_ITMP2 */
1111 M_AND(s1, s2, GET_HIGH_REG(d));
1112 store_reg_to_var_lng(iptr->dst, d);
1115 case ICMD_LANDCONST: /* ..., value ==> ..., value & constant */
1116 /* val.l = constant */
1118 s3 = iptr->val.l & 0xffffffff;
1119 var_to_reg_lng_low(s1, src, REG_ITMP1);
1120 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
1121 if ((s3 >= 0) && (s3 <= 65535)) {
1122 M_AND_IMM(s1, s3, GET_LOW_REG(d));
1124 ICONST(REG_ITMP3, s3);
1125 M_AND(s1, REG_ITMP3, GET_LOW_REG(d));
1127 var_to_reg_lng_high(s1, src, REG_ITMP1);
1128 s3 = iptr->val.l >> 32;
1129 if ((s3 >= 0) && (s3 <= 65535)) {
1130 M_AND_IMM(s1, s3, GET_HIGH_REG(d));
1132 ICONST(REG_ITMP3, s3); /* don't use REG_ITMP2 */
1133 M_AND(s1, REG_ITMP3, GET_HIGH_REG(d));
1135 store_reg_to_var_lng(iptr->dst, d);
1138 case ICMD_IREMPOW2: /* ..., value ==> ..., value % constant */
1139 /* val.i = constant */
1141 var_to_reg_int(s1, src, REG_ITMP1);
1142 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1143 M_MOV(s1, REG_ITMP2);
1145 M_BGE(1 + 2*(iptr->val.i >= 32768));
1146 if (iptr->val.i >= 32768) {
1147 M_ADDIS(REG_ZERO, iptr->val.i >> 16, REG_ITMP2);
1148 M_OR_IMM(REG_ITMP2, iptr->val.i, REG_ITMP2);
1149 M_IADD(s1, REG_ITMP2, REG_ITMP2);
1151 M_IADD_IMM(s1, iptr->val.i, REG_ITMP2);
1154 int b=0, m = iptr->val.i;
1157 M_RLWINM(REG_ITMP2, 0, 0, 30-b, REG_ITMP2);
1159 M_ISUB(s1, REG_ITMP2, d);
1160 store_reg_to_var_int(iptr->dst, d);
1163 case ICMD_IOR: /* ..., val1, val2 ==> ..., val1 | val2 */
1165 var_to_reg_int(s1, src->prev, REG_ITMP1);
1166 var_to_reg_int(s2, src, REG_ITMP2);
1167 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1169 store_reg_to_var_int(iptr->dst, d);
1172 case ICMD_IORCONST: /* ..., value ==> ..., value | constant */
1173 /* val.i = constant */
1175 var_to_reg_int(s1, src, REG_ITMP1);
1176 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1177 if ((iptr->val.i >= 0) && (iptr->val.i <= 65535)) {
1178 M_OR_IMM(s1, iptr->val.i, d);
1180 ICONST(REG_ITMP3, iptr->val.i);
1181 M_OR(s1, REG_ITMP3, d);
1183 store_reg_to_var_int(iptr->dst, d);
1186 case ICMD_LOR: /* ..., val1, val2 ==> ..., val1 | val2 */
1188 var_to_reg_lng_low(s1, src->prev, REG_ITMP1);
1189 var_to_reg_lng_low(s2, src, REG_ITMP2);
1190 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
1191 M_OR(s1, s2, GET_LOW_REG(d));
1192 var_to_reg_lng_high(s1, src->prev, REG_ITMP1);
1193 var_to_reg_lng_high(s2, src, REG_ITMP3); /* don't use REG_ITMP2 */
1194 M_OR(s1, s2, GET_HIGH_REG(d));
1195 store_reg_to_var_lng(iptr->dst, d);
1198 case ICMD_LORCONST: /* ..., value ==> ..., value | constant */
1199 /* val.l = constant */
1201 s3 = iptr->val.l & 0xffffffff;
1202 var_to_reg_lng_low(s1, src, REG_ITMP1);
1203 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
1204 if ((s3 >= 0) && (s3 <= 65535)) {
1205 M_OR_IMM(s1, s3, GET_LOW_REG(d));
1207 ICONST(REG_ITMP3, s3);
1208 M_OR(s1, REG_ITMP3, GET_LOW_REG(d));
1210 var_to_reg_lng_high(s1, src, REG_ITMP1);
1211 s3 = iptr->val.l >> 32;
1212 if ((s3 >= 0) && (s3 <= 65535)) {
1213 M_OR_IMM(s1, s3, GET_HIGH_REG(d));
1215 ICONST(REG_ITMP3, s3); /* don't use REG_ITMP2 */
1216 M_OR(s1, REG_ITMP3, GET_HIGH_REG(d));
1218 store_reg_to_var_lng(iptr->dst, d);
1221 case ICMD_IXOR: /* ..., val1, val2 ==> ..., val1 ^ val2 */
1223 var_to_reg_int(s1, src->prev, REG_ITMP1);
1224 var_to_reg_int(s2, src, REG_ITMP2);
1225 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1227 store_reg_to_var_int(iptr->dst, d);
1230 case ICMD_IXORCONST: /* ..., value ==> ..., value ^ constant */
1231 /* val.i = constant */
1233 var_to_reg_int(s1, src, REG_ITMP1);
1234 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1235 if ((iptr->val.i >= 0) && (iptr->val.i <= 65535)) {
1236 M_XOR_IMM(s1, iptr->val.i, d);
1238 ICONST(REG_ITMP3, iptr->val.i);
1239 M_XOR(s1, REG_ITMP3, d);
1241 store_reg_to_var_int(iptr->dst, d);
1244 case ICMD_LXOR: /* ..., val1, val2 ==> ..., val1 ^ val2 */
1246 var_to_reg_lng_low(s1, src->prev, REG_ITMP1);
1247 var_to_reg_lng_low(s2, src, REG_ITMP2);
1248 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
1249 M_XOR(s1, s2, GET_LOW_REG(d));
1250 var_to_reg_lng_high(s1, src->prev, REG_ITMP1);
1251 var_to_reg_lng_high(s2, src, REG_ITMP3); /* don't use REG_ITMP2 */
1252 M_XOR(s1, s2, GET_HIGH_REG(d));
1253 store_reg_to_var_lng(iptr->dst, d);
1256 case ICMD_LXORCONST: /* ..., value ==> ..., value ^ constant */
1257 /* val.l = constant */
1259 s3 = iptr->val.l & 0xffffffff;
1260 var_to_reg_lng_low(s1, src, REG_ITMP1);
1261 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
1262 if ((s3 >= 0) && (s3 <= 65535)) {
1263 M_XOR_IMM(s1, s3, GET_LOW_REG(d));
1265 ICONST(REG_ITMP3, s3);
1266 M_XOR(s1, REG_ITMP3, GET_LOW_REG(d));
1268 var_to_reg_lng_high(s1, src, REG_ITMP1);
1269 s3 = iptr->val.l >> 32;
1270 if ((s3 >= 0) && (s3 <= 65535)) {
1271 M_XOR_IMM(s1, s3, GET_HIGH_REG(d));
1273 ICONST(REG_ITMP3, s3); /* don't use REG_ITMP2 */
1274 M_XOR(s1, REG_ITMP3, GET_HIGH_REG(d));
1276 store_reg_to_var_lng(iptr->dst, d);
1279 case ICMD_LCMP: /* ..., val1, val2 ==> ..., val1 cmp val2 */
1280 /*******************************************************************
1281 TODO: CHANGE THIS TO A VERSION THAT WORKS !!!
1282 *******************************************************************/
1283 var_to_reg_lng_high(s1, src->prev, REG_ITMP3);
1284 var_to_reg_lng_high(s2, src, REG_ITMP2);
1285 d = reg_of_var(rd, iptr->dst, REG_ITMP1);
1287 int tempreg = false;
1291 if (src->prev->flags & INMEMORY) {
1292 tempreg = tempreg || (d == REG_ITMP3) || (d == REG_ITMP2);
1294 tempreg = tempreg || (d == GET_HIGH_REG(src->prev->regoff))
1295 || (d == GET_LOW_REG(src->prev->regoff));
1297 if (src->flags & INMEMORY) {
1298 tempreg = tempreg || (d == REG_ITMP3) || (d == REG_ITMP2);
1300 tempreg = tempreg || (d == GET_HIGH_REG(src->regoff))
1301 || (d == GET_LOW_REG(src->regoff));
1304 dreg = tempreg ? REG_ITMP1 : d;
1305 M_IADD_IMM(REG_ZERO, 1, dreg);
1310 var_to_reg_lng_low(s1, src->prev, REG_ITMP3);
1311 var_to_reg_lng_low(s2, src, REG_ITMP2);
1315 M_IADD_IMM(dreg, -1, dreg);
1316 M_IADD_IMM(dreg, -1, dreg);
1317 gen_resolvebranch(br1, (u1*) br1, (u1*) mcodeptr);
1318 gen_resolvebranch(br1+1, (u1*) (br1+1), (u1*) (mcodeptr-2));
1321 store_reg_to_var_lng(iptr->dst, d);
1324 case ICMD_IINC: /* ..., value ==> ..., value + constant */
1325 /* op1 = variable, val.i = constant */
1327 var = &(rd->locals[iptr->op1][TYPE_INT]);
1328 if (var->flags & INMEMORY) {
1330 M_ILD(s1, REG_SP, var->regoff * 4);
1339 M_ADDIS(s1, m >> 16, s1);
1341 M_IADD_IMM(s1, m & 0xffff, s1);
1343 if (var->flags & INMEMORY) {
1344 M_IST(s1, REG_SP, var->regoff * 4);
1349 /* floating operations ************************************************/
1351 case ICMD_FNEG: /* ..., value ==> ..., - value */
1353 var_to_reg_flt(s1, src, REG_FTMP1);
1354 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1356 store_reg_to_var_flt(iptr->dst, d);
1359 case ICMD_DNEG: /* ..., value ==> ..., - value */
1361 var_to_reg_flt(s1, src, REG_FTMP1);
1362 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1364 store_reg_to_var_dbl(iptr->dst, d);
1367 case ICMD_FADD: /* ..., val1, val2 ==> ..., val1 + val2 */
1369 var_to_reg_flt(s1, src->prev, REG_FTMP1);
1370 var_to_reg_flt(s2, src, REG_FTMP2);
1371 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1373 store_reg_to_var_flt(iptr->dst, d);
1376 case ICMD_DADD: /* ..., val1, val2 ==> ..., val1 + val2 */
1378 var_to_reg_flt(s1, src->prev, REG_FTMP1);
1379 var_to_reg_flt(s2, src, REG_FTMP2);
1380 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1382 store_reg_to_var_dbl(iptr->dst, d);
1385 case ICMD_FSUB: /* ..., val1, val2 ==> ..., val1 - val2 */
1387 var_to_reg_flt(s1, src->prev, REG_FTMP1);
1388 var_to_reg_flt(s2, src, REG_FTMP2);
1389 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1391 store_reg_to_var_flt(iptr->dst, d);
1394 case ICMD_DSUB: /* ..., val1, val2 ==> ..., val1 - val2 */
1396 var_to_reg_flt(s1, src->prev, REG_FTMP1);
1397 var_to_reg_flt(s2, src, REG_FTMP2);
1398 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1400 store_reg_to_var_dbl(iptr->dst, d);
1403 case ICMD_FMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
1405 var_to_reg_flt(s1, src->prev, REG_FTMP1);
1406 var_to_reg_flt(s2, src, REG_FTMP2);
1407 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1409 store_reg_to_var_flt(iptr->dst, d);
1412 case ICMD_DMUL: /* ..., val1, val2 ==> ..., val1 * val2 */
1414 var_to_reg_flt(s1, src->prev, REG_FTMP1);
1415 var_to_reg_flt(s2, src, REG_FTMP2);
1416 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1418 store_reg_to_var_dbl(iptr->dst, d);
1421 case ICMD_FDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
1423 var_to_reg_flt(s1, src->prev, REG_FTMP1);
1424 var_to_reg_flt(s2, src, REG_FTMP2);
1425 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1427 store_reg_to_var_flt(iptr->dst, d);
1430 case ICMD_DDIV: /* ..., val1, val2 ==> ..., val1 / val2 */
1432 var_to_reg_flt(s1, src->prev, REG_FTMP1);
1433 var_to_reg_flt(s2, src, REG_FTMP2);
1434 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1436 store_reg_to_var_dbl(iptr->dst, d);
1439 case ICMD_F2I: /* ..., value ==> ..., (int) value */
1442 var_to_reg_flt(s1, src, REG_FTMP1);
1443 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1445 disp = dseg_addfloat(cd, 0.0);
1446 M_FLD(REG_FTMP2, REG_PV, disp);
1447 M_FCMPU(s1, REG_FTMP2);
1449 disp = dseg_adds4(cd, 0);
1450 M_CVTDL_C(s1, REG_FTMP1);
1451 M_LDA(REG_ITMP1, REG_PV, disp);
1452 M_STFIWX(REG_FTMP1, 0, REG_ITMP1);
1453 M_ILD(d, REG_PV, disp);
1454 store_reg_to_var_int(iptr->dst, d);
1457 case ICMD_F2D: /* ..., value ==> ..., (double) value */
1459 var_to_reg_flt(s1, src, REG_FTMP1);
1460 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1462 store_reg_to_var_dbl(iptr->dst, d);
1465 case ICMD_D2F: /* ..., value ==> ..., (double) value */
1467 var_to_reg_flt(s1, src, REG_FTMP1);
1468 d = reg_of_var(rd, iptr->dst, REG_FTMP3);
1470 store_reg_to_var_flt(iptr->dst, d);
1473 case ICMD_FCMPL: /* ..., val1, val2 ==> ..., val1 fcmpg val2 */
1476 var_to_reg_flt(s1, src->prev, REG_FTMP1);
1477 var_to_reg_flt(s2, src, REG_FTMP2);
1478 d = reg_of_var(rd, iptr->dst, REG_ITMP1);
1480 M_IADD_IMM(REG_ZERO, -1, d);
1483 M_IADD_IMM(REG_ZERO, 0, d);
1485 M_IADD_IMM(REG_ZERO, 1, d);
1486 store_reg_to_var_int(iptr->dst, d);
1489 case ICMD_FCMPG: /* ..., val1, val2 ==> ..., val1 fcmpl val2 */
1492 var_to_reg_flt(s1, src->prev, REG_FTMP1);
1493 var_to_reg_flt(s2, src, REG_FTMP2);
1494 d = reg_of_var(rd, iptr->dst, REG_ITMP1);
1496 M_IADD_IMM(REG_ZERO, 1, d);
1499 M_IADD_IMM(REG_ZERO, 0, d);
1501 M_IADD_IMM(REG_ZERO, -1, d);
1502 store_reg_to_var_int(iptr->dst, d);
1506 /* memory operations **************************************************/
1508 case ICMD_ARRAYLENGTH: /* ..., arrayref ==> ..., length */
1510 var_to_reg_int(s1, src, REG_ITMP1);
1511 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1512 gen_nullptr_check(s1);
1513 M_ILD(d, s1, OFFSET(java_arrayheader, size));
1514 store_reg_to_var_int(iptr->dst, d);
1517 case ICMD_BALOAD: /* ..., arrayref, index ==> ..., value */
1519 var_to_reg_int(s1, src->prev, REG_ITMP1);
1520 var_to_reg_int(s2, src, REG_ITMP2);
1521 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1522 if (iptr->op1 == 0) {
1523 gen_nullptr_check(s1);
1526 M_IADD_IMM(s2, OFFSET(java_chararray, data[0]), REG_ITMP2);
1527 M_LBZX(d, s1, REG_ITMP2);
1529 store_reg_to_var_int(iptr->dst, d);
1532 case ICMD_CALOAD: /* ..., arrayref, index ==> ..., value */
1534 var_to_reg_int(s1, src->prev, REG_ITMP1);
1535 var_to_reg_int(s2, src, REG_ITMP2);
1536 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1537 if (iptr->op1 == 0) {
1538 gen_nullptr_check(s1);
1541 M_SLL_IMM(s2, 1, REG_ITMP2);
1542 M_IADD_IMM(REG_ITMP2, OFFSET(java_chararray, data[0]), REG_ITMP2);
1543 M_LHZX(d, s1, REG_ITMP2);
1544 store_reg_to_var_int(iptr->dst, d);
1547 case ICMD_SALOAD: /* ..., arrayref, index ==> ..., value */
1549 var_to_reg_int(s1, src->prev, REG_ITMP1);
1550 var_to_reg_int(s2, src, REG_ITMP2);
1551 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1552 if (iptr->op1 == 0) {
1553 gen_nullptr_check(s1);
1556 M_SLL_IMM(s2, 1, REG_ITMP2);
1557 M_IADD_IMM(REG_ITMP2, OFFSET(java_shortarray, data[0]), REG_ITMP2);
1558 M_LHAX(d, s1, REG_ITMP2);
1559 store_reg_to_var_int(iptr->dst, d);
1562 case ICMD_IALOAD: /* ..., arrayref, index ==> ..., value */
1564 var_to_reg_int(s1, src->prev, REG_ITMP1);
1565 var_to_reg_int(s2, src, REG_ITMP2);
1566 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1567 if (iptr->op1 == 0) {
1568 gen_nullptr_check(s1);
1571 M_SLL_IMM(s2, 2, REG_ITMP2);
1572 M_IADD_IMM(REG_ITMP2, OFFSET(java_intarray, data[0]), REG_ITMP2);
1573 M_LWZX(d, s1, REG_ITMP2);
1574 store_reg_to_var_int(iptr->dst, d);
1577 case ICMD_LALOAD: /* ..., arrayref, index ==> ..., value */
1579 var_to_reg_int(s1, src->prev, REG_ITMP1);
1580 var_to_reg_int(s2, src, REG_ITMP2);
1581 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
1582 if (iptr->op1 == 0) {
1583 gen_nullptr_check(s1);
1586 M_SLL_IMM(s2, 3, REG_ITMP2);
1587 M_IADD(s1, REG_ITMP2, REG_ITMP2);
1588 M_ILD(GET_HIGH_REG(d), REG_ITMP2, OFFSET(java_longarray, data[0]));
1589 M_ILD(GET_LOW_REG(d), REG_ITMP2, OFFSET(java_longarray,
1591 store_reg_to_var_lng(iptr->dst, d);
1594 case ICMD_FALOAD: /* ..., arrayref, index ==> ..., value */
1596 var_to_reg_int(s1, src->prev, REG_ITMP1);
1597 var_to_reg_int(s2, src, REG_ITMP2);
1598 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
1599 if (iptr->op1 == 0) {
1600 gen_nullptr_check(s1);
1603 M_SLL_IMM(s2, 2, REG_ITMP2);
1604 M_IADD_IMM(REG_ITMP2, OFFSET(java_floatarray, data[0]), REG_ITMP2);
1605 M_LFSX(d, s1, REG_ITMP2);
1606 store_reg_to_var_flt(iptr->dst, d);
1609 case ICMD_DALOAD: /* ..., arrayref, index ==> ..., value */
1611 var_to_reg_int(s1, src->prev, REG_ITMP1);
1612 var_to_reg_int(s2, src, REG_ITMP2);
1613 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
1614 if (iptr->op1 == 0) {
1615 gen_nullptr_check(s1);
1618 M_SLL_IMM(s2, 3, REG_ITMP2);
1619 M_IADD_IMM(REG_ITMP2, OFFSET(java_doublearray, data[0]), REG_ITMP2);
1620 M_LFDX(d, s1, REG_ITMP2);
1621 store_reg_to_var_dbl(iptr->dst, d);
1624 case ICMD_AALOAD: /* ..., arrayref, index ==> ..., value */
1626 var_to_reg_int(s1, src->prev, REG_ITMP1);
1627 var_to_reg_int(s2, src, REG_ITMP2);
1628 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1629 if (iptr->op1 == 0) {
1630 gen_nullptr_check(s1);
1633 M_SLL_IMM(s2, 2, REG_ITMP2);
1634 M_IADD_IMM(REG_ITMP2, OFFSET(java_objectarray, data[0]), REG_ITMP2);
1635 M_LWZX(d, s1, REG_ITMP2);
1636 store_reg_to_var_adr(iptr->dst, d);
1640 case ICMD_BASTORE: /* ..., arrayref, index, value ==> ... */
1642 var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1643 var_to_reg_int(s2, src->prev, REG_ITMP2);
1644 if (iptr->op1 == 0) {
1645 gen_nullptr_check(s1);
1648 var_to_reg_int(s3, src, REG_ITMP3);
1649 M_IADD_IMM(s2, OFFSET(java_bytearray, data[0]), REG_ITMP2);
1650 M_STBX(s3, s1, REG_ITMP2);
1653 case ICMD_CASTORE: /* ..., arrayref, index, value ==> ... */
1655 var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1656 var_to_reg_int(s2, src->prev, REG_ITMP2);
1657 if (iptr->op1 == 0) {
1658 gen_nullptr_check(s1);
1661 var_to_reg_int(s3, src, REG_ITMP3);
1662 M_SLL_IMM(s2, 1, REG_ITMP2);
1663 M_IADD_IMM(REG_ITMP2, OFFSET(java_chararray, data[0]), REG_ITMP2);
1664 M_STHX(s3, s1, REG_ITMP2);
1667 case ICMD_SASTORE: /* ..., arrayref, index, value ==> ... */
1669 var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1670 var_to_reg_int(s2, src->prev, REG_ITMP2);
1671 if (iptr->op1 == 0) {
1672 gen_nullptr_check(s1);
1675 var_to_reg_int(s3, src, REG_ITMP3);
1676 M_SLL_IMM(s2, 1, REG_ITMP2);
1677 M_IADD_IMM(REG_ITMP2, OFFSET(java_shortarray, data[0]), REG_ITMP2);
1678 M_STHX(s3, s1, REG_ITMP2);
1681 case ICMD_IASTORE: /* ..., arrayref, index, value ==> ... */
1683 var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1684 var_to_reg_int(s2, src->prev, REG_ITMP2);
1685 if (iptr->op1 == 0) {
1686 gen_nullptr_check(s1);
1689 var_to_reg_int(s3, src, REG_ITMP3);
1690 M_SLL_IMM(s2, 2, REG_ITMP2);
1691 M_IADD_IMM(REG_ITMP2, OFFSET(java_intarray, data[0]), REG_ITMP2);
1692 M_STWX(s3, s1, REG_ITMP2);
1695 case ICMD_LASTORE: /* ..., arrayref, index, value ==> ... */
1697 var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1698 var_to_reg_int(s2, src->prev, REG_ITMP2);
1699 if (iptr->op1 == 0) {
1700 gen_nullptr_check(s1);
1703 var_to_reg_lng_high(s3, src, REG_ITMP3);
1704 M_SLL_IMM(s2, 3, REG_ITMP2);
1705 M_IADD_IMM(REG_ITMP2, OFFSET(java_longarray, data[0]), REG_ITMP2);
1706 M_STWX(s3, s1, REG_ITMP2);
1707 M_IADD_IMM(REG_ITMP2, 4, REG_ITMP2);
1708 var_to_reg_lng_low(s3, src, REG_ITMP3);
1709 M_STWX(s3, s1, REG_ITMP2);
1712 case ICMD_FASTORE: /* ..., arrayref, index, value ==> ... */
1714 var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1715 var_to_reg_int(s2, src->prev, REG_ITMP2);
1716 if (iptr->op1 == 0) {
1717 gen_nullptr_check(s1);
1720 var_to_reg_flt(s3, src, REG_FTMP3);
1721 M_SLL_IMM(s2, 2, REG_ITMP2);
1722 M_IADD_IMM(REG_ITMP2, OFFSET(java_floatarray, data[0]), REG_ITMP2);
1723 M_STFSX(s3, s1, REG_ITMP2);
1726 case ICMD_DASTORE: /* ..., arrayref, index, value ==> ... */
1728 var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1729 var_to_reg_int(s2, src->prev, REG_ITMP2);
1730 if (iptr->op1 == 0) {
1731 gen_nullptr_check(s1);
1734 var_to_reg_flt(s3, src, REG_FTMP3);
1735 M_SLL_IMM(s2, 3, REG_ITMP2);
1736 M_IADD_IMM(REG_ITMP2, OFFSET(java_doublearray, data[0]), REG_ITMP2);
1737 M_STFDX(s3, s1, REG_ITMP2);
1740 case ICMD_AASTORE: /* ..., arrayref, index, value ==> ... */
1742 var_to_reg_int(s1, src->prev->prev, rd->argintregs[0]);
1743 var_to_reg_int(s2, src->prev, REG_ITMP2);
1744 if (iptr->op1 == 0) {
1745 gen_nullptr_check(s1);
1748 var_to_reg_int(s3, src, rd->argintregs[1]);
1750 M_INTMOVE(s1, rd->argintregs[0]);
1751 M_INTMOVE(s3, rd->argintregs[1]);
1752 disp = dseg_addaddress(cd, BUILTIN_canstore);
1753 M_ALD(REG_ITMP1, REG_PV, disp);
1758 codegen_addxstorerefs(cd, mcodeptr);
1760 var_to_reg_int(s1, src->prev->prev, REG_ITMP1);
1761 var_to_reg_int(s2, src->prev, REG_ITMP2);
1762 var_to_reg_int(s3, src, REG_ITMP3);
1763 M_SLL_IMM(s2, 2, REG_ITMP2);
1764 M_IADD_IMM(REG_ITMP2, OFFSET(java_objectarray, data[0]), REG_ITMP2);
1765 M_STWX(s3, s1, REG_ITMP2);
1769 case ICMD_GETSTATIC: /* ... ==> ..., value */
1770 /* op1 = type, val.a = field address */
1773 disp = dseg_addaddress(cd, NULL);
1775 codegen_addpatchref(cd, mcodeptr,
1776 PATCHER_get_putstatic,
1777 (unresolved_field *) iptr->target, disp);
1779 if (opt_showdisassemble)
1783 fieldinfo *fi = iptr->val.a;
1785 disp = dseg_addaddress(cd, &(fi->value));
1787 if (!(fi->class->state & CLASS_INITIALIZED)) {
1788 codegen_addpatchref(cd, mcodeptr,
1789 PATCHER_clinit, fi->class, disp);
1791 if (opt_showdisassemble)
1796 M_ALD(REG_ITMP1, REG_PV, disp);
1797 switch (iptr->op1) {
1799 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1800 M_ILD_INTERN(d, REG_ITMP1, 0);
1801 store_reg_to_var_int(iptr->dst, d);
1804 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
1805 M_ILD_INTERN(GET_LOW_REG(d), REG_ITMP1, 4);/* keep this order */
1806 M_ILD_INTERN(GET_HIGH_REG(d), REG_ITMP1, 0);/*keep this order */
1807 store_reg_to_var_lng(iptr->dst, d);
1810 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1811 M_ALD_INTERN(d, REG_ITMP1, 0);
1812 store_reg_to_var_adr(iptr->dst, d);
1815 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
1816 M_FLD_INTERN(d, REG_ITMP1, 0);
1817 store_reg_to_var_flt(iptr->dst, d);
1820 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
1821 M_DLD_INTERN(d, REG_ITMP1, 0);
1822 store_reg_to_var_dbl(iptr->dst, d);
1827 case ICMD_PUTSTATIC: /* ..., value ==> ... */
1828 /* op1 = type, val.a = field address */
1832 disp = dseg_addaddress(cd, NULL);
1834 codegen_addpatchref(cd, mcodeptr,
1835 PATCHER_get_putstatic,
1836 (unresolved_field *) iptr->target, disp);
1838 if (opt_showdisassemble)
1842 fieldinfo *fi = iptr->val.a;
1844 disp = dseg_addaddress(cd, &(fi->value));
1846 if (!(fi->class->state & CLASS_INITIALIZED)) {
1847 codegen_addpatchref(cd, mcodeptr,
1848 PATCHER_clinit, fi->class, disp);
1850 if (opt_showdisassemble)
1855 M_ALD(REG_ITMP1, REG_PV, disp);
1856 switch (iptr->op1) {
1858 var_to_reg_int(s2, src, REG_ITMP2);
1859 M_IST_INTERN(s2, REG_ITMP1, 0);
1862 var_to_reg_int(s2, src, PACK_REGS(REG_ITMP2, REG_ITMP3));
1863 M_IST_INTERN(GET_HIGH_REG(s2), REG_ITMP1, 0);
1864 M_IST_INTERN(GET_LOW_REG(s2), REG_ITMP1, 4);
1867 var_to_reg_int(s2, src, REG_ITMP2);
1868 M_AST_INTERN(s2, REG_ITMP1, 0);
1871 var_to_reg_flt(s2, src, REG_FTMP2);
1872 M_FST_INTERN(s2, REG_ITMP1, 0);
1875 var_to_reg_flt(s2, src, REG_FTMP2);
1876 M_DST_INTERN(s2, REG_ITMP1, 0);
1882 case ICMD_GETFIELD: /* ... ==> ..., value */
1883 /* op1 = type, val.i = field offset */
1885 var_to_reg_int(s1, src, REG_ITMP1);
1886 gen_nullptr_check(s1);
1889 codegen_addpatchref(cd, mcodeptr,
1890 PATCHER_get_putfield,
1891 (unresolved_field *) iptr->target, 0);
1893 if (opt_showdisassemble)
1899 disp = ((fieldinfo *) (iptr->val.a))->offset;
1902 switch (iptr->op1) {
1904 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1906 store_reg_to_var_int(iptr->dst, d);
1909 d = reg_of_var(rd, iptr->dst, PACK_REGS(REG_ITMP2, REG_ITMP1));
1910 if (GET_HIGH_REG(d) == s1) {
1911 M_ILD(GET_LOW_REG(d), s1, disp + 4);
1912 M_ILD(GET_HIGH_REG(d), s1, disp);
1914 M_ILD(GET_HIGH_REG(d), s1, disp);
1915 M_ILD(GET_LOW_REG(d), s1, disp + 4);
1917 store_reg_to_var_lng(iptr->dst, d);
1920 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
1922 store_reg_to_var_adr(iptr->dst, d);
1925 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
1927 store_reg_to_var_flt(iptr->dst, d);
1930 d = reg_of_var(rd, iptr->dst, REG_FTMP1);
1932 store_reg_to_var_dbl(iptr->dst, d);
1937 case ICMD_PUTFIELD: /* ..., value ==> ... */
1938 /* op1 = type, val.i = field offset */
1940 var_to_reg_int(s1, src->prev, REG_ITMP1);
1941 gen_nullptr_check(s1);
1943 if (!IS_FLT_DBL_TYPE(iptr->op1)) {
1944 if (IS_2_WORD_TYPE(iptr->op1)) {
1945 var_to_reg_int(s2, src, PACK_REGS(REG_ITMP2, REG_ITMP3));
1947 var_to_reg_int(s2, src, REG_ITMP2);
1950 var_to_reg_flt(s2, src, REG_FTMP2);
1954 codegen_addpatchref(cd, mcodeptr,
1955 PATCHER_get_putfield,
1956 (unresolved_field *) iptr->target, 0);
1958 if (opt_showdisassemble)
1964 disp = ((fieldinfo *) (iptr->val.a))->offset;
1967 switch (iptr->op1) {
1969 M_IST(s2, s1, disp);
1972 M_IST(GET_LOW_REG(s2), s1, disp + 4); /* keep this order */
1973 M_IST(GET_HIGH_REG(s2), s1, disp); /* keep this order */
1976 M_AST(s2, s1, disp);
1979 M_FST(s2, s1, disp);
1982 M_DST(s2, s1, disp);
1988 /* branch operations **************************************************/
1990 case ICMD_ATHROW: /* ..., objectref ==> ... (, objectref) */
1992 var_to_reg_int(s1, src, REG_ITMP1);
1993 M_INTMOVE(s1, REG_ITMP1_XPTR);
1995 #ifdef ENABLE_VERIFIER
1997 codegen_addpatchref(cd, mcodeptr,
1998 PATCHER_athrow_areturn,
1999 (unresolved_class *) iptr->val.a, 0);
2001 if (opt_showdisassemble)
2004 #endif /* ENABLE_VERIFIER */
2006 disp = dseg_addaddress(cd, asm_handle_exception);
2007 M_ALD(REG_ITMP2, REG_PV, disp);
2010 if (m->isleafmethod) M_MFLR(REG_ITMP3); /* save LR */
2011 M_BL(0); /* get current PC */
2012 M_MFLR(REG_ITMP2_XPC);
2013 if (m->isleafmethod) M_MTLR(REG_ITMP3); /* restore LR */
2014 M_RTS; /* jump to CTR */
2019 case ICMD_GOTO: /* ... ==> ... */
2020 /* op1 = target JavaVM pc */
2022 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2026 case ICMD_JSR: /* ... ==> ... */
2027 /* op1 = target JavaVM pc */
2029 if (m->isleafmethod) M_MFLR(REG_ITMP2);
2032 M_IADD_IMM(REG_ITMP1, m->isleafmethod ? 16 : 12, REG_ITMP1);
2033 if (m->isleafmethod) M_MTLR(REG_ITMP2);
2035 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2038 case ICMD_RET: /* ... ==> ... */
2039 /* op1 = local variable */
2041 var = &(rd->locals[iptr->op1][TYPE_ADR]);
2042 if (var->flags & INMEMORY) {
2043 M_ALD(REG_ITMP1, REG_SP, var->regoff * 4);
2046 M_MTCTR(var->regoff);
2052 case ICMD_IFNULL: /* ..., value ==> ... */
2053 /* op1 = target JavaVM pc */
2055 var_to_reg_int(s1, src, REG_ITMP1);
2058 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2061 case ICMD_IFNONNULL: /* ..., value ==> ... */
2062 /* op1 = target JavaVM pc */
2064 var_to_reg_int(s1, src, REG_ITMP1);
2067 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2075 case ICMD_IFEQ: /* ..., value ==> ... */
2076 /* op1 = target JavaVM pc, val.i = constant */
2078 var_to_reg_int(s1, src, REG_ITMP1);
2079 if ((iptr->val.i >= -32768) && (iptr->val.i <= 32767)) {
2080 M_CMPI(s1, iptr->val.i);
2082 ICONST(REG_ITMP2, iptr->val.i);
2083 M_CMP(s1, REG_ITMP2);
2085 switch (iptr->opc) {
2105 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2109 case ICMD_IF_LEQ: /* ..., value ==> ... */
2110 /* op1 = target JavaVM pc, val.l = constant */
2112 var_to_reg_lng_low(s1, src, REG_ITMP1);
2113 var_to_reg_lng_high(s2, src, REG_ITMP2);
2114 if (iptr->val.l == 0) {
2115 M_OR_TST(s1, s2, REG_ITMP3);
2116 } else if ((iptr->val.l >= 0) && (iptr->val.l <= 0xffff)) {
2117 M_XOR_IMM(s2, 0, REG_ITMP2);
2118 M_XOR_IMM(s1, iptr->val.l & 0xffff, REG_ITMP1);
2119 M_OR_TST(REG_ITMP1, REG_ITMP2, REG_ITMP3);
2121 ICONST(REG_ITMP3, iptr->val.l & 0xffffffff);
2122 M_XOR(s1, REG_ITMP3, REG_ITMP1);
2123 ICONST(REG_ITMP3, iptr->val.l >> 32);
2124 M_XOR(s2, REG_ITMP3, REG_ITMP2);
2125 M_OR_TST(REG_ITMP1, REG_ITMP2, REG_ITMP3);
2128 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2131 case ICMD_IF_LLT: /* ..., value ==> ... */
2132 /* op1 = target JavaVM pc, val.l = constant */
2133 var_to_reg_lng_low(s1, src, REG_ITMP1);
2134 var_to_reg_lng_high(s2, src, REG_ITMP2);
2135 if (iptr->val.l == 0) {
2136 /* if high word is less than zero, the whole long is too */
2138 } else if ((iptr->val.l >= 0) && (iptr->val.l <= 0xffff)) {
2141 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2143 M_CMPUI(s1, iptr->val.l & 0xffff);
2145 ICONST(REG_ITMP3, iptr->val.l >> 32);
2146 M_CMP(s2, REG_ITMP3);
2148 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2150 ICONST(REG_ITMP3, iptr->val.l & 0xffffffff);
2151 M_CMPU(s1, REG_ITMP3);
2154 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2157 case ICMD_IF_LLE: /* ..., value ==> ... */
2158 /* op1 = target JavaVM pc, val.l = constant */
2160 var_to_reg_lng_low(s1, src, REG_ITMP1);
2161 var_to_reg_lng_high(s2, src, REG_ITMP2);
2162 /* if (iptr->val.l == 0) { */
2163 /* M_OR(s1, s2, REG_ITMP3); */
2164 /* M_CMPI(REG_ITMP3, 0); */
2167 if ((iptr->val.l >= 0) && (iptr->val.l <= 0xffff)) {
2170 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2172 M_CMPUI(s1, iptr->val.l & 0xffff);
2174 ICONST(REG_ITMP3, iptr->val.l >> 32);
2175 M_CMP(s2, REG_ITMP3);
2177 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2179 ICONST(REG_ITMP3, iptr->val.l & 0xffffffff);
2180 M_CMPU(s1, REG_ITMP3);
2183 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2186 case ICMD_IF_LNE: /* ..., value ==> ... */
2187 /* op1 = target JavaVM pc, val.l = constant */
2189 var_to_reg_lng_low(s1, src, REG_ITMP1);
2190 var_to_reg_lng_high(s2, src, REG_ITMP2);
2191 if (iptr->val.l == 0) {
2192 M_OR_TST(s1, s2, REG_ITMP3);
2193 } else if ((iptr->val.l >= 0) && (iptr->val.l <= 0xffff)) {
2194 M_XOR_IMM(s2, 0, REG_ITMP2);
2195 M_XOR_IMM(s1, iptr->val.l & 0xffff, REG_ITMP1);
2196 M_OR_TST(REG_ITMP1, REG_ITMP2, REG_ITMP3);
2198 ICONST(REG_ITMP3, iptr->val.l & 0xffffffff);
2199 M_XOR(s1, REG_ITMP3, REG_ITMP1);
2200 ICONST(REG_ITMP3, iptr->val.l >> 32);
2201 M_XOR(s2, REG_ITMP3, REG_ITMP2);
2202 M_OR_TST(REG_ITMP1, REG_ITMP2, REG_ITMP3);
2205 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2208 case ICMD_IF_LGT: /* ..., value ==> ... */
2209 /* op1 = target JavaVM pc, val.l = constant */
2211 var_to_reg_lng_low(s1, src, REG_ITMP1);
2212 var_to_reg_lng_high(s2, src, REG_ITMP2);
2213 /* if (iptr->val.l == 0) { */
2214 /* M_OR(s1, s2, REG_ITMP3); */
2215 /* M_CMPI(REG_ITMP3, 0); */
2218 if ((iptr->val.l >= 0) && (iptr->val.l <= 0xffff)) {
2221 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2223 M_CMPUI(s1, iptr->val.l & 0xffff);
2225 ICONST(REG_ITMP3, iptr->val.l >> 32);
2226 M_CMP(s2, REG_ITMP3);
2228 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2230 ICONST(REG_ITMP3, iptr->val.l & 0xffffffff);
2231 M_CMPU(s1, REG_ITMP3);
2234 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2237 case ICMD_IF_LGE: /* ..., value ==> ... */
2238 /* op1 = target JavaVM pc, val.l = constant */
2239 var_to_reg_lng_low(s1, src, REG_ITMP1);
2240 var_to_reg_lng_high(s2, src, REG_ITMP2);
2241 if (iptr->val.l == 0) {
2242 /* if high word is greater equal zero, the whole long is too */
2244 } else if ((iptr->val.l >= 0) && (iptr->val.l <= 0xffff)) {
2247 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2249 M_CMPUI(s1, iptr->val.l & 0xffff);
2251 ICONST(REG_ITMP3, iptr->val.l >> 32);
2252 M_CMP(s2, REG_ITMP3);
2254 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2256 ICONST(REG_ITMP3, iptr->val.l & 0xffffffff);
2257 M_CMPU(s1, REG_ITMP3);
2260 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2263 case ICMD_IF_ICMPEQ: /* ..., value, value ==> ... */
2264 case ICMD_IF_ACMPEQ: /* op1 = target JavaVM pc */
2266 var_to_reg_int(s1, src->prev, REG_ITMP1);
2267 var_to_reg_int(s2, src, REG_ITMP2);
2270 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2273 case ICMD_IF_LCMPEQ: /* ..., value, value ==> ... */
2274 /* op1 = target JavaVM pc */
2276 var_to_reg_lng_high(s1, src->prev, REG_ITMP1);
2277 var_to_reg_lng_high(s2, src, REG_ITMP2);
2279 /* load low-bits before the branch, so we know the distance */
2280 var_to_reg_lng_low(s1, src->prev, REG_ITMP1);
2281 var_to_reg_lng_low(s2, src, REG_ITMP2);
2285 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2288 case ICMD_IF_ICMPNE: /* ..., value, value ==> ... */
2289 case ICMD_IF_ACMPNE: /* op1 = target JavaVM pc */
2291 var_to_reg_int(s1, src->prev, REG_ITMP1);
2292 var_to_reg_int(s2, src, REG_ITMP2);
2295 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2298 case ICMD_IF_LCMPNE: /* ..., value, value ==> ... */
2299 /* op1 = target JavaVM pc */
2301 var_to_reg_lng_high(s1, src->prev, REG_ITMP1);
2302 var_to_reg_lng_high(s2, src, REG_ITMP2);
2305 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2306 var_to_reg_lng_low(s1, src->prev, REG_ITMP1);
2307 var_to_reg_lng_low(s2, src, REG_ITMP2);
2310 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2313 case ICMD_IF_ICMPLT: /* ..., value, value ==> ... */
2314 /* op1 = target JavaVM pc */
2316 var_to_reg_int(s1, src->prev, REG_ITMP1);
2317 var_to_reg_int(s2, src, REG_ITMP2);
2320 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2323 case ICMD_IF_LCMPLT: /* ..., value, value ==> ... */
2324 /* op1 = target JavaVM pc */
2326 var_to_reg_lng_high(s1, src->prev, REG_ITMP1);
2327 var_to_reg_lng_high(s2, src, REG_ITMP2);
2330 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2331 /* load low-bits before the branch, so we know the distance */
2332 var_to_reg_lng_low(s1, src->prev, REG_ITMP1);
2333 var_to_reg_lng_low(s2, src, REG_ITMP2);
2337 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2340 case ICMD_IF_ICMPGT: /* ..., value, value ==> ... */
2341 /* op1 = target JavaVM pc */
2343 var_to_reg_int(s1, src->prev, REG_ITMP1);
2344 var_to_reg_int(s2, src, REG_ITMP2);
2347 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2350 case ICMD_IF_LCMPGT: /* ..., value, value ==> ... */
2351 /* op1 = target JavaVM pc */
2353 var_to_reg_lng_high(s1, src->prev, REG_ITMP1);
2354 var_to_reg_lng_high(s2, src, REG_ITMP2);
2357 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2358 /* load low-bits before the branch, so we know the distance */
2359 var_to_reg_lng_low(s1, src->prev, REG_ITMP1);
2360 var_to_reg_lng_low(s2, src, REG_ITMP2);
2364 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2367 case ICMD_IF_ICMPLE: /* ..., value, value ==> ... */
2368 /* op1 = target JavaVM pc */
2370 var_to_reg_int(s1, src->prev, REG_ITMP1);
2371 var_to_reg_int(s2, src, REG_ITMP2);
2374 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2377 case ICMD_IF_LCMPLE: /* ..., value, value ==> ... */
2378 /* op1 = target JavaVM pc */
2380 var_to_reg_lng_high(s1, src->prev, REG_ITMP1);
2381 var_to_reg_lng_high(s2, src, REG_ITMP2);
2384 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2385 /* load low-bits before the branch, so we know the distance */
2386 var_to_reg_lng_low(s1, src->prev, REG_ITMP1);
2387 var_to_reg_lng_low(s2, src, REG_ITMP2);
2391 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2394 case ICMD_IF_ICMPGE: /* ..., value, value ==> ... */
2395 /* op1 = target JavaVM pc */
2397 var_to_reg_int(s1, src->prev, REG_ITMP1);
2398 var_to_reg_int(s2, src, REG_ITMP2);
2401 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2404 case ICMD_IF_LCMPGE: /* ..., value, value ==> ... */
2405 /* op1 = target JavaVM pc */
2407 var_to_reg_lng_high(s1, src->prev, REG_ITMP1);
2408 var_to_reg_lng_high(s2, src, REG_ITMP2);
2411 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2412 /* load low-bits before the branch, so we know the distance */
2413 var_to_reg_lng_low(s1, src->prev, REG_ITMP1);
2414 var_to_reg_lng_low(s2, src, REG_ITMP2);
2418 codegen_addreference(cd, (basicblock *) iptr->target, mcodeptr);
2421 case ICMD_IRETURN: /* ..., retvalue ==> ... */
2423 var_to_reg_int(s1, src, REG_RESULT);
2424 M_TINTMOVE(src->type, s1, REG_RESULT);
2425 goto nowperformreturn;
2427 case ICMD_ARETURN: /* ..., retvalue ==> ... */
2429 var_to_reg_int(s1, src, REG_RESULT);
2430 M_TINTMOVE(src->type, s1, REG_RESULT);
2432 #ifdef ENABLE_VERIFIER
2434 codegen_addpatchref(cd, mcodeptr,
2435 PATCHER_athrow_areturn,
2436 (unresolved_class *) iptr->val.a, 0);
2438 if (opt_showdisassemble)
2441 #endif /* ENABLE_VERIFIER */
2442 goto nowperformreturn;
2444 case ICMD_LRETURN: /* ..., retvalue ==> ... */
2446 var_to_reg_int(s1, src, PACK_REGS(REG_RESULT2, REG_RESULT));
2447 M_TINTMOVE(src->type, s1, PACK_REGS(REG_RESULT2, REG_RESULT));
2448 goto nowperformreturn;
2450 case ICMD_FRETURN: /* ..., retvalue ==> ... */
2453 var_to_reg_flt(s1, src, REG_FRESULT);
2454 M_FLTMOVE(s1, REG_FRESULT);
2455 goto nowperformreturn;
2457 case ICMD_RETURN: /* ... ==> ... */
2463 p = parentargs_base;
2465 /* call trace function */
2469 M_LDA(REG_SP, REG_SP, -10 * 8);
2470 M_DST(REG_FRESULT, REG_SP, 48+0);
2471 M_IST(REG_RESULT, REG_SP, 48+8);
2472 M_AST(REG_ZERO, REG_SP, 48+12);
2473 M_IST(REG_RESULT2, REG_SP, 48+16);
2475 /* keep this order */
2476 switch (iptr->opc) {
2479 #if defined(__DARWIN__)
2480 M_MOV(REG_RESULT, rd->argintregs[2]);
2481 M_CLR(rd->argintregs[1]);
2483 M_MOV(REG_RESULT, rd->argintregs[3]);
2484 M_CLR(rd->argintregs[2]);
2489 #if defined(__DARWIN__)
2490 M_MOV(REG_RESULT2, rd->argintregs[2]);
2491 M_MOV(REG_RESULT, rd->argintregs[1]);
2493 M_MOV(REG_RESULT2, rd->argintregs[3]);
2494 M_MOV(REG_RESULT, rd->argintregs[2]);
2499 disp = dseg_addaddress(cd, m);
2500 M_ALD(rd->argintregs[0], REG_PV, disp);
2502 M_FLTMOVE(REG_FRESULT, rd->argfltregs[0]);
2503 M_FLTMOVE(REG_FRESULT, rd->argfltregs[1]);
2504 disp = dseg_addaddress(cd, builtin_displaymethodstop);
2505 M_ALD(REG_ITMP2, REG_PV, disp);
2509 M_DLD(REG_FRESULT, REG_SP, 48+0);
2510 M_ILD(REG_RESULT, REG_SP, 48+8);
2511 M_ALD(REG_ZERO, REG_SP, 48+12);
2512 M_ILD(REG_RESULT2, REG_SP, 48+16);
2513 M_LDA(REG_SP, REG_SP, 10 * 8);
2517 #if defined(USE_THREADS)
2518 if (checksync && (m->flags & ACC_SYNCHRONIZED)) {
2519 /* we need to save the proper return value */
2520 switch (iptr->opc) {
2522 M_IST(REG_RESULT2, REG_SP, rd->memuse * 4 + 8);
2526 M_IST(REG_RESULT , REG_SP, rd->memuse * 4 + 4);
2529 M_FST(REG_FRESULT, REG_SP, rd->memuse * 4 + 4);
2532 M_DST(REG_FRESULT, REG_SP, rd->memuse * 4 + 4);
2536 disp = dseg_addaddress(cd, BUILTIN_monitorexit);
2537 M_ALD(REG_ITMP3, REG_PV, disp);
2539 M_ALD(rd->argintregs[0], REG_SP, rd->memuse * 4);
2542 /* and now restore the proper return value */
2543 switch (iptr->opc) {
2545 M_ILD(REG_RESULT2, REG_SP, rd->memuse * 4 + 8);
2549 M_ILD(REG_RESULT , REG_SP, rd->memuse * 4 + 4);
2552 M_FLD(REG_FRESULT, REG_SP, rd->memuse * 4 + 4);
2555 M_DLD(REG_FRESULT, REG_SP, rd->memuse * 4 + 4);
2561 /* restore return address */
2563 if (!m->isleafmethod) {
2564 M_ALD(REG_ZERO, REG_SP, p * 4 + LA_LR_OFFSET);
2568 /* restore saved registers */
2570 for (i = INT_SAV_CNT - 1; i >= rd->savintreguse; i--) {
2571 p--; M_ILD(rd->savintregs[i], REG_SP, p * 4);
2573 for (i = FLT_SAV_CNT - 1; i >= rd->savfltreguse; i--) {
2574 p -= 2; M_DLD(rd->savfltregs[i], REG_SP, p * 4);
2577 /* deallocate stack */
2579 if (parentargs_base)
2580 M_LDA(REG_SP, REG_SP, parentargs_base * 4);
2588 case ICMD_TABLESWITCH: /* ..., index ==> ... */
2593 tptr = (void **) iptr->target;
2595 s4ptr = iptr->val.a;
2596 l = s4ptr[1]; /* low */
2597 i = s4ptr[2]; /* high */
2599 var_to_reg_int(s1, src, REG_ITMP1);
2601 M_INTMOVE(s1, REG_ITMP1);
2602 } else if (l <= 32768) {
2603 M_LDA(REG_ITMP1, s1, -l);
2605 ICONST(REG_ITMP2, l);
2606 M_ISUB(s1, REG_ITMP2, REG_ITMP1);
2612 M_CMPUI(REG_ITMP1, i - 1);
2614 codegen_addreference(cd, (basicblock *) tptr[0], mcodeptr);
2616 /* build jump table top down and use address of lowest entry */
2618 /* s4ptr += 3 + i; */
2622 dseg_addtarget(cd, (basicblock *) tptr[0]);
2627 /* length of dataseg after last dseg_addtarget is used by load */
2629 M_SLL_IMM(REG_ITMP1, 2, REG_ITMP1);
2630 M_IADD(REG_ITMP1, REG_PV, REG_ITMP2);
2631 M_ALD(REG_ITMP2, REG_ITMP2, -(cd->dseglen));
2638 case ICMD_LOOKUPSWITCH: /* ..., key ==> ... */
2640 s4 i, l, val, *s4ptr;
2643 tptr = (void **) iptr->target;
2645 s4ptr = iptr->val.a;
2646 l = s4ptr[0]; /* default */
2647 i = s4ptr[1]; /* count */
2649 MCODECHECK((i<<2)+8);
2650 var_to_reg_int(s1, src, REG_ITMP1);
2656 if ((val >= -32768) && (val <= 32767)) {
2659 a = dseg_adds4(cd, val);
2660 M_ILD(REG_ITMP2, REG_PV, a);
2661 M_CMP(s1, REG_ITMP2);
2664 codegen_addreference(cd, (basicblock *) tptr[0], mcodeptr);
2668 tptr = (void **) iptr->target;
2669 codegen_addreference(cd, (basicblock *) tptr[0], mcodeptr);
2676 case ICMD_BUILTIN: /* ..., [arg1, [arg2 ...]] ==> ... */
2677 /* op1 = arg count val.a = builtintable entry */
2683 case ICMD_INVOKESTATIC: /* ..., [arg1, [arg2 ...]] ==> ... */
2684 /* op1 = arg count, val.a = method pointer */
2686 case ICMD_INVOKESPECIAL:/* ..., objectref, [arg1, [arg2 ...]] ==> ... */
2687 case ICMD_INVOKEVIRTUAL:/* op1 = arg count, val.a = method pointer */
2688 case ICMD_INVOKEINTERFACE:
2693 unresolved_method *um = iptr->target;
2694 md = um->methodref->parseddesc.md;
2696 md = lm->parseddesc;
2700 s3 = md->paramcount;
2702 MCODECHECK((s3 << 1) + 64);
2704 /* copy arguments to registers or stack location */
2706 for (s3 = s3 - 1; s3 >= 0; s3--, src = src->prev) {
2707 if (src->varkind == ARGVAR)
2709 if (IS_INT_LNG_TYPE(src->type)) {
2710 if (!md->params[s3].inmemory) {
2711 if (IS_2_WORD_TYPE(src->type)) {
2713 rd->argintregs[GET_LOW_REG(md->params[s3].regoff)],
2714 rd->argintregs[GET_HIGH_REG(md->params[s3].regoff)]);
2716 s1 = rd->argintregs[md->params[s3].regoff];
2718 var_to_reg_int(d, src, s1);
2719 M_TINTMOVE(src->type, d, s1);
2721 if (IS_2_WORD_TYPE(src->type)) {
2722 var_to_reg_int(d, src, PACK_REGS(REG_ITMP2, REG_ITMP1));
2723 M_IST(GET_HIGH_REG(d), REG_SP,
2724 md->params[s3].regoff * 4);
2725 M_IST(GET_LOW_REG(d), REG_SP,
2726 md->params[s3].regoff * 4 + 4);
2728 var_to_reg_int(d, src, REG_ITMP1);
2729 M_IST(d, REG_SP, md->params[s3].regoff * 4);
2734 if (!md->params[s3].inmemory) {
2735 s1 = rd->argfltregs[md->params[s3].regoff];
2736 var_to_reg_flt(d, src, s1);
2739 var_to_reg_flt(d, src, REG_FTMP1);
2740 if (IS_2_WORD_TYPE(src->type)) {
2741 M_DST(d, REG_SP, md->params[s3].regoff * 4);
2743 M_FST(d, REG_SP, md->params[s3].regoff * 4);
2749 switch (iptr->opc) {
2751 disp = dseg_addaddress(cd, bte->fp);
2752 d = md->returntype.type;
2754 M_ALD(REG_PV, REG_PV, disp); /* pointer to built-in-function */
2757 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
2759 M_LDA(REG_PV, REG_ITMP1, -disp);
2761 /* if op1 == true, we need to check for an exception */
2763 if (iptr->op1 == true) {
2764 M_CMPI(REG_RESULT, 0);
2766 codegen_addxexceptionrefs(cd, mcodeptr);
2770 case ICMD_INVOKESPECIAL:
2771 gen_nullptr_check(rd->argintregs[0]);
2772 M_ILD(REG_ITMP1, rd->argintregs[0], 0); /* hardware nullptr */
2775 case ICMD_INVOKESTATIC:
2777 unresolved_method *um = iptr->target;
2779 disp = dseg_addaddress(cd, NULL);
2781 codegen_addpatchref(cd, mcodeptr,
2782 PATCHER_invokestatic_special, um, disp);
2784 if (opt_showdisassemble)
2787 d = md->returntype.type;
2790 disp = dseg_addaddress(cd, lm->stubroutine);
2791 d = md->returntype.type;
2794 M_ALD(REG_PV, REG_PV, disp);
2797 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
2799 M_LDA(REG_PV, REG_ITMP1, -disp);
2802 case ICMD_INVOKEVIRTUAL:
2803 gen_nullptr_check(rd->argintregs[0]);
2806 unresolved_method *um = iptr->target;
2808 codegen_addpatchref(cd, mcodeptr,
2809 PATCHER_invokevirtual, um, 0);
2811 if (opt_showdisassemble)
2815 d = md->returntype.type;
2818 s1 = OFFSET(vftbl_t, table[0]) +
2819 sizeof(methodptr) * lm->vftblindex;
2820 d = md->returntype.type;
2823 M_ALD(REG_METHODPTR, rd->argintregs[0],
2824 OFFSET(java_objectheader, vftbl));
2825 M_ALD(REG_PV, REG_METHODPTR, s1);
2828 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
2830 M_LDA(REG_PV, REG_ITMP1, -disp);
2833 case ICMD_INVOKEINTERFACE:
2834 gen_nullptr_check(rd->argintregs[0]);
2837 unresolved_method *um = iptr->target;
2839 codegen_addpatchref(cd, mcodeptr,
2840 PATCHER_invokeinterface, um, 0);
2842 if (opt_showdisassemble)
2847 d = md->returntype.type;
2850 s1 = OFFSET(vftbl_t, interfacetable[0]) -
2851 sizeof(methodptr*) * lm->class->index;
2853 s2 = sizeof(methodptr) * (lm - lm->class->methods);
2855 d = md->returntype.type;
2858 M_ALD(REG_METHODPTR, rd->argintregs[0],
2859 OFFSET(java_objectheader, vftbl));
2860 M_ALD(REG_METHODPTR, REG_METHODPTR, s1);
2861 M_ALD(REG_PV, REG_METHODPTR, s2);
2864 disp = (s4) ((u1 *) mcodeptr - cd->mcodebase);
2866 M_LDA(REG_PV, REG_ITMP1, -disp);
2870 /* d contains return type */
2872 if (d != TYPE_VOID) {
2873 if (IS_INT_LNG_TYPE(iptr->dst->type)) {
2874 if (IS_2_WORD_TYPE(iptr->dst->type)) {
2875 s1 = reg_of_var(rd, iptr->dst,
2876 PACK_REGS(REG_RESULT2, REG_RESULT));
2877 M_TINTMOVE(iptr->dst->type,
2878 PACK_REGS(REG_RESULT2, REG_RESULT), s1);
2879 store_reg_to_var_lng(iptr->dst, s1);
2881 s1 = reg_of_var(rd, iptr->dst, REG_RESULT);
2882 M_TINTMOVE(iptr->dst->type, REG_RESULT, s1);
2883 store_reg_to_var_int(iptr->dst, s1);
2886 s1 = reg_of_var(rd, iptr->dst, REG_FRESULT);
2887 M_FLTMOVE(REG_FRESULT, s1);
2888 if (IS_2_WORD_TYPE(iptr->dst->type)) {
2889 store_reg_to_var_dbl(iptr->dst, s1);
2891 store_reg_to_var_flt(iptr->dst, s1);
2898 case ICMD_CHECKCAST: /* ..., objectref ==> ..., objectref */
2899 /* op1: 0 == array, 1 == class */
2900 /* val.a: (classinfo*) superclass */
2902 /* superclass is an interface:
2904 * OK if ((sub == NULL) ||
2905 * (sub->vftbl->interfacetablelength > super->index) &&
2906 * (sub->vftbl->interfacetable[-super->index] != NULL));
2908 * superclass is a class:
2910 * OK if ((sub == NULL) || (0
2911 * <= (sub->vftbl->baseval - super->vftbl->baseval) <=
2912 * super->vftbl->diffvall));
2915 if (iptr->op1 == 1) {
2916 /* object type cast-check */
2919 vftbl_t *supervftbl;
2922 super = (classinfo *) iptr->val.a;
2929 superindex = super->index;
2930 supervftbl = super->vftbl;
2933 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
2934 codegen_threadcritrestart(cd, (u1 *) mcodeptr - cd->mcodebase);
2936 var_to_reg_int(s1, src, REG_ITMP1);
2938 /* calculate interface checkcast code size */
2942 s2 += (opt_showdisassemble ? 1 : 0);
2944 /* calculate class checkcast code size */
2946 s3 = 8 + (s1 == REG_ITMP1);
2948 s3 += (opt_showdisassemble ? 1 : 0);
2950 /* if class is not resolved, check which code to call */
2954 M_BEQ(3 + (opt_showdisassemble ? 1 : 0) + s2 + 1 + s3);
2956 disp = dseg_adds4(cd, 0); /* super->flags */
2958 codegen_addpatchref(cd, mcodeptr,
2959 PATCHER_checkcast_instanceof_flags,
2960 (constant_classref *) iptr->target, disp);
2962 if (opt_showdisassemble)
2965 M_ILD(REG_ITMP2, REG_PV, disp);
2966 M_AND_IMM(REG_ITMP2, ACC_INTERFACE, REG_ITMP2);
2970 /* interface checkcast code */
2972 if (!super || (super->flags & ACC_INTERFACE)) {
2978 codegen_addpatchref(cd, mcodeptr,
2979 PATCHER_checkcast_instanceof_interface,
2980 (constant_classref *) iptr->target, 0);
2982 if (opt_showdisassemble)
2986 M_ALD(REG_ITMP2, s1, OFFSET(java_objectheader, vftbl));
2987 M_ILD(REG_ITMP3, REG_ITMP2, OFFSET(vftbl_t, interfacetablelength));
2988 M_LDATST(REG_ITMP3, REG_ITMP3, -superindex);
2990 codegen_addxcastrefs(cd, mcodeptr);
2991 M_ALD(REG_ITMP3, REG_ITMP2,
2992 OFFSET(vftbl_t, interfacetable[0]) -
2993 superindex * sizeof(methodptr*));
2996 codegen_addxcastrefs(cd, mcodeptr);
3002 /* class checkcast code */
3004 if (!super || !(super->flags & ACC_INTERFACE)) {
3005 disp = dseg_addaddress(cd, supervftbl);
3012 codegen_addpatchref(cd, mcodeptr,
3013 PATCHER_checkcast_class,
3014 (constant_classref *) iptr->target,
3017 if (opt_showdisassemble)
3021 M_ALD(REG_ITMP2, s1, OFFSET(java_objectheader, vftbl));
3022 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3023 codegen_threadcritstart(cd, (u1 *) mcodeptr - cd->mcodebase);
3025 M_ILD(REG_ITMP3, REG_ITMP2, OFFSET(vftbl_t, baseval));
3026 M_ALD(REG_ITMP2, REG_PV, disp);
3027 if (s1 != REG_ITMP1) {
3028 M_ILD(REG_ITMP1, REG_ITMP2, OFFSET(vftbl_t, baseval));
3029 M_ILD(REG_ITMP2, REG_ITMP2, OFFSET(vftbl_t, diffval));
3030 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3031 codegen_threadcritstop(cd, (u1 *) mcodeptr - cd->mcodebase);
3033 M_ISUB(REG_ITMP3, REG_ITMP1, REG_ITMP3);
3035 M_ILD(REG_ITMP2, REG_ITMP2, OFFSET(vftbl_t, baseval));
3036 M_ISUB(REG_ITMP3, REG_ITMP2, REG_ITMP3);
3037 M_ALD(REG_ITMP2, REG_PV, disp);
3038 M_ILD(REG_ITMP2, REG_ITMP2, OFFSET(vftbl_t, diffval));
3039 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3040 codegen_threadcritstop(cd, (u1 *) mcodeptr - cd->mcodebase);
3043 M_CMPU(REG_ITMP3, REG_ITMP2);
3045 codegen_addxcastrefs(cd, mcodeptr);
3047 d = reg_of_var(rd, iptr->dst, s1);
3050 /* array type cast-check */
3052 var_to_reg_int(s1, src, rd->argintregs[0]);
3053 M_INTMOVE(s1, rd->argintregs[0]);
3055 disp = dseg_addaddress(cd, iptr->val.a);
3057 if (iptr->val.a == NULL) {
3058 codegen_addpatchref(cd, mcodeptr,
3059 PATCHER_builtin_arraycheckcast,
3060 (constant_classref *) iptr->target,
3063 if (opt_showdisassemble)
3067 M_ALD(rd->argintregs[1], REG_PV, disp);
3068 disp = dseg_addaddress(cd, BUILTIN_arraycheckcast);
3069 M_ALD(REG_ITMP2, REG_PV, disp);
3074 codegen_addxcastrefs(cd, mcodeptr);
3076 var_to_reg_int(s1, src, REG_ITMP1);
3077 d = reg_of_var(rd, iptr->dst, s1);
3080 store_reg_to_var_adr(iptr->dst, d);
3083 case ICMD_INSTANCEOF: /* ..., objectref ==> ..., intresult */
3084 /* val.a: (classinfo*) superclass */
3086 /* superclass is an interface:
3088 * return (sub != NULL) &&
3089 * (sub->vftbl->interfacetablelength > super->index) &&
3090 * (sub->vftbl->interfacetable[-super->index] != NULL);
3092 * superclass is a class:
3094 * return ((sub != NULL) && (0
3095 * <= (sub->vftbl->baseval - super->vftbl->baseval) <=
3096 * super->vftbl->diffvall));
3101 vftbl_t *supervftbl;
3104 super = (classinfo *) iptr->val.a;
3111 superindex = super->index;
3112 supervftbl = super->vftbl;
3115 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3116 codegen_threadcritrestart(cd, (u1*) mcodeptr - cd->mcodebase);
3118 var_to_reg_int(s1, src, REG_ITMP1);
3119 d = reg_of_var(rd, iptr->dst, REG_ITMP2);
3121 M_MOV(s1, REG_ITMP1);
3125 /* calculate interface instanceof code size */
3129 s2 += (opt_showdisassemble ? 1 : 0);
3131 /* calculate class instanceof code size */
3135 s3 += (opt_showdisassemble ? 1 : 0);
3139 /* if class is not resolved, check which code to call */
3143 M_BEQ(3 + (opt_showdisassemble ? 1 : 0) + s2 + 1 + s3);
3145 disp = dseg_adds4(cd, 0); /* super->flags */
3147 codegen_addpatchref(cd, mcodeptr,
3148 PATCHER_checkcast_instanceof_flags,
3149 (constant_classref *) iptr->target, disp);
3151 if (opt_showdisassemble)
3154 M_ILD(REG_ITMP3, REG_PV, disp);
3155 M_AND_IMM(REG_ITMP3, ACC_INTERFACE, REG_ITMP3);
3159 /* interface instanceof code */
3161 if (!super || (super->flags & ACC_INTERFACE)) {
3167 codegen_addpatchref(cd, mcodeptr,
3168 PATCHER_checkcast_instanceof_interface,
3169 (constant_classref *) iptr->target, 0);
3171 if (opt_showdisassemble)
3175 M_ALD(REG_ITMP1, s1, OFFSET(java_objectheader, vftbl));
3176 M_ILD(REG_ITMP3, REG_ITMP1, OFFSET(vftbl_t, interfacetablelength));
3177 M_LDATST(REG_ITMP3, REG_ITMP3, -superindex);
3179 M_ALD(REG_ITMP1, REG_ITMP1,
3180 OFFSET(vftbl_t, interfacetable[0]) -
3181 superindex * sizeof(methodptr*));
3184 M_IADD_IMM(REG_ZERO, 1, d);
3190 /* class instanceof code */
3192 if (!super || !(super->flags & ACC_INTERFACE)) {
3193 disp = dseg_addaddress(cd, supervftbl);
3200 codegen_addpatchref(cd, mcodeptr,
3201 PATCHER_instanceof_class,
3202 (constant_classref *) iptr->target,
3205 if (opt_showdisassemble) {
3210 M_ALD(REG_ITMP1, s1, OFFSET(java_objectheader, vftbl));
3211 M_ALD(REG_ITMP2, REG_PV, disp);
3212 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3213 codegen_threadcritstart(cd, (u1 *) mcodeptr - cd->mcodebase);
3215 M_ILD(REG_ITMP1, REG_ITMP1, OFFSET(vftbl_t, baseval));
3216 M_ILD(REG_ITMP3, REG_ITMP2, OFFSET(vftbl_t, baseval));
3217 M_ILD(REG_ITMP2, REG_ITMP2, OFFSET(vftbl_t, diffval));
3218 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3219 codegen_threadcritstop(cd, (u1 *) mcodeptr - cd->mcodebase);
3221 M_ISUB(REG_ITMP1, REG_ITMP3, REG_ITMP1);
3222 M_CMPU(REG_ITMP1, REG_ITMP2);
3225 M_IADD_IMM(REG_ZERO, 1, d);
3227 store_reg_to_var_int(iptr->dst, d);
3231 case ICMD_MULTIANEWARRAY:/* ..., cnt1, [cnt2, ...] ==> ..., arrayref */
3232 /* op1 = dimension, val.a = class */
3234 /* check for negative sizes and copy sizes to stack if necessary */
3236 MCODECHECK((iptr->op1 << 1) + 64);
3238 for (s1 = iptr->op1; --s1 >= 0; src = src->prev) {
3239 /* copy SAVEDVAR sizes to stack */
3241 if (src->varkind != ARGVAR) {
3242 var_to_reg_int(s2, src, REG_ITMP1);
3243 #if defined(__DARWIN__)
3244 M_IST(s2, REG_SP, LA_SIZE + (s1 + INT_ARG_CNT) * 4);
3246 M_IST(s2, REG_SP, LA_SIZE + (s1 + 3) * 4);
3251 /* a0 = dimension count */
3253 ICONST(rd->argintregs[0], iptr->op1);
3255 /* is patcher function set? */
3257 if (iptr->val.a == NULL) {
3258 disp = dseg_addaddress(cd, NULL);
3260 codegen_addpatchref(cd, mcodeptr,
3261 PATCHER_builtin_multianewarray,
3262 (constant_classref *) iptr->target,
3265 if (opt_showdisassemble)
3269 disp = dseg_addaddress(cd, iptr->val.a);
3272 /* a1 = arraydescriptor */
3274 M_ALD(rd->argintregs[1], REG_PV, disp);
3276 /* a2 = pointer to dimensions = stack pointer */
3278 #if defined(__DARWIN__)
3279 M_LDA(rd->argintregs[2], REG_SP, LA_SIZE + INT_ARG_CNT * 4);
3281 M_LDA(rd->argintregs[2], REG_SP, LA_SIZE + 3 * 4);
3284 disp = dseg_addaddress(cd, BUILTIN_multianewarray);
3285 M_ALD(REG_ITMP3, REG_PV, disp);
3289 /* check for exception before result assignment */
3291 M_CMPI(REG_RESULT, 0);
3293 codegen_addxexceptionrefs(cd, mcodeptr);
3295 d = reg_of_var(rd, iptr->dst, REG_RESULT);
3296 M_INTMOVE(REG_RESULT, d);
3297 store_reg_to_var_adr(iptr->dst, d);
3302 new_internalerror("Unknown ICMD %d", iptr->opc);
3306 } /* for instruction */
3308 /* copy values to interface registers */
3310 src = bptr->outstack;
3311 len = bptr->outdepth;
3312 MCODECHECK(64 + len);
3313 #if defined(ENABLE_LSRA)
3318 if ((src->varkind != STACKVAR)) {
3320 if (IS_FLT_DBL_TYPE(s2)) {
3321 var_to_reg_flt(s1, src, REG_FTMP1);
3322 if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
3323 M_FLTMOVE(s1, rd->interfaces[len][s2].regoff);
3326 M_DST(s1, REG_SP, rd->interfaces[len][s2].regoff * 4);
3330 var_to_reg_int(s1, src, REG_ITMP1);
3331 if (!(rd->interfaces[len][s2].flags & INMEMORY)) {
3332 M_TINTMOVE(s2, s1, rd->interfaces[len][s2].regoff);
3335 if (IS_2_WORD_TYPE(s2)) {
3336 M_IST(GET_HIGH_REG(s1),
3337 REG_SP, rd->interfaces[len][s2].regoff * 4);
3338 M_IST(GET_LOW_REG(s1), REG_SP,
3339 rd->interfaces[len][s2].regoff * 4 + 4);
3341 M_IST(s1, REG_SP, rd->interfaces[len][s2].regoff * 4);
3349 } /* if (bptr -> flags >= BBREACHED) */
3350 } /* for basic block */
3352 dseg_createlinenumbertable(cd);
3359 /* generate ArithemticException check stubs */
3363 for (bref = cd->xdivrefs; bref != NULL; bref = bref->next) {
3364 gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3366 (u1 *) mcodeptr - cd->mcodebase);
3370 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
3372 if (xcodeptr != NULL) {
3373 disp = xcodeptr - mcodeptr - 1;
3377 xcodeptr = mcodeptr;
3379 if (m->isleafmethod) {
3381 M_AST(REG_ZERO, REG_SP, parentargs_base * 4 + LA_LR_OFFSET);
3384 M_MOV(REG_PV, rd->argintregs[0]);
3385 M_MOV(REG_SP, rd->argintregs[1]);
3387 if (m->isleafmethod)
3388 M_MOV(REG_ZERO, rd->argintregs[2]);
3390 M_ALD(rd->argintregs[2],
3391 REG_SP, parentargs_base * 4 + LA_LR_OFFSET);
3393 M_MOV(REG_ITMP2_XPC, rd->argintregs[3]);
3395 M_STWU(REG_SP, REG_SP, -(LA_SIZE + 5 * 4));
3396 M_AST(REG_ITMP2_XPC, REG_SP, LA_SIZE + 4 * 4);
3398 disp = dseg_addaddress(cd, stacktrace_inline_arithmeticexception);
3399 M_ALD(REG_ITMP1, REG_PV, disp);
3402 M_MOV(REG_RESULT, REG_ITMP1_XPTR);
3404 M_ALD(REG_ITMP2_XPC, REG_SP, LA_SIZE + 4 * 4);
3405 M_IADD_IMM(REG_SP, LA_SIZE + 5 * 4, REG_SP);
3407 if (m->isleafmethod) {
3408 M_ALD(REG_ZERO, REG_SP, parentargs_base * 4 + LA_LR_OFFSET);
3412 disp = dseg_addaddress(cd, asm_handle_exception);
3413 M_ALD(REG_ITMP3, REG_PV, disp);
3419 /* generate ArrayIndexOutOfBoundsException stubs */
3423 for (bref = cd->xboundrefs; bref != NULL; bref = bref->next) {
3424 gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3426 (u1 *) mcodeptr - cd->mcodebase);
3430 /* move index register into REG_ITMP1 */
3432 M_MOV(bref->reg, REG_ITMP1);
3434 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
3436 if (xcodeptr != NULL) {
3437 disp = xcodeptr - mcodeptr - 1;
3441 xcodeptr = mcodeptr;
3443 if (m->isleafmethod) {
3445 M_AST(REG_ZERO, REG_SP, parentargs_base * 4 + LA_LR_OFFSET);
3448 M_MOV(REG_PV, rd->argintregs[0]);
3449 M_MOV(REG_SP, rd->argintregs[1]);
3451 if (m->isleafmethod)
3452 M_MOV(REG_ZERO, rd->argintregs[2]);
3454 M_ALD(rd->argintregs[2],
3455 REG_SP, parentargs_base * 4 + LA_LR_OFFSET);
3457 M_MOV(REG_ITMP2_XPC, rd->argintregs[3]);
3458 M_MOV(REG_ITMP1, rd->argintregs[4]);
3460 M_STWU(REG_SP, REG_SP, -(LA_SIZE + 6 * 4));
3461 M_AST(REG_ITMP2_XPC, REG_SP, LA_SIZE + 5 * 4);
3463 disp = dseg_addaddress(cd, stacktrace_inline_arrayindexoutofboundsexception);
3464 M_ALD(REG_ITMP1, REG_PV, disp);
3467 M_MOV(REG_RESULT, REG_ITMP1_XPTR);
3469 M_ALD(REG_ITMP2_XPC, REG_SP, LA_SIZE + 5 * 4);
3470 M_IADD_IMM(REG_SP, LA_SIZE + 6 * 4, REG_SP);
3472 if (m->isleafmethod) {
3473 M_ALD(REG_ZERO, REG_SP, parentargs_base * 4 + LA_LR_OFFSET);
3477 disp = dseg_addaddress(cd, asm_handle_exception);
3478 M_ALD(REG_ITMP3, REG_PV, disp);
3484 /* generate ArrayStoreException check stubs */
3488 for (bref = cd->xstorerefs; bref != NULL; bref = bref->next) {
3489 gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3491 (u1 *) mcodeptr - cd->mcodebase);
3495 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
3497 if (xcodeptr != NULL) {
3498 disp = xcodeptr - mcodeptr - 1;
3502 xcodeptr = mcodeptr;
3504 M_MOV(REG_PV, rd->argintregs[0]);
3505 M_MOV(REG_SP, rd->argintregs[1]);
3506 M_ALD(rd->argintregs[2],
3507 REG_SP, parentargs_base * 4 + LA_LR_OFFSET);
3508 M_MOV(REG_ITMP2_XPC, rd->argintregs[3]);
3510 M_STWU(REG_SP, REG_SP, -(LA_SIZE + 5 * 4));
3511 M_AST(REG_ITMP2_XPC, REG_SP, LA_SIZE + 4 * 4);
3513 disp = dseg_addaddress(cd, stacktrace_inline_arraystoreexception);
3514 M_ALD(REG_ITMP1, REG_PV, disp);
3517 M_MOV(REG_RESULT, REG_ITMP1_XPTR);
3519 M_ALD(REG_ITMP2_XPC, REG_SP, LA_SIZE + 4 * 4);
3520 M_IADD_IMM(REG_SP, LA_SIZE + 5 * 4, REG_SP);
3522 disp = dseg_addaddress(cd, asm_handle_exception);
3523 M_ALD(REG_ITMP3, REG_PV, disp);
3529 /* generate ClassCastException stubs */
3533 for (bref = cd->xcastrefs; bref != NULL; bref = bref->next) {
3534 gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3536 (u1 *) mcodeptr - cd->mcodebase);
3540 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
3542 if (xcodeptr != NULL) {
3543 disp = xcodeptr - mcodeptr - 1;
3547 xcodeptr = mcodeptr;
3549 if (m->isleafmethod) {
3551 M_AST(REG_ZERO, REG_SP, parentargs_base * 4 + LA_LR_OFFSET);
3554 M_MOV(REG_PV, rd->argintregs[0]);
3555 M_MOV(REG_SP, rd->argintregs[1]);
3557 if (m->isleafmethod)
3558 M_MOV(REG_ZERO, rd->argintregs[2]);
3560 M_ALD(rd->argintregs[2],
3561 REG_SP, parentargs_base * 4 + LA_LR_OFFSET);
3563 M_MOV(REG_ITMP2_XPC, rd->argintregs[3]);
3565 M_STWU(REG_SP, REG_SP, -(LA_SIZE + 5 * 4));
3566 M_AST(REG_ITMP2_XPC, REG_SP, LA_SIZE + 4 * 4);
3568 disp = dseg_addaddress(cd, stacktrace_inline_classcastexception);
3569 M_ALD(REG_ITMP1, REG_PV, disp);
3572 M_MOV(REG_RESULT, REG_ITMP1_XPTR);
3574 M_ALD(REG_ITMP2_XPC, REG_SP, LA_SIZE + 4 * 4);
3575 M_IADD_IMM(REG_SP, LA_SIZE + 5 * 4, REG_SP);
3577 if (m->isleafmethod) {
3578 M_ALD(REG_ZERO, REG_SP, parentargs_base * 4 + LA_LR_OFFSET);
3582 disp = dseg_addaddress(cd, asm_handle_exception);
3583 M_ALD(REG_ITMP3, REG_PV, disp);
3589 /* generate NullPointerException stubs */
3593 for (bref = cd->xnullrefs; bref != NULL; bref = bref->next) {
3594 gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3596 (u1 *) mcodeptr - cd->mcodebase);
3600 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
3602 if (xcodeptr != NULL) {
3603 disp = xcodeptr - mcodeptr - 1;
3607 xcodeptr = mcodeptr;
3609 if (m->isleafmethod) {
3611 M_AST(REG_ZERO, REG_SP, parentargs_base * 4 + LA_LR_OFFSET);
3614 M_MOV(REG_PV, rd->argintregs[0]);
3615 M_MOV(REG_SP, rd->argintregs[1]);
3617 if (m->isleafmethod)
3618 M_MOV(REG_ZERO, rd->argintregs[2]);
3620 M_ALD(rd->argintregs[2],
3621 REG_SP, parentargs_base * 4 + LA_LR_OFFSET);
3623 M_MOV(REG_ITMP2_XPC, rd->argintregs[3]);
3625 M_STWU(REG_SP, REG_SP, -(LA_SIZE + 5 * 4));
3626 M_AST(REG_ITMP2_XPC, REG_SP, LA_SIZE + 4 * 4);
3628 disp = dseg_addaddress(cd, stacktrace_inline_nullpointerexception);
3629 M_ALD(REG_ITMP1, REG_PV, disp);
3632 M_MOV(REG_RESULT, REG_ITMP1_XPTR);
3634 M_ALD(REG_ITMP2_XPC, REG_SP, LA_SIZE + 4 * 4);
3635 M_IADD_IMM(REG_SP, LA_SIZE + 5 * 4, REG_SP);
3637 if (m->isleafmethod) {
3638 M_ALD(REG_ZERO, REG_SP, parentargs_base * 4 + LA_LR_OFFSET);
3642 disp = dseg_addaddress(cd, asm_handle_exception);
3643 M_ALD(REG_ITMP3, REG_PV, disp);
3649 /* generate exception check stubs */
3653 for (bref = cd->xexceptionrefs; bref != NULL; bref = bref->next) {
3654 gen_resolvebranch((u1 *) cd->mcodebase + bref->branchpos,
3656 (u1 *) mcodeptr - cd->mcodebase);
3660 M_LDA(REG_ITMP2_XPC, REG_PV, bref->branchpos - 4);
3662 if (xcodeptr != NULL) {
3663 disp = xcodeptr - mcodeptr - 1;
3667 xcodeptr = mcodeptr;
3669 M_MOV(REG_PV, rd->argintregs[0]);
3670 M_MOV(REG_SP, rd->argintregs[1]);
3671 M_ALD(rd->argintregs[2],
3672 REG_SP, parentargs_base * 4 + LA_LR_OFFSET);
3673 M_MOV(REG_ITMP2_XPC, rd->argintregs[3]);
3675 M_STWU(REG_SP, REG_SP, -(LA_SIZE + 5 * 4));
3676 M_AST(REG_ITMP2_XPC, REG_SP, LA_SIZE + 4 * 4);
3678 disp = dseg_addaddress(cd, stacktrace_inline_fillInStackTrace);
3679 M_ALD(REG_ITMP1, REG_PV, disp);
3682 M_MOV(REG_RESULT, REG_ITMP1_XPTR);
3684 M_ALD(REG_ITMP2_XPC, REG_SP, LA_SIZE + 4 * 4);
3685 M_IADD_IMM(REG_SP, LA_SIZE + 5 * 4, REG_SP);
3687 disp = dseg_addaddress(cd, asm_handle_exception);
3688 M_ALD(REG_ITMP3, REG_PV, disp);
3694 /* generate patcher stub call code */
3701 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
3702 /* check code segment size */
3706 /* Get machine code which is patched back in later. The call is */
3707 /* 1 instruction word long. */
3709 xcodeptr = (s4 *) (cd->mcodebase + pref->branchpos);
3712 /* patch in the call to call the following code (done at compile */
3715 tmpmcodeptr = mcodeptr; /* save current mcodeptr */
3716 mcodeptr = xcodeptr; /* set mcodeptr to patch position */
3718 M_BR(tmpmcodeptr - (xcodeptr + 1));
3720 mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
3722 /* create stack frame - keep stack 16-byte aligned */
3724 M_AADD_IMM(REG_SP, -8 * 4, REG_SP);
3726 /* calculate return address and move it onto the stack */
3728 M_LDA(REG_ITMP3, REG_PV, pref->branchpos);
3729 M_AST_INTERN(REG_ITMP3, REG_SP, 5 * 4);
3731 /* move pointer to java_objectheader onto stack */
3733 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
3734 /* order reversed because of data segment layout */
3736 (void) dseg_addaddress(cd, get_dummyLR()); /* monitorPtr */
3737 disp = dseg_addaddress(cd, NULL); /* vftbl */
3739 M_LDA(REG_ITMP3, REG_PV, disp);
3740 M_AST_INTERN(REG_ITMP3, REG_SP, 4 * 4);
3745 /* move machine code onto stack */
3747 disp = dseg_adds4(cd, mcode);
3748 M_ILD(REG_ITMP3, REG_PV, disp);
3749 M_IST_INTERN(REG_ITMP3, REG_SP, 3 * 4);
3751 /* move class/method/field reference onto stack */
3753 disp = dseg_addaddress(cd, pref->ref);
3754 M_ALD(REG_ITMP3, REG_PV, disp);
3755 M_AST_INTERN(REG_ITMP3, REG_SP, 2 * 4);
3757 /* move data segment displacement onto stack */
3759 disp = dseg_addaddress(cd, pref->disp);
3760 M_ILD(REG_ITMP3, REG_PV, disp);
3761 M_IST_INTERN(REG_ITMP3, REG_SP, 1 * 4);
3763 /* move patcher function pointer onto stack */
3765 disp = dseg_addaddress(cd, pref->patcher);
3766 M_ALD(REG_ITMP3, REG_PV, disp);
3767 M_AST_INTERN(REG_ITMP3, REG_SP, 0 * 4);
3769 disp = dseg_addaddress(cd, asm_wrapper_patcher);
3770 M_ALD(REG_ITMP3, REG_PV, disp);
3778 codegen_finish(m, cd, (ptrint) ((u1 *) mcodeptr - cd->mcodebase));
3780 asm_cacheflush((void *) (ptrint) m->entrypoint, ((u1 *) mcodeptr - cd->mcodebase));
3782 /* everything's ok */
3788 /* createcompilerstub **********************************************************
3790 Creates a stub routine which calls the compiler.
3792 *******************************************************************************/
3794 #define COMPSTUBSIZE 6
3796 u1 *createcompilerstub(methodinfo *m)
3798 s4 *s = CNEW(s4, COMPSTUBSIZE); /* memory to hold the stub */
3799 s4 *mcodeptr = s; /* code generation pointer */
3801 M_LDA(REG_ITMP1, REG_PV, 4 * 4);
3802 M_ALD_INTERN(REG_PV, REG_PV, 5 * 4);
3806 s[4] = (s4) m; /* literals to be adressed */
3807 s[5] = (s4) asm_call_jit_compiler; /* jump directly via PV from above */
3809 asm_cacheflush((void *) s, (u1 *) mcodeptr - (u1 *) s);
3811 #if defined(ENABLE_STATISTICS)
3813 count_cstub_len += COMPSTUBSIZE * 4;
3820 /* createnativestub ************************************************************
3822 Creates a stub routine which calls a native method.
3824 *******************************************************************************/
3826 u1 *createnativestub(functionptr f, methodinfo *m, codegendata *cd,
3827 registerdata *rd, methoddesc *nmd)
3829 s4 *mcodeptr; /* code generation pointer */
3830 s4 stackframesize; /* size of stackframe if needed */
3833 s4 i, j; /* count variables */
3838 /* set some variables */
3841 nativeparams = (m->flags & ACC_STATIC) ? 2 : 1;
3843 /* calculate stackframe size */
3846 sizeof(stackframeinfo) / SIZEOF_VOID_P +
3847 sizeof(localref_table) / SIZEOF_VOID_P +
3848 4 + /* 4 stackframeinfo arguments (darwin)*/
3849 nmd->paramcount * 2 + /* assume all arguments are doubles */
3852 stackframesize = (stackframesize + 3) & ~3; /* keep stack 16-byte aligned */
3855 /* create method header */
3857 (void) dseg_addaddress(cd, m); /* MethodPointer */
3858 (void) dseg_adds4(cd, stackframesize * 4); /* FrameSize */
3859 (void) dseg_adds4(cd, 0); /* IsSync */
3860 (void) dseg_adds4(cd, 0); /* IsLeaf */
3861 (void) dseg_adds4(cd, 0); /* IntSave */
3862 (void) dseg_adds4(cd, 0); /* FltSave */
3863 (void) dseg_addlinenumbertablesize(cd);
3864 (void) dseg_adds4(cd, 0); /* ExTableSize */
3867 /* initialize mcode variables */
3869 mcodeptr = (s4 *) cd->mcodebase;
3875 M_AST_INTERN(REG_ZERO, REG_SP, LA_LR_OFFSET);
3876 M_STWU(REG_SP, REG_SP, -(stackframesize * 4));
3880 /* parent_argbase == stackframesize * 4 */
3881 mcodeptr = codegen_trace_args(m, cd, rd, mcodeptr, stackframesize * 4 ,
3886 /* get function address (this must happen before the stackframeinfo) */
3888 funcdisp = dseg_addaddress(cd, f);
3890 #if !defined(ENABLE_STATICVM)
3892 codegen_addpatchref(cd, mcodeptr, PATCHER_resolve_native, m, funcdisp);
3894 if (opt_showdisassemble)
3899 /* save integer and float argument registers */
3901 for (i = 0, j = 0; i < md->paramcount && j < INT_ARG_CNT; i++) {
3902 t = md->paramtypes[i].type;
3904 if (IS_INT_LNG_TYPE(t)) {
3905 s1 = md->params[i].regoff;
3906 if (IS_2_WORD_TYPE(t)) {
3907 M_IST(rd->argintregs[GET_HIGH_REG(s1)], REG_SP, LA_SIZE + 4 * 4 + j * 4);
3909 M_IST(rd->argintregs[GET_LOW_REG(s1)], REG_SP, LA_SIZE + 4 * 4 + j * 4);
3912 M_IST(rd->argintregs[s1], REG_SP, LA_SIZE + 4 * 4 + j * 4);
3918 for (i = 0; i < md->paramcount && j < FLT_ARG_CNT; i++) {
3919 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
3920 s1 = md->params[i].regoff;
3921 M_DST(rd->argfltregs[s1], REG_SP, LA_SIZE + 4 * 4 + j * 8);
3926 /* create native stack info */
3928 M_AADD_IMM(REG_SP, stackframesize * 4, rd->argintregs[0]);
3929 M_MOV(REG_PV, rd->argintregs[1]);
3930 M_AADD_IMM(REG_SP, stackframesize * 4, rd->argintregs[2]);
3931 M_ALD(rd->argintregs[3], REG_SP, stackframesize * 4 + LA_LR_OFFSET);
3932 disp = dseg_addaddress(cd, codegen_start_native_call);
3933 M_ALD(REG_ITMP1, REG_PV, disp);
3937 /* restore integer and float argument registers */
3939 for (i = 0, j = 0; i < md->paramcount && j < INT_ARG_CNT; i++) {
3940 t = md->paramtypes[i].type;
3942 if (IS_INT_LNG_TYPE(t)) {
3943 s1 = md->params[i].regoff;
3945 if (IS_2_WORD_TYPE(t)) {
3946 M_ILD(rd->argintregs[GET_HIGH_REG(s1)], REG_SP, LA_SIZE + 4 * 4 + j * 4);
3948 M_ILD(rd->argintregs[GET_LOW_REG(s1)], REG_SP, LA_SIZE + 4 * 4 + j * 4);
3951 M_ILD(rd->argintregs[s1], REG_SP, LA_SIZE + 4 * 4 + j * 4);
3957 for (i = 0; i < md->paramcount && j < FLT_ARG_CNT; i++) {
3958 if (IS_FLT_DBL_TYPE(md->paramtypes[i].type)) {
3959 s1 = md->params[i].regoff;
3960 M_DLD(rd->argfltregs[i], REG_SP, LA_SIZE + 4 * 4 + j * 8);
3965 /* copy or spill arguments to new locations */
3967 for (i = md->paramcount - 1, j = i + nativeparams; i >= 0; i--, j--) {
3968 t = md->paramtypes[i].type;
3970 if (IS_INT_LNG_TYPE(t)) {
3971 if (!md->params[i].inmemory) {
3972 if (IS_2_WORD_TYPE(t))
3974 rd->argintregs[GET_LOW_REG(md->params[i].regoff)],
3975 rd->argintregs[GET_HIGH_REG(md->params[i].regoff)]);
3977 s1 = rd->argintregs[md->params[i].regoff];
3979 if (!nmd->params[j].inmemory) {
3980 if (IS_2_WORD_TYPE(t))
3982 rd->argintregs[GET_LOW_REG(nmd->params[j].regoff)],
3983 rd->argintregs[GET_HIGH_REG(nmd->params[j].regoff)]);
3985 s2 = rd->argintregs[nmd->params[j].regoff];
3986 M_TINTMOVE(t, s1, s2);
3989 s2 = nmd->params[j].regoff;
3990 if (IS_2_WORD_TYPE(t)) {
3991 M_IST(GET_HIGH_REG(s1), REG_SP, s2 * 4);
3992 M_IST(GET_LOW_REG(s1), REG_SP, s2 * 4 + 4);
3994 M_IST(s1, REG_SP, s2 * 4);
3999 s1 = md->params[i].regoff + stackframesize;
4000 s2 = nmd->params[j].regoff;
4002 M_ILD(REG_ITMP1, REG_SP, s1 * 4);
4003 if (IS_2_WORD_TYPE(t)) {
4004 M_ILD(REG_ITMP2, REG_SP, s1 * 4 + 4);
4006 M_IST(REG_ITMP1, REG_SP, s2 * 4);
4007 if (IS_2_WORD_TYPE(t)) {
4008 M_IST(REG_ITMP2, REG_SP, s2 * 4 + 4);
4013 /* We only copy spilled float arguments, as the float argument */
4014 /* registers keep unchanged. */
4016 if (md->params[i].inmemory) {
4017 s1 = md->params[i].regoff + stackframesize;
4018 s2 = nmd->params[j].regoff;
4020 if (IS_2_WORD_TYPE(t)) {
4021 M_DLD(REG_FTMP1, REG_SP, s1 * 4);
4022 M_DST(REG_FTMP1, REG_SP, s2 * 4);
4025 M_FLD(REG_FTMP1, REG_SP, s1 * 4);
4026 M_FST(REG_FTMP1, REG_SP, s2 * 4);
4032 /* put class into second argument register */
4034 if (m->flags & ACC_STATIC) {
4035 disp = dseg_addaddress(cd, m->class);
4036 M_ALD(rd->argintregs[1], REG_PV, disp);
4039 /* put env into first argument register */
4041 disp = dseg_addaddress(cd, &env);
4042 M_ALD(rd->argintregs[0], REG_PV, disp);
4044 /* generate the actual native call */
4046 M_ALD(REG_ITMP3, REG_PV, funcdisp);
4050 /* save return value */
4052 if (md->returntype.type != TYPE_VOID) {
4053 if (IS_INT_LNG_TYPE(md->returntype.type)) {
4054 if (IS_2_WORD_TYPE(md->returntype.type))
4055 M_IST(REG_RESULT2, REG_SP, LA_SIZE + 2 * 4);
4056 M_IST(REG_RESULT, REG_SP, LA_SIZE + 1 * 4);
4058 if (IS_2_WORD_TYPE(md->returntype.type))
4059 M_DST(REG_FRESULT, REG_SP, LA_SIZE + 1 * 4);
4061 M_FST(REG_FRESULT, REG_SP, LA_SIZE + 1 * 4);
4065 /* remove native stackframe info */
4067 M_AADD_IMM(REG_SP, stackframesize * 4, rd->argintregs[0]);
4068 disp = dseg_addaddress(cd, codegen_finish_native_call);
4069 M_ALD(REG_ITMP1, REG_PV, disp);
4073 /* print call trace */
4076 /* just restore the value we need, don't care about the other */
4078 if (md->returntype.type != TYPE_VOID) {
4079 if (IS_INT_LNG_TYPE(md->returntype.type)) {
4080 if (IS_2_WORD_TYPE(md->returntype.type))
4081 M_ILD(REG_RESULT2, REG_SP, LA_SIZE + 2 * 4);
4082 M_ILD(REG_RESULT, REG_SP, LA_SIZE + 1 * 4);
4084 if (IS_2_WORD_TYPE(md->returntype.type))
4085 M_DLD(REG_FRESULT, REG_SP, LA_SIZE + 1 * 4);
4087 M_FLD(REG_FRESULT, REG_SP, LA_SIZE + 1 * 4);
4091 M_LDA(REG_SP, REG_SP, -(LA_SIZE + (1 + 2 + 2 + 1) * 4));
4093 /* keep this order */
4094 switch (md->returntype.type) {
4097 #if defined(__DARWIN__)
4098 M_MOV(REG_RESULT, rd->argintregs[2]);
4099 M_CLR(rd->argintregs[1]);
4101 M_MOV(REG_RESULT, rd->argintregs[3]);
4102 M_CLR(rd->argintregs[2]);
4107 #if defined(__DARWIN__)
4108 M_MOV(REG_RESULT2, rd->argintregs[2]);
4109 M_MOV(REG_RESULT, rd->argintregs[1]);
4111 M_MOV(REG_RESULT2, rd->argintregs[3]);
4112 M_MOV(REG_RESULT, rd->argintregs[2]);
4117 M_FLTMOVE(REG_FRESULT, rd->argfltregs[0]);
4118 M_FLTMOVE(REG_FRESULT, rd->argfltregs[1]);
4119 disp = dseg_addaddress(cd, m);
4120 M_ALD(rd->argintregs[0], REG_PV, disp);
4122 disp = dseg_addaddress(cd, builtin_displaymethodstop);
4123 M_ALD(REG_ITMP2, REG_PV, disp);
4127 M_LDA(REG_SP, REG_SP, LA_SIZE + (1 + 2 + 2 + 1) * 4);
4130 /* check for exception */
4132 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4133 disp = dseg_addaddress(cd, builtin_get_exceptionptrptr);
4134 M_ALD(REG_ITMP1, REG_PV, disp);
4137 M_MOV(REG_RESULT, REG_ITMP2);
4139 disp = dseg_addaddress(cd, &_no_threads_exceptionptr);
4140 M_ALD(REG_ITMP2, REG_PV, disp);
4142 M_ALD(REG_ITMP1_XPTR, REG_ITMP2, 0);/* load exception into reg. itmp1 */
4144 /* restore return value */
4146 if (md->returntype.type != TYPE_VOID) {
4147 if (IS_INT_LNG_TYPE(md->returntype.type)) {
4148 if (IS_2_WORD_TYPE(md->returntype.type))
4149 M_ILD(REG_RESULT2, REG_SP, LA_SIZE + 2 * 4);
4150 M_ILD(REG_RESULT, REG_SP, LA_SIZE + 1 * 4);
4152 if (IS_2_WORD_TYPE(md->returntype.type))
4153 M_DLD(REG_FRESULT, REG_SP, LA_SIZE + 1 * 4);
4155 M_FLD(REG_FRESULT, REG_SP, LA_SIZE + 1 * 4);
4159 M_TST(REG_ITMP1_XPTR);
4160 M_BNE(4); /* if no exception then return */
4162 M_ALD(REG_ZERO, REG_SP, stackframesize * 4 + LA_LR_OFFSET); /* load ra */
4164 M_LDA(REG_SP, REG_SP, stackframesize * 4); /* remove stackframe */
4167 /* handle exception */
4170 M_AST(REG_ITMP3, REG_ITMP2, 0); /* store NULL into exceptionptr */
4172 M_ALD(REG_ITMP2, REG_SP, stackframesize * 4 + LA_LR_OFFSET); /* load ra */
4175 M_LDA(REG_SP, REG_SP, stackframesize * 4); /* remove stackframe */
4177 M_IADD_IMM(REG_ITMP2, -4, REG_ITMP2_XPC); /* fault address */
4179 disp = dseg_addaddress(cd, asm_handle_nat_exception);
4180 M_ALD(REG_ITMP3, REG_PV, disp);
4184 /* generate patcher stub call code */
4192 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
4193 /* Get machine code which is patched back in later. The call is */
4194 /* 1 instruction word long. */
4196 xcodeptr = (s4 *) (cd->mcodebase + pref->branchpos);
4197 mcode = (u4) *xcodeptr;
4199 /* patch in the call to call the following code (done at compile */
4202 tmpmcodeptr = mcodeptr; /* save current mcodeptr */
4203 mcodeptr = xcodeptr; /* set mcodeptr to patch position */
4205 M_BL(tmpmcodeptr - (xcodeptr + 1));
4207 mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
4209 /* create stack frame - keep stack 16-byte aligned */
4211 M_AADD_IMM(REG_SP, -8 * 4, REG_SP);
4213 /* move return address onto stack */
4216 M_AST(REG_ZERO, REG_SP, 5 * 4);
4218 /* move pointer to java_objectheader onto stack */
4220 #if defined(USE_THREADS) && defined(NATIVE_THREADS)
4221 /* order reversed because of data segment layout */
4223 (void) dseg_addaddress(cd, get_dummyLR()); /* monitorPtr */
4224 disp = dseg_addaddress(cd, NULL); /* vftbl */
4226 M_LDA(REG_ITMP3, REG_PV, disp);
4227 M_AST(REG_ITMP3, REG_SP, 4 * 4);
4232 /* move machine code onto stack */
4234 disp = dseg_adds4(cd, mcode);
4235 M_ILD(REG_ITMP3, REG_PV, disp);
4236 M_IST(REG_ITMP3, REG_SP, 3 * 4);
4238 /* move class/method/field reference onto stack */
4240 disp = dseg_addaddress(cd, pref->ref);
4241 M_ALD(REG_ITMP3, REG_PV, disp);
4242 M_AST(REG_ITMP3, REG_SP, 2 * 4);
4244 /* move data segment displacement onto stack */
4246 disp = dseg_addaddress(cd, pref->disp);
4247 M_ILD(REG_ITMP3, REG_PV, disp);
4248 M_IST(REG_ITMP3, REG_SP, 1 * 4);
4250 /* move patcher function pointer onto stack */
4252 disp = dseg_addaddress(cd, pref->patcher);
4253 M_ALD(REG_ITMP3, REG_PV, disp);
4254 M_AST(REG_ITMP3, REG_SP, 0 * 4);
4256 disp = dseg_addaddress(cd, asm_wrapper_patcher);
4257 M_ALD(REG_ITMP3, REG_PV, disp);
4263 codegen_finish(m, cd, (s4) ((u1 *) mcodeptr - cd->mcodebase));
4265 asm_cacheflush((void *) (ptrint) m->entrypoint, ((u1 *) mcodeptr - cd->mcodebase));
4267 return m->entrypoint;
4271 s4 *codegen_trace_args(methodinfo *m, codegendata *cd, registerdata *rd,
4272 s4 *mcodeptr, s4 parentargs_base, bool nativestub)
4283 /* Build up Stackframe for builtin_trace_args call (a multiple of 16) */
4285 /* LA + TRACE_ARGS_NUM u8 args + methodinfo + LR */
4286 /* LA_SIZE(=6*4) + 8*8 + 4 + 4 + 0(Padding) */
4287 /* 6 * 4 + 8 * 8 + 2 * 4 = 12 * 8 = 6 * 16 */
4289 /* LA + (TRACE_ARGS_NUM - INT_ARG_CNT/2) u8 args + methodinfo */
4290 /* + INT_ARG_CNT * 4 ( save integer registers) + LR + 8 + 8 (Padding) */
4291 /* LA_SIZE(=2*4) + 4 * 8 + 4 + 8 * 4 + 4 + 8 */
4292 /* 2 * 4 + 4 * 8 + 10 * 4 + 1 * 8 + 8= 12 * 8 = 6 * 16 */
4294 /* in nativestubs no Place to save the LR (Link Register) would be needed */
4295 /* but since the stack frame has to be aligned the 4 Bytes would have to */
4296 /* be padded again */
4298 #if defined(__DARWIN__)
4299 stack_size = LA_SIZE + (TRACE_ARGS_NUM + 1) * 8;
4301 stack_size = 6 * 16;
4303 M_LDA(REG_SP, REG_SP, -stack_size);
4307 M_IST(REG_ITMP3, REG_SP, LA_SIZE + TRACE_ARGS_NUM * 8 + 1 * 4);
4309 M_CLR(REG_ITMP1); /* clear help register */
4311 /* save up to TRACE_ARGS_NUM arguments into the reserved stack space */
4312 #if defined(__DARWIN__)
4313 /* Copy Params starting from first to Stack */
4314 /* since TRACE_ARGS == INT_ARG_CNT all used integer argument regs */
4318 /* Copy Params starting from fifth to Stack (INT_ARG_CNT/2) are in */
4319 /* integer argument regs */
4320 /* all integer argument registers have to be saved */
4321 for (p = 0; p < 8; p++) {
4322 d = rd->argintregs[p];
4323 /* save integer argument registers */
4324 M_IST(d, REG_SP, LA_SIZE + 4 * 8 + 4 + p * 4);
4328 stack_off = LA_SIZE;
4329 for (; p < md->paramcount && p < TRACE_ARGS_NUM; p++, stack_off += 8) {
4330 t = md->paramtypes[p].type;
4331 if (IS_INT_LNG_TYPE(t)) {
4332 if (!md->params[p].inmemory) { /* Param in Arg Reg */
4333 if (IS_2_WORD_TYPE(t)) {
4334 M_IST(rd->argintregs[GET_HIGH_REG(md->params[p].regoff)]
4335 , REG_SP, stack_off);
4336 M_IST(rd->argintregs[GET_LOW_REG(md->params[p].regoff)]
4337 , REG_SP, stack_off + 4);
4339 M_IST(REG_ITMP1, REG_SP, stack_off);
4340 M_IST(rd->argintregs[md->params[p].regoff]
4341 , REG_SP, stack_off + 4);
4343 } else { /* Param on Stack */
4344 s1 = (md->params[p].regoff + parentargs_base) * 4
4346 if (IS_2_WORD_TYPE(t)) {
4347 M_ILD(REG_ITMP2, REG_SP, s1);
4348 M_IST(REG_ITMP2, REG_SP, stack_off);
4349 M_ILD(REG_ITMP2, REG_SP, s1 + 4);
4350 M_IST(REG_ITMP2, REG_SP, stack_off + 4);
4352 M_IST(REG_ITMP1, REG_SP, stack_off);
4353 M_ILD(REG_ITMP2, REG_SP, s1);
4354 M_IST(REG_ITMP2, REG_SP, stack_off + 4);
4357 } else { /* IS_FLT_DBL_TYPE(t) */
4358 if (!md->params[p].inmemory) { /* in Arg Reg */
4359 s1 = rd->argfltregs[md->params[p].regoff];
4360 if (!IS_2_WORD_TYPE(t)) {
4361 M_IST(REG_ITMP1, REG_SP, stack_off);
4362 M_FST(s1, REG_SP, stack_off + 4);
4364 M_DST(s1, REG_SP, stack_off);
4366 } else { /* on Stack */
4367 /* this should not happen */
4372 /* load first 4 (==INT_ARG_CNT/2) arguments into integer registers */
4373 #if defined(__DARWIN__)
4374 for (p = 0; p < 8; p++) {
4375 d = rd->argintregs[p];
4376 M_ILD(d, REG_SP, LA_SIZE + p * 4);
4380 /* Set integer and float argument registers vor trace_args call */
4381 /* offset to saved integer argument registers */
4382 stack_off = LA_SIZE + 4 * 8 + 4;
4383 for (p = 0; (p < 4) && (p < md->paramcount); p++) {
4384 t = md->paramtypes[p].type;
4385 if (IS_INT_LNG_TYPE(t)) {
4386 /* "stretch" int types */
4387 if (!IS_2_WORD_TYPE(t)) {
4388 M_CLR(rd->argintregs[2 * p]);
4389 M_ILD(rd->argintregs[2 * p + 1], REG_SP,stack_off);
4392 M_ILD(rd->argintregs[2 * p + 1], REG_SP,stack_off + 4);
4393 M_ILD(rd->argintregs[2 * p], REG_SP,stack_off);
4396 } else { /* Float/Dbl */
4397 if (!md->params[p].inmemory) { /* Param in Arg Reg */
4398 /* use reserved Place on Stack (sp + 5 * 16) to copy */
4399 /* float/double arg reg to int reg */
4400 s1 = rd->argfltregs[md->params[p].regoff];
4401 if (!IS_2_WORD_TYPE(t)) {
4402 M_FST(s1, REG_SP, 5 * 16);
4403 M_ILD(rd->argintregs[2 * p + 1], REG_SP, 5 * 16);
4404 M_CLR(rd->argintregs[2 * p]);
4406 M_DST(s1, REG_SP, 5 * 16);
4407 M_ILD(rd->argintregs[2 * p + 1], REG_SP, 5 * 16 + 4);
4408 M_ILD(rd->argintregs[2 * p], REG_SP, 5 * 16);
4415 /* put methodinfo pointer on Stackframe */
4416 p = dseg_addaddress(cd, m);
4417 M_ALD(REG_ITMP1, REG_PV, p);
4418 #if defined(__DARWIN__)
4419 M_AST(REG_ITMP1, REG_SP, LA_SIZE + TRACE_ARGS_NUM * 8);
4421 M_AST(REG_ITMP1, REG_SP, LA_SIZE + 4 * 8);
4423 p = dseg_addaddress(cd, builtin_trace_args);
4424 M_ALD(REG_ITMP2, REG_PV, p);
4428 #if defined(__DARWIN__)
4429 /* restore integer argument registers from the reserved stack space */
4431 stack_off = LA_SIZE;
4432 for (p = 0; p < md->paramcount && p < TRACE_ARGS_NUM;
4433 p++, stack_off += 8) {
4434 t = md->paramtypes[p].type;
4436 if (IS_INT_LNG_TYPE(t)) {
4437 if (!md->params[p].inmemory) {
4438 if (IS_2_WORD_TYPE(t)) {
4439 M_ILD(rd->argintregs[GET_HIGH_REG(md->params[p].regoff)]
4440 , REG_SP, stack_off);
4441 M_ILD(rd->argintregs[GET_LOW_REG(md->params[p].regoff)]
4442 , REG_SP, stack_off + 4);
4444 M_ILD(rd->argintregs[md->params[p].regoff]
4445 , REG_SP, stack_off + 4);
4452 for (p = 0; p < 8; p++) {
4453 d = rd->argintregs[p];
4454 /* save integer argument registers */
4455 M_ILD(d, REG_SP, LA_SIZE + 4 * 8 + 4 + p * 4);
4460 M_ILD(REG_ITMP3, REG_SP, LA_SIZE + TRACE_ARGS_NUM * 8 + 1 * 4);
4462 M_LDA(REG_SP, REG_SP, stack_size);
4469 * These are local overrides for various environment variables in Emacs.
4470 * Please do not remove this and leave it at the end of the file, where
4471 * Emacs will automagically detect them.
4472 * ---------------------------------------------------------------------
4475 * indent-tabs-mode: t