Merged with tip.
[cacao.git] / src / vm / jit / mips / emit.c
1 /* src/vm/jit/mips/emit.c - MIPS code emitter functions
2
3    Copyright (C) 1996-2005, 2006, 2007, 2008
4    CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
5
6    This file is part of CACAO.
7
8    This program is free software; you can redistribute it and/or
9    modify it under the terms of the GNU General Public License as
10    published by the Free Software Foundation; either version 2, or (at
11    your option) any later version.
12
13    This program is distributed in the hope that it will be useful, but
14    WITHOUT ANY WARRANTY; without even the implied warranty of
15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16    General Public License for more details.
17
18    You should have received a copy of the GNU General Public License
19    along with this program; if not, write to the Free Software
20    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21    02110-1301, USA.
22
23 */
24
25
26 #include "config.h"
27
28 #include <assert.h>
29
30 #include "vm/types.h"
31
32 #include "vm/jit/mips/codegen.h"
33 #include "vm/jit/mips/md-abi.h"
34
35 #include "mm/memory.h"
36
37 #include "threads/lock-common.h"
38
39 #include "vm/builtin.h"
40 #include "vm/exceptions.h"
41 #include "vm/stringlocal.h" /* XXX for gen_resolvebranch */
42
43 #include "vm/jit/abi.h"
44 #include "vm/jit/abi-asm.h"
45 #include "vm/jit/asmpart.h"
46 #include "vm/jit/dseg.h"
47 #include "vm/jit/emit-common.h"
48 #include "vm/jit/jit.h"
49 #include "vm/jit/patcher-common.h"
50 #include "vm/jit/replace.h"
51 #include "vm/jit/trap.h"
52
53 #include "vmcore/options.h"
54
55
56 /* emit_load *******************************************************************
57
58    Emits a possible load of an operand.
59
60 *******************************************************************************/
61
62 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
63 {
64         codegendata  *cd;
65         s4            disp;
66         s4            reg;
67
68         /* get required compiler data */
69
70         cd = jd->cd;
71
72         if (src->flags & INMEMORY) {
73                 COUNT_SPILLS;
74
75                 disp = src->vv.regoff;
76
77                 switch (src->type) {
78 #if SIZEOF_VOID_P == 8
79                 case TYPE_INT:
80                 case TYPE_LNG:
81                 case TYPE_ADR:
82                         M_LLD(tempreg, REG_SP, disp);
83                         break;
84 #else
85                 case TYPE_INT:
86                 case TYPE_ADR:
87                         M_ILD(tempreg, REG_SP, disp);
88                         break;
89                 case TYPE_LNG:
90                         M_LLD(tempreg, REG_SP, disp);
91                         break;
92 #endif
93                 case TYPE_FLT:
94                         M_FLD(tempreg, REG_SP, disp);
95                         break;
96                 case TYPE_DBL:
97                         M_DLD(tempreg, REG_SP, disp);
98                         break;
99                 default:
100                         vm_abort("emit_load: unknown type %d", src->type);
101                 }
102
103                 reg = tempreg;
104         }
105         else
106                 reg = src->vv.regoff;
107
108         return reg;
109 }
110
111
112 /* emit_load_low ***************************************************************
113
114    Emits a possible load of the low 32-bits of an operand.
115
116 *******************************************************************************/
117
118 #if SIZEOF_VOID_P == 4
119 s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
120 {
121         codegendata  *cd;
122         s4            disp;
123         s4            reg;
124
125         assert(src->type == TYPE_LNG);
126
127         /* get required compiler data */
128
129         cd = jd->cd;
130
131         if (src->flags & INMEMORY) {
132                 COUNT_SPILLS;
133
134                 disp = src->vv.regoff;
135
136 #if WORDS_BIGENDIAN == 1
137                 M_ILD(tempreg, REG_SP, disp + 4);
138 #else
139                 M_ILD(tempreg, REG_SP, disp);
140 #endif
141
142                 reg = tempreg;
143         }
144         else
145                 reg = GET_LOW_REG(src->vv.regoff);
146
147         return reg;
148 }
149 #endif /* SIZEOF_VOID_P == 4 */
150
151
152 /* emit_load_high **************************************************************
153
154    Emits a possible load of the high 32-bits of an operand.
155
156 *******************************************************************************/
157
158 #if SIZEOF_VOID_P == 4
159 s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
160 {
161         codegendata  *cd;
162         s4            disp;
163         s4            reg;
164
165         assert(src->type == TYPE_LNG);
166
167         /* get required compiler data */
168
169         cd = jd->cd;
170
171         if (src->flags & INMEMORY) {
172                 COUNT_SPILLS;
173
174                 disp = src->vv.regoff;
175
176 #if WORDS_BIGENDIAN == 1
177                 M_ILD(tempreg, REG_SP, disp);
178 #else
179                 M_ILD(tempreg, REG_SP, disp + 4);
180 #endif
181
182                 reg = tempreg;
183         }
184         else
185                 reg = GET_HIGH_REG(src->vv.regoff);
186
187         return reg;
188 }
189 #endif /* SIZEOF_VOID_P == 4 */
190
191
192 /* emit_store ******************************************************************
193
194    Emits a possible store to variable.
195
196 *******************************************************************************/
197
198 void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
199 {
200         codegendata  *cd;
201         s4            disp;
202
203         /* get required compiler data */
204
205         cd = jd->cd;
206
207         if (dst->flags & INMEMORY) {
208                 COUNT_SPILLS;
209
210                 disp = dst->vv.regoff;
211
212                 switch (dst->type) {
213 #if SIZEOF_VOID_P == 8
214                 case TYPE_INT:
215                 case TYPE_LNG:
216                 case TYPE_ADR:
217                         M_LST(d, REG_SP, disp);
218                         break;
219 #else
220                 case TYPE_INT:
221                 case TYPE_ADR:
222                         M_IST(d, REG_SP, disp);
223                         break;
224                 case TYPE_LNG:
225                         M_LST(d, REG_SP, disp);
226                         break;
227 #endif
228                 case TYPE_FLT:
229                         M_FST(d, REG_SP, disp);
230                         break;
231                 case TYPE_DBL:
232                         M_DST(d, REG_SP, disp);
233                         break;
234                 default:
235                         vm_abort("emit_store: unknown type %d", dst->type);
236                 }
237         }
238 }
239
240
241 /* emit_copy *******************************************************************
242
243    Generates a register/memory to register/memory copy.
244
245 *******************************************************************************/
246
247 void emit_copy(jitdata *jd, instruction *iptr)
248 {
249         codegendata *cd;
250         varinfo     *src;
251         varinfo     *dst;
252         s4           s1, d;
253
254         /* get required compiler data */
255
256         cd = jd->cd;
257
258         /* get source and destination variables */
259
260         src = VAROP(iptr->s1);
261         dst = VAROP(iptr->dst);
262
263         if ((src->vv.regoff != dst->vv.regoff) ||
264                 ((src->flags ^ dst->flags) & INMEMORY)) {
265
266                 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
267                         /* emit nothing, as the value won't be used anyway */
268                         return;
269                 }
270
271                 /* If one of the variables resides in memory, we can eliminate
272                    the register move from/to the temporary register with the
273                    order of getting the destination register and the load. */
274
275                 if (IS_INMEMORY(src->flags)) {
276 #if SIZEOF_VOID_P == 4
277                         if (IS_2_WORD_TYPE(src->type))
278                                 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
279                         else
280 #endif
281                                 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
282                         s1 = emit_load(jd, iptr, src, d);
283                 }
284                 else {
285                         s1 = emit_load(jd, iptr, src, REG_IFTMP);
286 #if SIZEOF_VOID_P == 4
287                         if (IS_2_WORD_TYPE(src->type))
288                                 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
289                         else
290 #endif
291                                 d = codegen_reg_of_var(iptr->opc, dst, s1);
292                 }
293
294                 if (s1 != d) {
295                         switch (dst->type) {
296 #if SIZEOF_VOID_P == 8
297                         case TYPE_INT:
298                         case TYPE_LNG:
299                         case TYPE_ADR:
300                                 M_MOV(s1, d);
301                                 break;
302 #else
303                         case TYPE_INT:
304                         case TYPE_ADR:
305                                 M_MOV(s1, d);
306                                 break;
307                         case TYPE_LNG:
308                                 M_LNGMOVE(s1, d);
309                                 break;
310 #endif
311                         case TYPE_FLT:
312                                 M_FMOV(s1, d);
313                                 break;
314                         case TYPE_DBL:
315                                 M_DMOV(s1, d);
316                                 break;
317                         default:
318                                 vm_abort("emit_copy: unknown type %d", dst->type);
319                         }
320                 }
321
322                 emit_store(jd, iptr, dst, d);
323         }
324 }
325
326
327 /* emit_iconst *****************************************************************
328
329    XXX
330
331 *******************************************************************************/
332
333 void emit_iconst(codegendata *cd, s4 d, s4 value)
334 {
335         s4 disp;
336
337     if ((value >= -32768) && (value <= 32767))
338         M_IADD_IMM(REG_ZERO, value, d);
339         else if ((value >= 0) && (value <= 0xffff))
340         M_OR_IMM(REG_ZERO, value, d);
341         else {
342         disp = dseg_add_s4(cd, value);
343         M_ILD(d, REG_PV, disp);
344     }
345 }
346
347
348 /* emit_lconst *****************************************************************
349
350    XXX
351
352 *******************************************************************************/
353
354 void emit_lconst(codegendata *cd, s4 d, s8 value)
355 {
356         s4 disp;
357
358 #if SIZEOF_VOID_P == 8
359         if ((value >= -32768) && (value <= 32767))
360                 M_LADD_IMM(REG_ZERO, value, d);
361         else if ((value >= 0) && (value <= 0xffff))
362                 M_OR_IMM(REG_ZERO, value, d);
363         else {
364                 disp = dseg_add_s8(cd, value);
365                 M_LLD(d, REG_PV, disp);
366         }
367 #else
368         disp = dseg_add_s8(cd, value);
369         M_LLD(d, REG_PV, disp);
370 #endif
371 }
372
373
374 /* emit_branch *****************************************************************
375
376    Emits the code for conditional and unconditional branchs.
377
378    NOTE: The reg argument may contain two packed registers.
379
380 *******************************************************************************/
381
382 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 opt)
383 {
384         s4 checkdisp;
385         s4 branchdisp;
386
387         /* calculate the different displacements */
388
389         checkdisp  = (disp - 4);
390         branchdisp = (disp - 4) >> 2;
391
392         /* check which branch to generate */
393
394         if (condition == BRANCH_UNCONDITIONAL) {
395                 /* check displacement for overflow */
396
397                 if ((checkdisp < (s4) 0xffff8000) || (checkdisp > (s4) 0x00007fff)) {
398                         /* if the long-branches flag isn't set yet, do it */
399
400                         if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
401                                 cd->flags |= (CODEGENDATA_FLAG_ERROR |
402                                                           CODEGENDATA_FLAG_LONGBRANCHES);
403                         }
404
405                         vm_abort("emit_branch: emit unconditional long-branch code");
406                 }
407                 else {
408                         M_BR(branchdisp);
409                         M_NOP;
410                 }
411         }
412         else {
413                 /* and displacement for overflow */
414
415                 if ((checkdisp < (s4) 0xffff8000) || (checkdisp > (s4) 0x00007fff)) {
416                         /* if the long-branches flag isn't set yet, do it */
417
418                         if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
419                                 cd->flags |= (CODEGENDATA_FLAG_ERROR |
420                                                           CODEGENDATA_FLAG_LONGBRANCHES);
421                         }
422
423                         switch (condition) {
424                         case BRANCH_EQ:
425                                 M_BNE(GET_HIGH_REG(reg), GET_LOW_REG(reg), 5);
426                                 break;
427                         case BRANCH_NE:
428                                 M_BEQ(GET_HIGH_REG(reg), GET_LOW_REG(reg), 5);
429                                 break;
430                         case BRANCH_LT:
431                                 M_BGEZ(reg, 5);
432                                 break;
433                         case BRANCH_GE:
434                                 M_BLTZ(reg, 5);
435                                 break;
436                         case BRANCH_GT:
437                                 M_BLEZ(reg, 5);
438                                 break;
439                         case BRANCH_LE:
440                                 M_BGTZ(reg, 5);
441                                 break;
442                         default:
443                                 vm_abort("emit_branch: unknown condition %d", condition);
444                         }
445
446                         /* The actual branch code which is over-jumped (NOTE: we
447                            don't use a branch delay slot here). */
448
449                         M_LUI(REG_ITMP3, branchdisp >> 16);
450                         M_OR_IMM(REG_ITMP3, branchdisp, REG_ITMP3);
451                         M_AADD(REG_PV, REG_ITMP3, REG_ITMP3);
452                         M_JMP(REG_ITMP3);
453                         M_NOP;
454
455                 }
456                 else {
457                         switch (condition) {
458                         case BRANCH_EQ:
459                                 M_BEQ(GET_HIGH_REG(reg), GET_LOW_REG(reg), branchdisp);
460                                 break;
461                         case BRANCH_NE:
462                                 M_BNE(GET_HIGH_REG(reg), GET_LOW_REG(reg), branchdisp);
463                                 break;
464                         case BRANCH_LT:
465                                 M_BLTZ(reg, branchdisp);
466                                 break;
467                         case BRANCH_GE:
468                                 M_BGEZ(reg, branchdisp);
469                                 break;
470                         case BRANCH_GT:
471                                 M_BGTZ(reg, branchdisp);
472                                 break;
473                         case BRANCH_LE:
474                                 M_BLEZ(reg, branchdisp);
475                                 break;
476                         default:
477                                 vm_abort("emit_branch: unknown condition %d", condition);
478                         }
479
480                         /* branch delay */
481                         M_NOP;
482                 }
483         }
484 }
485
486
487 /* emit_arithmetic_check *******************************************************
488
489    Emit an ArithmeticException check.
490
491 *******************************************************************************/
492
493 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
494 {
495         if (INSTRUCTION_MUST_CHECK(iptr)) {
496                 M_BNEZ(reg, 2);
497                 M_NOP;
498                 M_ALD_INTERN(REG_ZERO, REG_ZERO, TRAP_ArithmeticException);
499         }
500 }
501
502
503 /* emit_arrayindexoutofbounds_check ********************************************
504
505    Emit an ArrayIndexOutOfBoundsException check.
506
507 *******************************************************************************/
508
509 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
510 {
511         if (INSTRUCTION_MUST_CHECK(iptr)) {
512                 M_ILD_INTERN(REG_ITMP3, s1, OFFSET(java_array_t, size));
513                 M_CMPULT(s2, REG_ITMP3, REG_ITMP3);
514                 M_BNEZ(REG_ITMP3, 2);
515                 M_NOP;
516                 M_ALD_INTERN(s2, REG_ZERO, TRAP_ArrayIndexOutOfBoundsException);
517         }
518 }
519
520
521 /* emit_arraystore_check *******************************************************
522
523    Emit an ArrayStoreException check.
524
525 *******************************************************************************/
526
527 void emit_arraystore_check(codegendata *cd, instruction *iptr)
528 {
529         if (INSTRUCTION_MUST_CHECK(iptr)) {
530                 M_BNEZ(REG_RESULT, 2);
531                 M_NOP;
532                 M_ALD_INTERN(REG_RESULT, REG_ZERO, TRAP_ArrayStoreException);
533         }
534 }
535
536
537 /* emit_classcast_check ********************************************************
538
539    Emit a ClassCastException check.
540
541 *******************************************************************************/
542
543 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
544 {
545         if (INSTRUCTION_MUST_CHECK(iptr)) {
546                 switch (condition) {
547                 case ICMD_IFEQ:
548                         M_BNEZ(reg, 2);
549                         break;
550
551                 case ICMD_IFNE:
552                         M_BEQZ(reg, 2);
553                         break;
554
555                 case ICMD_IFLE:
556                         M_BGTZ(reg, 2);
557                         break;
558
559                 default:
560                         vm_abort("emit_classcast_check: unknown condition %d", condition);
561                 }
562
563                 M_NOP;
564                 M_ALD_INTERN(s1, REG_ZERO, TRAP_ClassCastException);
565         }
566 }
567
568
569 /* emit_nullpointer_check ******************************************************
570
571    Emit a NullPointerException check.
572
573 *******************************************************************************/
574
575 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
576 {
577         if (INSTRUCTION_MUST_CHECK(iptr)) {
578                 M_BNEZ(reg, 2);
579                 M_NOP;
580                 M_ALD_INTERN(REG_ZERO, REG_ZERO, TRAP_NullPointerException);
581         }
582 }
583
584
585 /* emit_exception_check ********************************************************
586
587    Emit an Exception check.
588
589 *******************************************************************************/
590
591 void emit_exception_check(codegendata *cd, instruction *iptr)
592 {
593         if (INSTRUCTION_MUST_CHECK(iptr)) {
594                 M_BNEZ(REG_RESULT, 2);
595                 M_NOP;
596                 M_ALD_INTERN(REG_RESULT, REG_ZERO, TRAP_CHECK_EXCEPTION);
597         }
598 }
599
600
601 /* emit_trap_compiler **********************************************************
602
603    Emit a trap instruction which calls the JIT compiler.
604
605 *******************************************************************************/
606
607 void emit_trap_compiler(codegendata *cd)
608 {
609         M_ALD_INTERN(REG_METHODPTR, REG_ZERO, TRAP_COMPILER);
610 }
611
612
613 /* emit_trap *******************************************************************
614
615    Emit a trap instruction and return the original machine code.
616
617 *******************************************************************************/
618
619 uint32_t emit_trap(codegendata *cd)
620 {
621         uint32_t mcode;
622
623         /* Get machine code which is patched back in later. The
624            trap is 1 instruction word long. */
625
626         mcode = *((uint32_t *) cd->mcodeptr);
627
628         M_ALD_INTERN(REG_ZERO, REG_ZERO, TRAP_PATCHER);
629
630         return mcode;
631 }
632
633
634 /* emit_verbosecall_enter ******************************************************
635
636    Generates the code for the call trace.
637
638 *******************************************************************************/
639
640 #if !defined(NDEBUG)
641 void emit_verbosecall_enter(jitdata *jd)
642 {
643         methodinfo   *m;
644         codeinfo     *code;
645         codegendata  *cd;
646         registerdata *rd;
647         methoddesc   *md;
648         s4            disp;
649         s4            i, j, t;
650
651         /* get required compiler data */
652
653         m    = jd->m;
654         code = jd->code;
655         cd   = jd->cd;
656         rd   = jd->rd;
657
658         md = m->parseddesc;
659
660         /* mark trace code */
661
662         M_NOP;
663
664         M_LDA(REG_SP, REG_SP, -(PA_SIZE + (2 + ARG_CNT + TMP_CNT) * 8));
665         M_AST(REG_RA, REG_SP, PA_SIZE + 1 * 8);
666
667         /* save argument registers (we store the registers as address
668            types, so it's correct for MIPS32 too) */
669
670         for (i = 0; i < INT_ARG_CNT; i++)
671                 M_AST(abi_registers_integer_argument[i], REG_SP, PA_SIZE + (2 + i) * 8);
672
673         for (i = 0; i < FLT_ARG_CNT; i++)
674                 M_DST(abi_registers_float_argument[i], REG_SP, PA_SIZE + (2 + INT_ARG_CNT + i) * 8);
675
676         /* save temporary registers for leaf methods */
677
678         if (code_is_leafmethod(code)) {
679                 for (i = 0; i < INT_TMP_CNT; i++)
680                         M_AST(rd->tmpintregs[i], REG_SP, PA_SIZE + (2 + ARG_CNT + i) * 8);
681
682                 for (i = 0; i < FLT_TMP_CNT; i++)
683                         M_DST(rd->tmpfltregs[i], REG_SP, PA_SIZE + (2 + ARG_CNT + INT_TMP_CNT + i) * 8);
684         }
685
686         /* Load float arguments into integer registers.  MIPS32 has less
687            float argument registers than integer ones, we need to check
688            that. */
689
690         for (i = 0; i < md->paramcount && i < INT_ARG_CNT && i < FLT_ARG_CNT; i++) {
691                 t = md->paramtypes[i].type;
692
693                 if (IS_FLT_DBL_TYPE(t)) {
694                         if (IS_2_WORD_TYPE(t)) {
695                                 M_DST(abi_registers_float_argument[i], REG_SP, 0 * 8);
696                                 M_LLD(abi_registers_integer_argument[i], REG_SP, 0 * 8);
697                         }
698                         else {
699                                 M_FST(abi_registers_float_argument[i], REG_SP, 0 * 8);
700                                 M_ILD(abi_registers_integer_argument[i], REG_SP, 0 * 8);
701                         }
702                 }
703         }
704
705 #if SIZEOF_VOID_P == 4
706                 for (i = 0, j = 0; i < md->paramcount && i < TRACE_ARGS_NUM; i++) {
707                         t = md->paramtypes[i].type;
708
709                         if (IS_INT_LNG_TYPE(t)) {
710                                 if (IS_2_WORD_TYPE(t)) {
711                                         M_ILD(abi_registers_integer_argument[j], REG_SP, PA_SIZE + (2 + i) * 8);
712                                         M_ILD(abi_registers_integer_argument[j + 1], REG_SP, PA_SIZE + (2 + i) * 8 + 4);
713                                 }
714                                 else {
715 # if WORDS_BIGENDIAN == 1
716                                         M_MOV(REG_ZERO, abi_registers_integer_argument[j]);
717                                         M_ILD(abi_registers_integer_argument[j + 1], REG_SP, PA_SIZE + (2 + i) * 8);
718 # else
719                                         M_ILD(abi_registers_integer_argument[j], REG_SP, PA_SIZE + (2 + i) * 8);
720                                         M_MOV(REG_ZERO, abi_registers_integer_argument[j + 1]);
721 # endif
722                                 }
723                                 j += 2;
724                         }
725                 }
726 #endif
727
728         disp = dseg_add_address(cd, m);
729         M_ALD(REG_ITMP1, REG_PV, disp);
730         M_AST(REG_ITMP1, REG_SP, PA_SIZE + 0 * 8);
731         disp = dseg_add_functionptr(cd, builtin_verbosecall_enter);
732         M_ALD(REG_ITMP3, REG_PV, disp);
733         M_JSR(REG_RA, REG_ITMP3);
734         M_NOP;
735
736         /* restore argument registers */
737
738         for (i = 0; i < INT_ARG_CNT; i++)
739                 M_ALD(abi_registers_integer_argument[i], REG_SP, PA_SIZE + (2 + i) * 8);
740
741         for (i = 0; i < FLT_ARG_CNT; i++)
742                 M_DLD(abi_registers_float_argument[i], REG_SP, PA_SIZE + (2 + INT_ARG_CNT + i) * 8);
743
744         /* restore temporary registers for leaf methods */
745
746         if (code_is_leafmethod(code)) {
747                 for (i = 0; i < INT_TMP_CNT; i++)
748                         M_ALD(rd->tmpintregs[i], REG_SP, PA_SIZE + (2 + ARG_CNT + i) * 8);
749
750                 for (i = 0; i < FLT_TMP_CNT; i++)
751                         M_DLD(rd->tmpfltregs[i], REG_SP, PA_SIZE + (2 + ARG_CNT + INT_TMP_CNT + i) * 8);
752         }
753
754         M_ALD(REG_RA, REG_SP, PA_SIZE + 1 * 8);
755         M_LDA(REG_SP, REG_SP, PA_SIZE + (2 + ARG_CNT + TMP_CNT) * 8);
756
757         /* mark trace code */
758
759         M_NOP;
760 }
761 #endif /* !defined(NDEBUG) */
762
763
764 /* emit_verbosecall_exit *******************************************************
765
766    Generates the code for the call trace.
767
768    void builtin_verbosecall_exit(s8 l, double d, float f, methodinfo *m);
769
770 *******************************************************************************/
771
772 #if !defined(NDEBUG)
773 void emit_verbosecall_exit(jitdata *jd)
774 {
775         methodinfo   *m;
776         codegendata  *cd;
777         registerdata *rd;
778         methoddesc   *md;
779         s4            disp;
780
781         /* get required compiler data */
782
783         m  = jd->m;
784         cd = jd->cd;
785         rd = jd->rd;
786
787         md = m->parseddesc;
788
789         /* mark trace code */
790
791         M_NOP;
792
793 #if SIZEOF_VOID_P == 8
794         M_ASUB_IMM(REG_SP, 4 * 8, REG_SP);          /* keep stack 16-byte aligned */
795         M_AST(REG_RA, REG_SP, 0 * 8);
796
797         M_LST(REG_RESULT, REG_SP, 1 * 8);
798         M_DST(REG_FRESULT, REG_SP, 2 * 8);
799
800         M_MOV(REG_RESULT, REG_A0);
801         M_DMOV(REG_FRESULT, REG_FA1);
802         M_FMOV(REG_FRESULT, REG_FA2);
803
804         disp = dseg_add_address(cd, m);
805         M_ALD(REG_A4, REG_PV, disp);
806 #else
807         M_ASUB_IMM(REG_SP, (8*4 + 4 * 8), REG_SP);
808         M_AST(REG_RA, REG_SP, 8*4 + 0 * 8);
809
810         M_LST(REG_RESULT_PACKED, REG_SP, 8*4 + 1 * 8);
811         M_DST(REG_FRESULT, REG_SP, 8*4 + 2 * 8);
812
813         switch (md->returntype.type) {
814         case TYPE_LNG:
815                 M_LNGMOVE(REG_RESULT_PACKED, REG_A0_A1_PACKED);
816                 break;
817
818         default:
819 # if WORDS_BIGENDIAN == 1
820                 M_MOV(REG_ZERO, REG_A0);
821                 M_MOV(REG_RESULT, REG_A1);
822 # else
823                 M_MOV(REG_RESULT, REG_A0);
824                 M_MOV(REG_ZERO, REG_A1);
825 # endif
826         }
827
828         M_LLD(REG_A2_A3_PACKED, REG_SP, 8*4 + 2 * 8);
829         M_FST(REG_FRESULT, REG_SP, 4*4 + 0 * 4);
830
831         disp = dseg_add_address(cd, m);
832         M_ALD(REG_ITMP1, REG_PV, disp);
833         M_AST(REG_ITMP1, REG_SP, 4*4 + 1 * 4);
834 #endif
835
836         disp = dseg_add_functionptr(cd, builtin_verbosecall_exit);
837         M_ALD(REG_ITMP3, REG_PV, disp);
838         M_JSR(REG_RA, REG_ITMP3);
839         M_NOP;
840
841 #if SIZEOF_VOID_P == 8
842         M_DLD(REG_FRESULT, REG_SP, 2 * 8);
843         M_LLD(REG_RESULT, REG_SP, 1 * 8);
844
845         M_ALD(REG_RA, REG_SP, 0 * 8);
846         M_AADD_IMM(REG_SP, 4 * 8, REG_SP);
847 #else
848         M_DLD(REG_FRESULT, REG_SP, 8*4 + 2 * 8);
849         M_LLD(REG_RESULT_PACKED, REG_SP, 8*4 + 1 * 8);
850
851         M_ALD(REG_RA, REG_SP, 8*4 + 0 * 8);
852         M_AADD_IMM(REG_SP, 8*4 + 4 * 8, REG_SP);
853 #endif
854
855         /* mark trace code */
856
857         M_NOP;
858 }
859 #endif /* !defined(NDEBUG) */
860
861
862 /*
863  * These are local overrides for various environment variables in Emacs.
864  * Please do not remove this and leave it at the end of the file, where
865  * Emacs will automagically detect them.
866  * ---------------------------------------------------------------------
867  * Local variables:
868  * mode: c
869  * indent-tabs-mode: t
870  * c-basic-offset: 4
871  * tab-width: 4
872  * End:
873  * vim:noexpandtab:sw=4:ts=4:
874  */