1 /* src/vm/jit/m68k/emit.c
3 Copyright (C) 1996-2005, 2006, 2007 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 $Id: arch.h 5330 2006-09-05 18:43:12Z edwin $
33 #include "vm/jit/emit-common.h"
34 #include "vm/exceptions.h"
35 #include "vm/jit/asmpart.h"
37 #include "vm/builtin.h"
38 #include "mm/memory.h"
43 * Loads an immededat operand into data register
45 void emit_mov_imm_reg (codegendata *cd, s4 imm, s4 dreg)
47 if ((imm & 0x000000FF) == imm) {
49 *((s2*)cd->mcodeptr) = 0x7000 | (dreg << 9) | imm; /* MOVEQ.L */
51 } else if ((imm & 0xFFFF0000) != 0) {
53 OPWORD( ((2<<6) | (dreg << 3) | 0), 7, 4);
54 *((s4*)cd->mcodeptr) = (s4)imm;
58 OPWORD( ((3<<6) | (dreg << 3) | 0), 7, 4);
59 *((s2*)cd->mcodeptr) = (s2)imm;
64 /* emit_copy *******************************************************************
66 Generates a register/memory to register/memory copy.
68 *******************************************************************************/
69 void emit_copy(jitdata *jd, instruction *iptr, varinfo *src, varinfo *dst)
74 /* get required compiler data */
78 if ((src->vv.regoff != dst->vv.regoff) ||
79 (IS_INMEMORY(src->flags ^ dst->flags))) {
81 /* If one of the variables resides in memory, we can eliminate
82 the register move from/to the temporary register with the
83 order of getting the destination register and the load. */
85 if (IS_INMEMORY(src->flags)) {
86 if (IS_LNG_TYPE(src->type))
87 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
89 d = codegen_reg_of_var(iptr->opc, dst, REG_IFTMP);
91 s1 = emit_load(jd, iptr, src, d);
93 if (IS_LNG_TYPE(src->type))
94 s1 = emit_load(jd, iptr, src, REG_ITMP12_PACKED);
96 s1 = emit_load(jd, iptr, src, REG_IFTMP);
98 d = codegen_reg_of_var(iptr->opc, dst, s1);
103 case TYPE_INT: M_INTMOVE(s1, d); break;
104 case TYPE_ADR: M_ADRMOVE(s1, d); break;
105 case TYPE_LNG: M_LNGMOVE(s1, d); break;
106 #if !defined(ENABLE_SOFTFLOAT)
107 case TYPE_FLT: M_FLTMOVE(s1, d); break;
108 case TYPE_DBL: M_DBLMOVE(s1, d); break;
110 case TYPE_FLT: M_INTMOVE(s1, d); break;
111 case TYPE_DBL: M_LNGMOVE(s1, d); break;
116 emit_store(jd, iptr, dst, d);
119 /* emit_store ******************************************************************
121 Emits a possible store of the destination operand.
123 *******************************************************************************/
125 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
129 /* get required compiler data */
133 if (IS_INMEMORY(dst->flags)) {
137 #if defined(ENABLE_SOFTFLOAT)
141 M_LST(d, REG_SP, dst->vv.regoff * 4);
143 #if defined(ENABLE_SOFTFLOAT)
147 M_IST(d, REG_SP, dst->vv.regoff * 4);
150 M_AST(d, REG_SP, dst->vv.regoff * 4);
152 #if !defined(ENABLE_SOFTFLOAT)
154 M_DST(d, REG_SP, dst->vv.regoff * 4);
157 M_FST(d, REG_SP, dst->vv.regoff * 4);
165 /* emit_load *******************************************************************
167 Emits a possible load of an operand.
169 *******************************************************************************/
170 s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
176 /* get required compiler data */
180 if (IS_INMEMORY(src->flags)) {
183 disp = src->vv.regoff * 4;
186 #if defined(ENABLE_SOFTFLOAT)
190 M_ILD(tempreg, REG_SP, disp);
192 #if defined(ENABLE_SOFTFLOAT)
196 M_LLD(tempreg, REG_SP, disp);
199 M_ALD(tempreg, REG_SP, disp);
201 #if !defined(ENABLE_SOFTFLOAT)
203 M_FLD(tempreg, REG_SP, disp);
206 M_DLD(tempreg, REG_SP, disp);
212 if (IS_FLT_DBL_TYPE(src->type)) {
213 if (IS_2_WORD_TYPE(src->type)) {
214 M_DLD(tempreg, REG_SP, disp);
216 M_FLD(tempreg, REG_SP, disp);
219 if (IS_2_WORD_TYPE(src->type)) {
220 M_LLD(tempreg, REG_SP, disp);
222 M_ILD(tempreg, REG_SP, disp);
230 reg = src->vv.regoff;
236 /* emit_patcher_stubs **********************************************************
238 Generates the code for the patcher stubs.
240 *******************************************************************************/
241 void emit_patcher_stubs(jitdata *jd)
251 /* get required compiler data */
255 /* generate code patching stub call code */
259 for (pref = cd->patchrefs; pref != NULL; pref = pref->next) {
260 /* check code segment size */
264 /* Get machine code which is patched back in later. A
265 `bsr.l' is 6 bytes long. */
267 savedmcodeptr = cd->mcodebase + pref->branchpos;
268 mcode = *((u8 *) savedmcodeptr);
270 /* patch in `bsr.l' to call the following code */
272 tmpmcodeptr = cd->mcodeptr; /* save current mcodeptr */
273 cd->mcodeptr = savedmcodeptr; /* set mcodeptr to patch position */
275 M_BSR_IMM(tmpmcodeptr - (savedmcodeptr + PATCHER_CALL_SIZE) + 4);
277 cd->mcodeptr = tmpmcodeptr; /* restore the current mcodeptr */
280 M_IPUSH(REG_ITMP3); /* FIXME why, and restore where ? */
282 /* move pointer to java_objectheader onto stack */
284 #if defined(ENABLE_THREADS)
285 (void) dseg_add_unique_address(cd, NULL); /* flcword */
286 (void) dseg_add_unique_address(cd, lock_get_initial_lock_word());
287 disp = dseg_add_unique_address(cd, NULL); /* vftbl */
289 assert(0); /* The next lines are wrong */
290 M_MOV_IMM(0, REG_ITMP3);
292 M_AADD_IMM(REG_ITMP3, disp);
298 /* push move machine code bytes and classinfo pointer */
300 M_IPUSH_IMM(mcode >> 32);
302 M_IPUSH_IMM(pref->ref);
303 M_IPUSH_IMM(pref->patcher);
305 M_JMP_IMM(asm_patcher_wrapper);
308 s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
314 assert(src->type == TYPE_LNG);
316 /* get required compiler data */
319 if (IS_INMEMORY(src->flags)) {
322 disp = src->vv.regoff * 4;
323 M_ILD(tempreg, REG_SP, disp + 4);
326 reg = GET_LOW_REG(src->vv.regoff);
330 s4 emit_load_high(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
336 assert(src->type == TYPE_LNG);
338 /* get required compiler data */
341 if (IS_INMEMORY(src->flags)) {
343 disp = src->vv.regoff * 4;
344 M_ILD(tempreg, REG_SP, disp);
347 reg = GET_HIGH_REG(src->vv.regoff);
351 /* emit_branch *****************************************************************
353 Emits the code for conditional and unconditional branchs.
355 *******************************************************************************/
356 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 opt)
358 /* calculate the different displacements */
359 /* PC is a at branch instruction + 2 */
360 /* coditional and uncondition branching work the same way */
361 /* short branches have signed 16 bit offset */
362 /* long branches are signed 32 bit */
363 /* the 8 bit offset branching instructions are not used */
367 /* check displacement for overflow */
368 if ((disp & 0x0000FFFF) != disp) {
369 if (!CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
370 cd->flags |= (CODEGENDATA_FLAG_ERROR | CODEGENDATA_FLAG_LONGBRANCHES);
374 /* check which branch to generate */
376 if (condition == BRANCH_UNCONDITIONAL) {
377 if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
383 if (CODEGENDATA_HAS_FLAG_LONGBRANCHES(cd)) {
411 vm_abort("emit_branch: unknown condition %d", condition);
440 vm_abort("emit_branch: unknown condition %d", condition);
449 * Trace functions. Implement -verbose:call flag
450 * code marked by real NOP, but performance is no matter when using -verbose:call :)
452 void emit_verbosecall_enter(jitdata* jd)
461 if (!JITDATA_HAS_FLAG_VERBOSECALL(jd))
464 /* get required compiler data */
470 /* mark trace code */
473 M_LINK(REG_FP, -16*4);
476 /* builtin_verbosecall_enter takes all args as s8 type */
477 /* TRACE_ARGS_NUM is the number of args the builtin_verbosecall_enter expects */
480 disp = 16*4 + 4 + 4; /* points to old argument stack initially */
482 /* travel up stack to the first argument of the function which needs to be copied */
483 for (i=0; (i < md->paramcount) && (i < TRACE_ARGS_NUM); i++) {
485 if (IS_2_WORD_TYPE(md->paramtypes[i].type)) {
490 /* disp now points to the first arg which gets copied to the trace stack, relative to REG_SP! */
491 for (i=TRACE_ARGS_NUM-1; i>=0; --i) {
492 if (i < md->paramcount) {
493 /* traced function has such an argument */
494 t = md->paramtypes[i].type;
496 if (IS_2_WORD_TYPE(t)) {
497 /* copy from original argument stack */
498 M_ILD(REG_ITMP1, REG_SP, disp);
500 M_ILD(REG_ITMP1, REG_SP, disp);
503 /* displacment is increased as 4 byte on original stack but 8 byte on trace stack */
504 M_ILD(REG_ITMP1, REG_SP, disp);
510 /* function has no arg here, push nothing and adapt displacement */
516 M_JSR_IMM(builtin_verbosecall_enter);
517 /* pop arguments off stack */
518 M_AADD_IMM(TRACE_ARGS_NUM*8+4, REG_SP);
524 void emit_verbosecall_exit(jitdata* jd)
531 if (!JITDATA_HAS_FLAG_VERBOSECALL(jd))
534 /* get required compiler data */
540 /* void builtin_verbosecall_exit(s8 l, double d, float f, methodinfo *m); */
543 /* mark trace code */
547 M_IPUSH_IMM(m); /* push methodinfo */
549 M_IPUSH_IMM(0); /* TODO push float result */
551 M_IPUSH_IMM(0); /* TODO push double result */
552 M_IPUSH_IMM(0); /* TODO push double result */
554 M_IPUSH(GET_HIGH_REG(REG_RESULT_PACKED))
555 M_IPUSH(GET_LOW_REG(REG_RESULT_PACKED)) /* push long result */
558 M_JSR_IMM(builtin_verbosecall_exit);
560 /* poping result registers from stack */
561 M_IPOP(GET_LOW_REG(REG_RESULT_PACKED))
562 M_IPOP(GET_HIGH_REG(REG_RESULT_PACKED))
565 /* that is wrong of course, overwrites registers and stuff */
566 M_IPOP(0); /* TODO: pop double result */
567 M_IPOP(0); /* TODO: pop double result */
569 M_IPOP(0); /* TODO: pop float result */
571 M_AADD_IMM(3*4, REG_SP);
573 M_AADD_IMM(4, REG_SP); /* remove rest of stack */
579 /* emit_classcast_check ********************************************************
581 Emit a ClassCastException check.
583 *******************************************************************************/
585 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
587 if (INSTRUCTION_MUST_CHECK(iptr)) {
602 vm_abort("emit_classcast_check: unknown condition %d", condition);
604 M_TRAP_SETREGISTER(s1);
605 M_TRAP(EXCEPTION_HARDWARE_CLASSCAST);
609 /* emit_arrayindexoutofbounds_check ********************************************
611 Emit a ArrayIndexOutOfBoundsException check.
613 *******************************************************************************/
614 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
616 if (INSTRUCTION_MUST_CHECK(iptr)) {
617 M_ILD(REG_ITMP3, s1, OFFSET(java_arrayheader, size));
618 M_ICMP(REG_ITMP3, s2);
620 /*M_ALD_INTERN(s2, REG_ZERO, EXCEPTION_LOAD_DISP_ARRAYINDEXOUTOFBOUNDS);*/
621 M_ILLEGAL; /*FIXME */
625 /* emit_nullpointer_check ******************************************************
627 Emit a NullPointerException check.
629 *******************************************************************************/
630 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
632 if (INSTRUCTION_MUST_CHECK(iptr)) {
633 /* did like to assert on TYPE_ADR, but not possible in here */
634 /* so assert before each emit_nullpointer_check */
637 /*M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_LOAD_DISP_NULLPOINTER);*/
642 /* emit_arithmetic_check *******************************************************
644 Emit an ArithmeticException check.
646 *******************************************************************************/
648 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
650 if (INSTRUCTION_MUST_CHECK(iptr)) {
653 /*M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_HARDWARE_ARITHMETIC);*/
654 M_ILLEGAL; /* FIXME */
658 /* emit_exception_check_areg **************************************************
660 Emit an Exception check, tested register is address REG_RESULT
662 *******************************************************************************/
663 void emit_exception_check_areg(codegendata *cd, instruction *iptr)
665 if (INSTRUCTION_MUST_CHECK(iptr)) {
668 /*M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_HARDWARE_EXCEPTION);*/
672 /* emit_exception_check_ireg **************************************************
674 Emit an Exception check. Teste register is integer REG_RESULT
676 *******************************************************************************/
677 void emit_exception_check_ireg(codegendata *cd, instruction *iptr)
679 if (INSTRUCTION_MUST_CHECK(iptr)) {
682 /*M_ALD_INTERN(REG_ZERO, REG_ZERO, EXCEPTION_HARDWARE_EXCEPTION);*/