1 /* src/vm/jit/i386/emit.c - i386 code emitter functions
3 Copyright (C) 1996-2005, 2006, 2007, 2008, 2009
4 CACAOVM - Verein zur Foerderung der freien virtuellen Maschine CACAO
6 This file is part of CACAO.
8 This program is free software; you can redistribute it and/or
9 modify it under the terms of the GNU General Public License as
10 published by the Free Software Foundation; either version 2, or (at
11 your option) any later version.
13 This program is distributed in the hope that it will be useful, but
14 WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
33 #include "vm/jit/i386/codegen.h"
34 #include "vm/jit/i386/emit.h"
35 #include "vm/jit/i386/md-abi.h"
37 #include "mm/memory.hpp"
39 #include "threads/lock.hpp"
41 #include "vm/options.h"
42 #include "vm/statistics.h"
44 #include "vm/jit/abi.h"
45 #include "vm/jit/asmpart.h"
46 #include "vm/jit/dseg.h"
47 #include "vm/jit/emit-common.hpp"
48 #include "vm/jit/jit.hpp"
49 #include "vm/jit/patcher-common.hpp"
50 #include "vm/jit/replace.hpp"
51 #include "vm/jit/trace.hpp"
52 #include "vm/jit/trap.hpp"
55 /* emit_load ******************************************************************
57 Emits a possible load of an operand.
59 *******************************************************************************/
61 inline s4 emit_load(jitdata *jd, instruction *iptr, varinfo *src, s4 tempreg)
67 /* get required compiler data */
71 if (IS_INMEMORY(src->flags)) {
74 disp = src->vv.regoff;
79 M_ILD(tempreg, REG_SP, disp);
82 M_LLD(tempreg, REG_SP, disp);
85 M_FLD(tempreg, REG_SP, disp);
88 M_DLD(tempreg, REG_SP, disp);
91 vm_abort("emit_load: unknown type %d", src->type);
103 /* emit_load_low ************************************************************
105 Emits a possible load of the low 32-bits of an operand.
107 *******************************************************************************/
109 inline s4 emit_load_low(jitdata *jd, instruction *iptr, varinfo *src,s4 tempreg)
115 assert(src->type == TYPE_LNG);
117 /* get required compiler data */
122 if (IS_INMEMORY(src->flags)) {
125 disp = src->vv.regoff;
127 M_ILD(tempreg, REG_SP, disp);
132 reg = GET_LOW_REG(src->vv.regoff);
138 /* emit_load_high ***********************************************************
140 Emits a possible load of the high 32-bits of an operand.
142 *******************************************************************************/
144 inline s4 emit_load_high(jitdata *jd, instruction *iptr,varinfo *src,s4 tempreg)
150 /* get required compiler data */
152 assert(src->type == TYPE_LNG);
156 if (IS_INMEMORY(src->flags)) {
159 disp = src->vv.regoff;
161 M_ILD(tempreg, REG_SP, disp + 4);
166 reg = GET_HIGH_REG(src->vv.regoff);
172 /* emit_store ******************************************************************
174 Emits a possible store of the destination operand.
176 *******************************************************************************/
178 inline void emit_store(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
183 /* get required compiler data */
187 if (IS_INMEMORY(dst->flags)) {
190 disp = dst->vv.regoff;
195 M_IST(d, REG_SP, disp);
198 M_LST(d, REG_SP, disp);
201 M_FST(d, REG_SP, disp);
204 M_DST(d, REG_SP, disp);
207 vm_abort("emit_store: unknown type %d", dst->type);
213 /* emit_store_low **************************************************************
215 Emits a possible store of the low 32-bits of the destination
218 *******************************************************************************/
220 inline void emit_store_low(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
224 assert(dst->type == TYPE_LNG);
226 /* get required compiler data */
230 if (IS_INMEMORY(dst->flags)) {
232 M_IST(GET_LOW_REG(d), REG_SP, dst->vv.regoff);
237 /* emit_store_high *************************************************************
239 Emits a possible store of the high 32-bits of the destination
242 *******************************************************************************/
244 inline void emit_store_high(jitdata *jd, instruction *iptr, varinfo *dst, s4 d)
248 assert(dst->type == TYPE_LNG);
250 /* get required compiler data */
254 if (IS_INMEMORY(dst->flags)) {
256 M_IST(GET_HIGH_REG(d), REG_SP, dst->vv.regoff + 4);
261 /* emit_copy *******************************************************************
263 Generates a register/memory to register/memory copy.
265 *******************************************************************************/
267 void emit_copy(jitdata *jd, instruction *iptr)
274 /* get required compiler data */
278 /* get source and destination variables */
280 src = VAROP(iptr->s1);
281 dst = VAROP(iptr->dst);
283 if ((src->vv.regoff != dst->vv.regoff) ||
284 ((src->flags ^ dst->flags) & INMEMORY)) {
286 if ((src->type == TYPE_RET) || (dst->type == TYPE_RET)) {
287 /* emit nothing, as the value won't be used anyway */
291 /* If one of the variables resides in memory, we can eliminate
292 the register move from/to the temporary register with the
293 order of getting the destination register and the load. */
295 if (IS_INMEMORY(src->flags)) {
296 if (IS_LNG_TYPE(src->type))
297 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP12_PACKED);
299 d = codegen_reg_of_var(iptr->opc, dst, REG_ITMP1);
301 s1 = emit_load(jd, iptr, src, d);
304 if (IS_LNG_TYPE(src->type))
305 s1 = emit_load(jd, iptr, src, REG_ITMP12_PACKED);
307 s1 = emit_load(jd, iptr, src, REG_ITMP1);
309 d = codegen_reg_of_var(iptr->opc, dst, s1);
326 vm_abort("emit_copy: unknown type %d", src->type);
330 emit_store(jd, iptr, dst, d);
336 * Emits code updating the condition register by comparing one integer
337 * register to an immediate integer value.
339 void emit_icmp_imm(codegendata* cd, int reg, int32_t value)
341 M_CMP_IMM(value, reg);
345 /* emit_branch *****************************************************************
347 Emits the code for conditional and unconditional branchs.
349 *******************************************************************************/
351 void emit_branch(codegendata *cd, s4 disp, s4 condition, s4 reg, u4 options)
355 /* ATTENTION: a displacement overflow cannot happen */
357 /* check which branch to generate */
359 if (condition == BRANCH_UNCONDITIONAL) {
361 /* calculate the different displacements */
363 branchdisp = disp - BRANCH_UNCONDITIONAL_SIZE;
365 M_JMP_IMM(branchdisp);
368 /* calculate the different displacements */
370 branchdisp = disp - BRANCH_CONDITIONAL_SIZE;
404 vm_abort("emit_branch: unknown condition %d", condition);
410 /* emit_arithmetic_check *******************************************************
412 Emit an ArithmeticException check.
414 *******************************************************************************/
416 void emit_arithmetic_check(codegendata *cd, instruction *iptr, s4 reg)
418 if (INSTRUCTION_MUST_CHECK(iptr)) {
421 M_ALD_MEM(reg, TRAP_ArithmeticException);
426 /* emit_arrayindexoutofbounds_check ********************************************
428 Emit a ArrayIndexOutOfBoundsException check.
430 *******************************************************************************/
432 void emit_arrayindexoutofbounds_check(codegendata *cd, instruction *iptr, s4 s1, s4 s2)
434 if (INSTRUCTION_MUST_CHECK(iptr)) {
435 M_ILD(REG_ITMP3, s1, OFFSET(java_array_t, size));
436 M_CMP(REG_ITMP3, s2);
438 M_ALD_MEM(s2, TRAP_ArrayIndexOutOfBoundsException);
443 /* emit_arraystore_check *******************************************************
445 Emit an ArrayStoreException check.
447 *******************************************************************************/
449 void emit_arraystore_check(codegendata *cd, instruction *iptr)
451 if (INSTRUCTION_MUST_CHECK(iptr)) {
454 M_ALD_MEM(REG_RESULT, TRAP_ArrayStoreException);
459 /* emit_classcast_check ********************************************************
461 Emit a ClassCastException check.
463 *******************************************************************************/
465 void emit_classcast_check(codegendata *cd, instruction *iptr, s4 condition, s4 reg, s4 s1)
467 if (INSTRUCTION_MUST_CHECK(iptr)) {
485 vm_abort("emit_classcast_check: unknown condition %d", condition);
487 M_ALD_MEM(s1, TRAP_ClassCastException);
492 /* emit_nullpointer_check ******************************************************
494 Emit a NullPointerException check.
496 *******************************************************************************/
498 void emit_nullpointer_check(codegendata *cd, instruction *iptr, s4 reg)
500 if (INSTRUCTION_MUST_CHECK(iptr)) {
503 M_ALD_MEM(reg, TRAP_NullPointerException);
508 /* emit_exception_check ********************************************************
510 Emit an Exception check.
512 *******************************************************************************/
514 void emit_exception_check(codegendata *cd, instruction *iptr)
516 if (INSTRUCTION_MUST_CHECK(iptr)) {
519 M_ALD_MEM(REG_RESULT, TRAP_CHECK_EXCEPTION);
524 /* emit_trap_compiler **********************************************************
526 Emit a trap instruction which calls the JIT compiler.
528 *******************************************************************************/
530 void emit_trap_compiler(codegendata *cd)
532 M_ALD_MEM(REG_METHODPTR, TRAP_COMPILER);
535 /* emit_trap_countdown *********************************************************
537 Emit a countdown trap.
539 counter....absolute address of the counter variable
541 *******************************************************************************/
543 void emit_trap_countdown(codegendata *cd, s4 *counter)
545 M_ISUB_IMM_MEMABS(1, (s4) counter);
547 M_ALD_MEM(REG_METHODPTR, TRAP_COUNTDOWN);
550 /* emit_patcher_alignment ******************************************************
552 Emit NOP to ensure placement at an even address.
554 *******************************************************************************/
556 void emit_patcher_alignment(codegendata *cd)
558 if ((uintptr_t) cd->mcodeptr & 1)
563 /* emit_trap *******************************************************************
565 Emit a trap instruction and return the original machine code.
567 *******************************************************************************/
569 uint32_t emit_trap(codegendata *cd)
573 /* Get machine code which is patched back in later. The
574 trap is 2 bytes long. */
576 mcode = *((uint16_t *) cd->mcodeptr);
579 /* XXX this breaks GDB, so we disable it for now */
580 *(cd->mcodeptr++) = 0xcc;
586 return (uint32_t) mcode;
591 * Generates synchronization code to enter a monitor.
593 #if defined(ENABLE_THREADS)
594 void emit_monitor_enter(jitdata* jd, int32_t syncslot_offset)
598 // Get required compiler data.
599 methodinfo* m = jd->m;
600 codegendata* cd = jd->cd;
602 align_off = cd->stackframesize ? 4 : 0;
604 if (m->flags & ACC_STATIC) {
605 M_MOV_IMM(&m->clazz->object.header, REG_ITMP1);
608 M_ALD(REG_ITMP1, REG_SP, cd->stackframesize * 8 + 4 + align_off);
611 M_ALD_MEM(REG_ITMP1, TRAP_NullPointerException);
614 M_AST(REG_ITMP1, REG_SP, syncslot_offset);
615 M_AST(REG_ITMP1, REG_SP, 0 * 4);
616 M_MOV_IMM(LOCK_monitor_enter, REG_ITMP3);
623 * Generates synchronization code to leave a monitor.
625 #if defined(ENABLE_THREADS)
626 void emit_monitor_exit(jitdata* jd, int32_t syncslot_offset)
628 // Get required compiler data.
629 methodinfo* m = jd->m;
630 codegendata* cd = jd->cd;
632 M_ALD(REG_ITMP2, REG_SP, syncslot_offset);
634 /* we need to save the proper return value */
636 methoddesc* md = m->parseddesc;
638 switch (md->returntype.type) {
641 M_IST(REG_RESULT, REG_SP, syncslot_offset);
645 M_LST(REG_RESULT_PACKED, REG_SP, syncslot_offset);
649 emit_fstps_membase(cd, REG_SP, syncslot_offset);
653 emit_fstpl_membase(cd, REG_SP, syncslot_offset);
657 M_AST(REG_ITMP2, REG_SP, 0);
658 M_MOV_IMM(LOCK_monitor_exit, REG_ITMP3);
661 /* and now restore the proper return value */
663 switch (md->returntype.type) {
666 M_ILD(REG_RESULT, REG_SP, syncslot_offset);
670 M_LLD(REG_RESULT_PACKED, REG_SP, syncslot_offset);
674 emit_flds_membase(cd, REG_SP, syncslot_offset);
678 emit_fldl_membase(cd, REG_SP, syncslot_offset);
686 * Emit profiling code for method frequency counting.
688 #if defined(ENABLE_PROFILING)
689 void emit_profile_method(codegendata* cd, codeinfo* code)
691 M_MOV_IMM(code, REG_ITMP3);
692 M_IADD_IMM_MEMBASE(1, REG_ITMP3, OFFSET(codeinfo, frequency));
698 * Emit profiling code for basicblock frequency counting.
700 #if defined(ENABLE_PROFILING)
701 void emit_profile_basicblock(codegendata* cd, codeinfo* code, basicblock* bptr)
703 M_MOV_IMM(code->bbfrequency, REG_ITMP3);
704 M_IADD_IMM_MEMBASE(1, REG_ITMP3, bptr->nr * 4);
709 /* emit_verbosecall_enter ******************************************************
711 Generates the code for the call trace.
713 *******************************************************************************/
716 void emit_verbosecall_enter(jitdata *jd)
723 int32_t stackframesize;
725 int align_off; /* offset for alignment compensation */
727 if (!JITDATA_HAS_FLAG_VERBOSECALL(jd))
730 /* get required compiler data */
739 /* mark trace code */
743 /* keep stack 16-byte aligned */
745 stackframesize = 2 + TMP_CNT;
746 ALIGN_2(stackframesize);
748 M_ASUB_IMM(stackframesize * 8, REG_SP);
750 /* save temporary registers for leaf methods */
752 if (code_is_leafmethod(code)) {
753 for (i = 0; i < INT_TMP_CNT; i++)
754 M_IST(rd->tmpintregs[i], REG_SP, (2 + i) * 8);
757 /* no argument registers to save */
759 align_off = cd->stackframesize ? 4 : 0;
760 M_AST_IMM(m, REG_SP, 0 * 4);
761 M_AST_IMM(0, REG_SP, 1 * 4);
762 M_AST(REG_SP, REG_SP, 2 * 4);
763 M_IADD_IMM_MEMBASE(stackframesize * 8 + cd->stackframesize * 8 + 4 + align_off, REG_SP, 2 * 4);
764 M_MOV_IMM(trace_java_call_enter, REG_ITMP1);
767 /* no argument registers to restore */
769 /* restore temporary registers for leaf methods */
771 if (code_is_leafmethod(code)) {
772 for (i = 0; i < INT_TMP_CNT; i++)
773 M_ILD(rd->tmpintregs[i], REG_SP, (2 + i) * 8);
776 M_AADD_IMM(stackframesize * 8, REG_SP);
778 /* mark trace code */
782 #endif /* !defined(NDEBUG) */
785 /* emit_verbosecall_exit *******************************************************
787 Generates the code for the call trace.
789 *******************************************************************************/
792 void emit_verbosecall_exit(jitdata *jd)
799 if (!JITDATA_HAS_FLAG_VERBOSECALL(jd))
802 /* get required compiler data */
810 /* mark trace code */
814 /* keep stack 16-byte aligned */
816 M_ASUB_IMM(4 + 4 + 8, REG_SP);
818 /* save return value */
820 switch (md->returntype.type) {
823 M_IST(REG_RESULT, REG_SP, 2 * 4);
826 M_LST(REG_RESULT_PACKED, REG_SP, 2 * 4);
829 M_FSTNP(REG_NULL, REG_SP, 2 * 4);
832 M_DSTNP(REG_NULL, REG_SP, 2 * 4);
836 M_AST_IMM(m, REG_SP, 0 * 4);
837 M_AST(REG_SP, REG_SP, 1 * 4);
838 M_IADD_IMM_MEMBASE(2 * 4, REG_SP, 1 * 4);
839 M_MOV_IMM(trace_java_call_exit, REG_ITMP1);
842 /* restore return value */
844 switch (md->returntype.type) {
847 M_ILD(REG_RESULT, REG_SP, 2 * 4);
850 M_LLD(REG_RESULT_PACKED, REG_SP, 2 * 4);
854 M_AADD_IMM(4 + 4 + 8, REG_SP);
856 /* mark trace code */
860 #endif /* !defined(NDEBUG) */
863 /* code generation functions **************************************************/
865 static void emit_membase(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
867 if (basereg == ESP) {
869 emit_address_byte(0, dreg, ESP);
870 emit_address_byte(0, ESP, ESP);
872 else if (IS_IMM8(disp)) {
873 emit_address_byte(1, dreg, ESP);
874 emit_address_byte(0, ESP, ESP);
878 emit_address_byte(2, dreg, ESP);
879 emit_address_byte(0, ESP, ESP);
883 else if ((disp == 0) && (basereg != EBP)) {
884 emit_address_byte(0, dreg, basereg);
886 else if (IS_IMM8(disp)) {
887 emit_address_byte(1, dreg, basereg);
891 emit_address_byte(2, dreg, basereg);
897 static void emit_membase32(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
899 if (basereg == ESP) {
900 emit_address_byte(2, dreg, ESP);
901 emit_address_byte(0, ESP, ESP);
905 emit_address_byte(2, dreg, basereg);
911 static void emit_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
914 emit_address_byte(0, reg, 4);
915 emit_address_byte(scale, indexreg, 5);
918 else if ((disp == 0) && (basereg != EBP)) {
919 emit_address_byte(0, reg, 4);
920 emit_address_byte(scale, indexreg, basereg);
922 else if (IS_IMM8(disp)) {
923 emit_address_byte(1, reg, 4);
924 emit_address_byte(scale, indexreg, basereg);
928 emit_address_byte(2, reg, 4);
929 emit_address_byte(scale, indexreg, basereg);
935 /* low-level code emitter functions *******************************************/
937 void emit_mov_reg_reg(codegendata *cd, s4 reg, s4 dreg)
939 COUNT(count_mov_reg_reg);
940 *(cd->mcodeptr++) = 0x89;
941 emit_reg((reg),(dreg));
945 void emit_mov_imm_reg(codegendata *cd, s4 imm, s4 reg)
947 *(cd->mcodeptr++) = 0xb8 + ((reg) & 0x07);
951 /* 2-byte opcode for use with patchers */
952 void emit_mov_imm2_reg(codegendata *cd, s4 imm, s4 reg)
954 *(cd->mcodeptr++) = 0xc7;
955 emit_address_byte(3, 0, reg);
961 void emit_movb_imm_reg(codegendata *cd, s4 imm, s4 reg)
963 *(cd->mcodeptr++) = 0xc6;
969 void emit_mov_membase_reg(codegendata *cd, s4 basereg, s4 disp, s4 reg)
971 COUNT(count_mov_mem_reg);
972 *(cd->mcodeptr++) = 0x8b;
973 emit_membase(cd, (basereg),(disp),(reg));
978 * this one is for INVOKEVIRTUAL/INVOKEINTERFACE to have a
979 * constant membase immediate length of 32bit
981 void emit_mov_membase32_reg(codegendata *cd, s4 basereg, s4 disp, s4 reg)
983 COUNT(count_mov_mem_reg);
984 *(cd->mcodeptr++) = 0x8b;
985 emit_membase32(cd, (basereg),(disp),(reg));
989 void emit_mov_reg_membase(codegendata *cd, s4 reg, s4 basereg, s4 disp)
991 COUNT(count_mov_reg_mem);
992 *(cd->mcodeptr++) = 0x89;
993 emit_membase(cd, (basereg),(disp),(reg));
997 void emit_mov_reg_membase32(codegendata *cd, s4 reg, s4 basereg, s4 disp)
999 COUNT(count_mov_reg_mem);
1000 *(cd->mcodeptr++) = 0x89;
1001 emit_membase32(cd, (basereg),(disp),(reg));
1005 void emit_mov_memindex_reg(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg)
1007 COUNT(count_mov_mem_reg);
1008 *(cd->mcodeptr++) = 0x8b;
1009 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1013 void emit_mov_reg_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1015 COUNT(count_mov_reg_mem);
1016 *(cd->mcodeptr++) = 0x89;
1017 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1021 void emit_movw_reg_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1023 COUNT(count_mov_reg_mem);
1024 *(cd->mcodeptr++) = 0x66;
1025 *(cd->mcodeptr++) = 0x89;
1026 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1030 void emit_movb_reg_memindex(codegendata *cd, s4 reg, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1032 COUNT(count_mov_reg_mem);
1033 *(cd->mcodeptr++) = 0x88;
1034 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1038 void emit_mov_reg_mem(codegendata *cd, s4 reg, s4 mem)
1040 COUNT(count_mov_reg_mem);
1041 *(cd->mcodeptr++) = 0x89;
1042 emit_mem((reg),(mem));
1046 void emit_mov_mem_reg(codegendata *cd, s4 mem, s4 dreg)
1048 COUNT(count_mov_mem_reg);
1049 *(cd->mcodeptr++) = 0x8b;
1050 emit_mem((dreg),(mem));
1054 void emit_mov_imm_mem(codegendata *cd, s4 imm, s4 mem)
1056 *(cd->mcodeptr++) = 0xc7;
1062 void emit_mov_imm_membase(codegendata *cd, s4 imm, s4 basereg, s4 disp)
1064 *(cd->mcodeptr++) = 0xc7;
1065 emit_membase(cd, (basereg),(disp),0);
1070 void emit_mov_imm_membase32(codegendata *cd, s4 imm, s4 basereg, s4 disp)
1072 *(cd->mcodeptr++) = 0xc7;
1073 emit_membase32(cd, (basereg),(disp),0);
1078 void emit_movb_imm_membase(codegendata *cd, s4 imm, s4 basereg, s4 disp)
1080 *(cd->mcodeptr++) = 0xc6;
1081 emit_membase(cd, (basereg),(disp),0);
1086 void emit_movsbl_reg_reg(codegendata *cd, s4 a, s4 b)
1088 assert(a < 4); /* Can only operate on al, bl, cl, dl. */
1089 *(cd->mcodeptr++) = 0x0f;
1090 *(cd->mcodeptr++) = 0xbe;
1095 void emit_movsbl_memindex_reg(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg)
1097 COUNT(count_mov_mem_reg);
1098 *(cd->mcodeptr++) = 0x0f;
1099 *(cd->mcodeptr++) = 0xbe;
1100 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1104 void emit_movswl_reg_reg(codegendata *cd, s4 a, s4 b)
1106 *(cd->mcodeptr++) = 0x0f;
1107 *(cd->mcodeptr++) = 0xbf;
1112 void emit_movswl_memindex_reg(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg)
1114 COUNT(count_mov_mem_reg);
1115 *(cd->mcodeptr++) = 0x0f;
1116 *(cd->mcodeptr++) = 0xbf;
1117 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1121 void emit_movzbl_reg_reg(codegendata *cd, s4 a, s4 b)
1123 assert(a < 4); /* Can only operate on al, bl, cl, dl. */
1124 *(cd->mcodeptr++) = 0x0f;
1125 *(cd->mcodeptr++) = 0xb6;
1130 void emit_movzwl_reg_reg(codegendata *cd, s4 a, s4 b)
1132 *(cd->mcodeptr++) = 0x0f;
1133 *(cd->mcodeptr++) = 0xb7;
1138 void emit_movzwl_memindex_reg(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg)
1140 COUNT(count_mov_mem_reg);
1141 *(cd->mcodeptr++) = 0x0f;
1142 *(cd->mcodeptr++) = 0xb7;
1143 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1147 void emit_mov_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1149 *(cd->mcodeptr++) = 0xc7;
1150 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1155 void emit_movw_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1157 *(cd->mcodeptr++) = 0x66;
1158 *(cd->mcodeptr++) = 0xc7;
1159 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1164 void emit_movb_imm_memindex(codegendata *cd, s4 imm, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1166 *(cd->mcodeptr++) = 0xc6;
1167 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1175 void emit_alu_reg_reg(codegendata *cd, s4 opc, s4 reg, s4 dreg)
1177 *(cd->mcodeptr++) = (((u1) (opc)) << 3) + 1;
1178 emit_reg((reg),(dreg));
1182 void emit_alu_reg_membase(codegendata *cd, s4 opc, s4 reg, s4 basereg, s4 disp)
1184 *(cd->mcodeptr++) = (((u1) (opc)) << 3) + 1;
1185 emit_membase(cd, (basereg),(disp),(reg));
1189 void emit_alu_membase_reg(codegendata *cd, s4 opc, s4 basereg, s4 disp, s4 reg)
1191 *(cd->mcodeptr++) = (((u1) (opc)) << 3) + 3;
1192 emit_membase(cd, (basereg),(disp),(reg));
1196 void emit_alu_imm_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1199 *(cd->mcodeptr++) = 0x83;
1200 emit_reg((opc),(dreg));
1203 *(cd->mcodeptr++) = 0x81;
1204 emit_reg((opc),(dreg));
1210 void emit_alu_imm32_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1212 *(cd->mcodeptr++) = 0x81;
1213 emit_reg((opc),(dreg));
1218 void emit_alu_imm_membase(codegendata *cd, s4 opc, s4 imm, s4 basereg, s4 disp)
1221 *(cd->mcodeptr++) = 0x83;
1222 emit_membase(cd, (basereg),(disp),(opc));
1225 *(cd->mcodeptr++) = 0x81;
1226 emit_membase(cd, (basereg),(disp),(opc));
1232 void emit_alu_imm_memabs(codegendata *cd, s4 opc, s4 imm, s4 disp)
1235 *(cd->mcodeptr++) = 0x83;
1236 emit_mem(opc, disp);
1239 *(cd->mcodeptr++) = 0x81;
1240 emit_mem(opc, disp);
1245 void emit_alu_memindex_reg(codegendata *cd, s4 opc, s4 disp, s4 basereg, s4 indexreg, s4 scale, s4 reg)
1247 *(cd->mcodeptr++) = (((u1) (opc)) << 3) + 3;
1248 emit_memindex(cd, (reg),(disp),(basereg),(indexreg),(scale));
1251 void emit_test_reg_reg(codegendata *cd, s4 reg, s4 dreg)
1253 *(cd->mcodeptr++) = 0x85;
1254 emit_reg((reg),(dreg));
1258 void emit_test_imm_reg(codegendata *cd, s4 imm, s4 reg)
1260 *(cd->mcodeptr++) = 0xf7;
1268 * inc, dec operations
1270 void emit_inc_reg(codegendata *cd, s4 reg)
1272 *(cd->mcodeptr++) = 0xff;
1276 void emit_dec_mem(codegendata *cd, s4 mem)
1278 *(cd->mcodeptr++) = 0xff;
1283 void emit_imul_reg_reg(codegendata *cd, s4 reg, s4 dreg)
1285 *(cd->mcodeptr++) = 0x0f;
1286 *(cd->mcodeptr++) = 0xaf;
1287 emit_reg((dreg),(reg));
1291 void emit_imul_membase_reg(codegendata *cd, s4 basereg, s4 disp, s4 dreg)
1293 *(cd->mcodeptr++) = 0x0f;
1294 *(cd->mcodeptr++) = 0xaf;
1295 emit_membase(cd, (basereg),(disp),(dreg));
1299 void emit_imul_imm_reg(codegendata *cd, s4 imm, s4 dreg)
1301 if (IS_IMM8((imm))) {
1302 *(cd->mcodeptr++) = 0x6b;
1306 *(cd->mcodeptr++) = 0x69;
1313 void emit_imul_imm_reg_reg(codegendata *cd, s4 imm, s4 reg, s4 dreg)
1315 if (IS_IMM8((imm))) {
1316 *(cd->mcodeptr++) = 0x6b;
1317 emit_reg((dreg),(reg));
1320 *(cd->mcodeptr++) = 0x69;
1321 emit_reg((dreg),(reg));
1327 void emit_imul_imm_membase_reg(codegendata *cd, s4 imm, s4 basereg, s4 disp, s4 dreg)
1329 if (IS_IMM8((imm))) {
1330 *(cd->mcodeptr++) = 0x6b;
1331 emit_membase(cd, (basereg),(disp),(dreg));
1334 *(cd->mcodeptr++) = 0x69;
1335 emit_membase(cd, (basereg),(disp),(dreg));
1341 void emit_mul_reg(codegendata *cd, s4 reg)
1343 *(cd->mcodeptr++) = 0xf7;
1348 void emit_mul_membase(codegendata *cd, s4 basereg, s4 disp)
1350 *(cd->mcodeptr++) = 0xf7;
1351 emit_membase(cd, (basereg),(disp),4);
1355 void emit_idiv_reg(codegendata *cd, s4 reg)
1357 *(cd->mcodeptr++) = 0xf7;
1366 void emit_shift_reg(codegendata *cd, s4 opc, s4 reg)
1368 *(cd->mcodeptr++) = 0xd3;
1369 emit_reg((opc),(reg));
1373 void emit_shift_imm_reg(codegendata *cd, s4 opc, s4 imm, s4 dreg)
1376 *(cd->mcodeptr++) = 0xd1;
1377 emit_reg((opc),(dreg));
1379 *(cd->mcodeptr++) = 0xc1;
1380 emit_reg((opc),(dreg));
1386 void emit_shld_reg_reg(codegendata *cd, s4 reg, s4 dreg)
1388 *(cd->mcodeptr++) = 0x0f;
1389 *(cd->mcodeptr++) = 0xa5;
1390 emit_reg((reg),(dreg));
1394 void emit_shld_imm_reg_reg(codegendata *cd, s4 imm, s4 reg, s4 dreg)
1396 *(cd->mcodeptr++) = 0x0f;
1397 *(cd->mcodeptr++) = 0xa4;
1398 emit_reg((reg),(dreg));
1403 void emit_shld_reg_membase(codegendata *cd, s4 reg, s4 basereg, s4 disp)
1405 *(cd->mcodeptr++) = 0x0f;
1406 *(cd->mcodeptr++) = 0xa5;
1407 emit_membase(cd, (basereg),(disp),(reg));
1411 void emit_shrd_reg_reg(codegendata *cd, s4 reg, s4 dreg)
1413 *(cd->mcodeptr++) = 0x0f;
1414 *(cd->mcodeptr++) = 0xad;
1415 emit_reg((reg),(dreg));
1419 void emit_shrd_imm_reg_reg(codegendata *cd, s4 imm, s4 reg, s4 dreg)
1421 *(cd->mcodeptr++) = 0x0f;
1422 *(cd->mcodeptr++) = 0xac;
1423 emit_reg((reg),(dreg));
1428 void emit_shrd_reg_membase(codegendata *cd, s4 reg, s4 basereg, s4 disp)
1430 *(cd->mcodeptr++) = 0x0f;
1431 *(cd->mcodeptr++) = 0xad;
1432 emit_membase(cd, (basereg),(disp),(reg));
1440 void emit_jmp_imm(codegendata *cd, s4 imm)
1442 *(cd->mcodeptr++) = 0xe9;
1447 void emit_jmp_reg(codegendata *cd, s4 reg)
1449 *(cd->mcodeptr++) = 0xff;
1454 void emit_jcc(codegendata *cd, s4 opc, s4 imm)
1456 *(cd->mcodeptr++) = 0x0f;
1457 *(cd->mcodeptr++) = 0x80 + (u1) (opc);
1464 * conditional set operations
1466 void emit_setcc_reg(codegendata *cd, s4 opc, s4 reg)
1468 assert(reg < 4); /* Can only operate on al, bl, cl, dl. */
1469 *(cd->mcodeptr++) = 0x0f;
1470 *(cd->mcodeptr++) = 0x90 + (u1) (opc);
1475 void emit_setcc_membase(codegendata *cd, s4 opc, s4 basereg, s4 disp)
1477 *(cd->mcodeptr++) = 0x0f;
1478 *(cd->mcodeptr++) = 0x90 + (u1) (opc);
1479 emit_membase(cd, (basereg),(disp),0);
1483 void emit_xadd_reg_mem(codegendata *cd, s4 reg, s4 mem)
1485 *(cd->mcodeptr++) = 0x0f;
1486 *(cd->mcodeptr++) = 0xc1;
1487 emit_mem((reg),(mem));
1491 void emit_neg_reg(codegendata *cd, s4 reg)
1493 *(cd->mcodeptr++) = 0xf7;
1499 void emit_push_imm(codegendata *cd, s4 imm)
1501 *(cd->mcodeptr++) = 0x68;
1506 void emit_pop_reg(codegendata *cd, s4 reg)
1508 *(cd->mcodeptr++) = 0x58 + (0x07 & (u1) (reg));
1512 void emit_push_reg(codegendata *cd, s4 reg)
1514 *(cd->mcodeptr++) = 0x50 + (0x07 & (u1) (reg));
1518 void emit_lock(codegendata *cd)
1520 *(cd->mcodeptr++) = 0xf0;
1527 void emit_call_reg(codegendata *cd, s4 reg)
1529 *(cd->mcodeptr++) = 0xff;
1534 void emit_call_imm(codegendata *cd, s4 imm)
1536 *(cd->mcodeptr++) = 0xe8;
1543 * floating point instructions
1545 void emit_fld1(codegendata *cd)
1547 *(cd->mcodeptr++) = 0xd9;
1548 *(cd->mcodeptr++) = 0xe8;
1552 void emit_fldz(codegendata *cd)
1554 *(cd->mcodeptr++) = 0xd9;
1555 *(cd->mcodeptr++) = 0xee;
1559 void emit_fld_reg(codegendata *cd, s4 reg)
1561 *(cd->mcodeptr++) = 0xd9;
1562 *(cd->mcodeptr++) = 0xc0 + (0x07 & (u1) (reg));
1566 void emit_flds_membase(codegendata *cd, s4 basereg, s4 disp)
1568 *(cd->mcodeptr++) = 0xd9;
1569 emit_membase(cd, (basereg),(disp),0);
1573 void emit_flds_membase32(codegendata *cd, s4 basereg, s4 disp)
1575 *(cd->mcodeptr++) = 0xd9;
1576 emit_membase32(cd, (basereg),(disp),0);
1580 void emit_fldl_membase(codegendata *cd, s4 basereg, s4 disp)
1582 *(cd->mcodeptr++) = 0xdd;
1583 emit_membase(cd, (basereg),(disp),0);
1587 void emit_fldl_membase32(codegendata *cd, s4 basereg, s4 disp)
1589 *(cd->mcodeptr++) = 0xdd;
1590 emit_membase32(cd, (basereg),(disp),0);
1594 void emit_fldt_membase(codegendata *cd, s4 basereg, s4 disp)
1596 *(cd->mcodeptr++) = 0xdb;
1597 emit_membase(cd, (basereg),(disp),5);
1601 void emit_flds_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1603 *(cd->mcodeptr++) = 0xd9;
1604 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1608 void emit_fldl_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1610 *(cd->mcodeptr++) = 0xdd;
1611 emit_memindex(cd, 0,(disp),(basereg),(indexreg),(scale));
1615 void emit_flds_mem(codegendata *cd, s4 mem)
1617 *(cd->mcodeptr++) = 0xd9;
1622 void emit_fldl_mem(codegendata *cd, s4 mem)
1624 *(cd->mcodeptr++) = 0xdd;
1629 void emit_fildl_membase(codegendata *cd, s4 basereg, s4 disp)
1631 *(cd->mcodeptr++) = 0xdb;
1632 emit_membase(cd, (basereg),(disp),0);
1636 void emit_fildll_membase(codegendata *cd, s4 basereg, s4 disp)
1638 *(cd->mcodeptr++) = 0xdf;
1639 emit_membase(cd, (basereg),(disp),5);
1643 void emit_fst_reg(codegendata *cd, s4 reg)
1645 *(cd->mcodeptr++) = 0xdd;
1646 *(cd->mcodeptr++) = 0xd0 + (0x07 & (u1) (reg));
1650 void emit_fsts_membase(codegendata *cd, s4 basereg, s4 disp)
1652 *(cd->mcodeptr++) = 0xd9;
1653 emit_membase(cd, (basereg),(disp),2);
1657 void emit_fstl_membase(codegendata *cd, s4 basereg, s4 disp)
1659 *(cd->mcodeptr++) = 0xdd;
1660 emit_membase(cd, (basereg),(disp),2);
1664 void emit_fsts_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1666 *(cd->mcodeptr++) = 0xd9;
1667 emit_memindex(cd, 2,(disp),(basereg),(indexreg),(scale));
1671 void emit_fstl_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1673 *(cd->mcodeptr++) = 0xdd;
1674 emit_memindex(cd, 2,(disp),(basereg),(indexreg),(scale));
1678 void emit_fstp_reg(codegendata *cd, s4 reg)
1680 *(cd->mcodeptr++) = 0xdd;
1681 *(cd->mcodeptr++) = 0xd8 + (0x07 & (u1) (reg));
1685 void emit_fstps_membase(codegendata *cd, s4 basereg, s4 disp)
1687 *(cd->mcodeptr++) = 0xd9;
1688 emit_membase(cd, (basereg),(disp),3);
1692 void emit_fstps_membase32(codegendata *cd, s4 basereg, s4 disp)
1694 *(cd->mcodeptr++) = 0xd9;
1695 emit_membase32(cd, (basereg),(disp),3);
1699 void emit_fstpl_membase(codegendata *cd, s4 basereg, s4 disp)
1701 *(cd->mcodeptr++) = 0xdd;
1702 emit_membase(cd, (basereg),(disp),3);
1706 void emit_fstpl_membase32(codegendata *cd, s4 basereg, s4 disp)
1708 *(cd->mcodeptr++) = 0xdd;
1709 emit_membase32(cd, (basereg),(disp),3);
1713 void emit_fstpt_membase(codegendata *cd, s4 basereg, s4 disp)
1715 *(cd->mcodeptr++) = 0xdb;
1716 emit_membase(cd, (basereg),(disp),7);
1720 void emit_fstps_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1722 *(cd->mcodeptr++) = 0xd9;
1723 emit_memindex(cd, 3,(disp),(basereg),(indexreg),(scale));
1727 void emit_fstpl_memindex(codegendata *cd, s4 disp, s4 basereg, s4 indexreg, s4 scale)
1729 *(cd->mcodeptr++) = 0xdd;
1730 emit_memindex(cd, 3,(disp),(basereg),(indexreg),(scale));
1734 void emit_fstps_mem(codegendata *cd, s4 mem)
1736 *(cd->mcodeptr++) = 0xd9;
1741 void emit_fstpl_mem(codegendata *cd, s4 mem)
1743 *(cd->mcodeptr++) = 0xdd;
1748 void emit_fistl_membase(codegendata *cd, s4 basereg, s4 disp)
1750 *(cd->mcodeptr++) = 0xdb;
1751 emit_membase(cd, (basereg),(disp),2);
1755 void emit_fistpl_membase(codegendata *cd, s4 basereg, s4 disp)
1757 *(cd->mcodeptr++) = 0xdb;
1758 emit_membase(cd, (basereg),(disp),3);
1762 void emit_fistpll_membase(codegendata *cd, s4 basereg, s4 disp)
1764 *(cd->mcodeptr++) = 0xdf;
1765 emit_membase(cd, (basereg),(disp),7);
1769 void emit_fchs(codegendata *cd)
1771 *(cd->mcodeptr++) = 0xd9;
1772 *(cd->mcodeptr++) = 0xe0;
1776 void emit_faddp(codegendata *cd)
1778 *(cd->mcodeptr++) = 0xde;
1779 *(cd->mcodeptr++) = 0xc1;
1783 void emit_fadd_reg_st(codegendata *cd, s4 reg)
1785 *(cd->mcodeptr++) = 0xd8;
1786 *(cd->mcodeptr++) = 0xc0 + (0x0f & (u1) (reg));
1790 void emit_fadd_st_reg(codegendata *cd, s4 reg)
1792 *(cd->mcodeptr++) = 0xdc;
1793 *(cd->mcodeptr++) = 0xc0 + (0x0f & (u1) (reg));
1797 void emit_faddp_st_reg(codegendata *cd, s4 reg)
1799 *(cd->mcodeptr++) = 0xde;
1800 *(cd->mcodeptr++) = 0xc0 + (0x0f & (u1) (reg));
1804 void emit_fadds_membase(codegendata *cd, s4 basereg, s4 disp)
1806 *(cd->mcodeptr++) = 0xd8;
1807 emit_membase(cd, (basereg),(disp),0);
1811 void emit_faddl_membase(codegendata *cd, s4 basereg, s4 disp)
1813 *(cd->mcodeptr++) = 0xdc;
1814 emit_membase(cd, (basereg),(disp),0);
1818 void emit_fsub_reg_st(codegendata *cd, s4 reg)
1820 *(cd->mcodeptr++) = 0xd8;
1821 *(cd->mcodeptr++) = 0xe0 + (0x07 & (u1) (reg));
1825 void emit_fsub_st_reg(codegendata *cd, s4 reg)
1827 *(cd->mcodeptr++) = 0xdc;
1828 *(cd->mcodeptr++) = 0xe8 + (0x07 & (u1) (reg));
1832 void emit_fsubp_st_reg(codegendata *cd, s4 reg)
1834 *(cd->mcodeptr++) = 0xde;
1835 *(cd->mcodeptr++) = 0xe8 + (0x07 & (u1) (reg));
1839 void emit_fsubp(codegendata *cd)
1841 *(cd->mcodeptr++) = 0xde;
1842 *(cd->mcodeptr++) = 0xe9;
1846 void emit_fsubs_membase(codegendata *cd, s4 basereg, s4 disp)
1848 *(cd->mcodeptr++) = 0xd8;
1849 emit_membase(cd, (basereg),(disp),4);
1853 void emit_fsubl_membase(codegendata *cd, s4 basereg, s4 disp)
1855 *(cd->mcodeptr++) = 0xdc;
1856 emit_membase(cd, (basereg),(disp),4);
1860 void emit_fmul_reg_st(codegendata *cd, s4 reg)
1862 *(cd->mcodeptr++) = 0xd8;
1863 *(cd->mcodeptr++) = 0xc8 + (0x07 & (u1) (reg));
1867 void emit_fmul_st_reg(codegendata *cd, s4 reg)
1869 *(cd->mcodeptr++) = 0xdc;
1870 *(cd->mcodeptr++) = 0xc8 + (0x07 & (u1) (reg));
1874 void emit_fmulp(codegendata *cd)
1876 *(cd->mcodeptr++) = 0xde;
1877 *(cd->mcodeptr++) = 0xc9;
1881 void emit_fmulp_st_reg(codegendata *cd, s4 reg)
1883 *(cd->mcodeptr++) = 0xde;
1884 *(cd->mcodeptr++) = 0xc8 + (0x07 & (u1) (reg));
1888 void emit_fmuls_membase(codegendata *cd, s4 basereg, s4 disp)
1890 *(cd->mcodeptr++) = 0xd8;
1891 emit_membase(cd, (basereg),(disp),1);
1895 void emit_fmull_membase(codegendata *cd, s4 basereg, s4 disp)
1897 *(cd->mcodeptr++) = 0xdc;
1898 emit_membase(cd, (basereg),(disp),1);
1902 void emit_fdiv_reg_st(codegendata *cd, s4 reg)
1904 *(cd->mcodeptr++) = 0xd8;
1905 *(cd->mcodeptr++) = 0xf0 + (0x07 & (u1) (reg));
1909 void emit_fdiv_st_reg(codegendata *cd, s4 reg)
1911 *(cd->mcodeptr++) = 0xdc;
1912 *(cd->mcodeptr++) = 0xf8 + (0x07 & (u1) (reg));
1916 void emit_fdivp(codegendata *cd)
1918 *(cd->mcodeptr++) = 0xde;
1919 *(cd->mcodeptr++) = 0xf9;
1923 void emit_fdivp_st_reg(codegendata *cd, s4 reg)
1925 *(cd->mcodeptr++) = 0xde;
1926 *(cd->mcodeptr++) = 0xf8 + (0x07 & (u1) (reg));
1930 void emit_fxch(codegendata *cd)
1932 *(cd->mcodeptr++) = 0xd9;
1933 *(cd->mcodeptr++) = 0xc9;
1937 void emit_fxch_reg(codegendata *cd, s4 reg)
1939 *(cd->mcodeptr++) = 0xd9;
1940 *(cd->mcodeptr++) = 0xc8 + (0x07 & (reg));
1944 void emit_fprem(codegendata *cd)
1946 *(cd->mcodeptr++) = 0xd9;
1947 *(cd->mcodeptr++) = 0xf8;
1951 void emit_fprem1(codegendata *cd)
1953 *(cd->mcodeptr++) = 0xd9;
1954 *(cd->mcodeptr++) = 0xf5;
1958 void emit_fucom(codegendata *cd)
1960 *(cd->mcodeptr++) = 0xdd;
1961 *(cd->mcodeptr++) = 0xe1;
1965 void emit_fucom_reg(codegendata *cd, s4 reg)
1967 *(cd->mcodeptr++) = 0xdd;
1968 *(cd->mcodeptr++) = 0xe0 + (0x07 & (u1) (reg));
1972 void emit_fucomp_reg(codegendata *cd, s4 reg)
1974 *(cd->mcodeptr++) = 0xdd;
1975 *(cd->mcodeptr++) = 0xe8 + (0x07 & (u1) (reg));
1979 void emit_fucompp(codegendata *cd)
1981 *(cd->mcodeptr++) = 0xda;
1982 *(cd->mcodeptr++) = 0xe9;
1986 void emit_fnstsw(codegendata *cd)
1988 *(cd->mcodeptr++) = 0xdf;
1989 *(cd->mcodeptr++) = 0xe0;
1993 void emit_sahf(codegendata *cd)
1995 *(cd->mcodeptr++) = 0x9e;
1999 void emit_finit(codegendata *cd)
2001 *(cd->mcodeptr++) = 0x9b;
2002 *(cd->mcodeptr++) = 0xdb;
2003 *(cd->mcodeptr++) = 0xe3;
2007 void emit_fldcw_mem(codegendata *cd, s4 mem)
2009 *(cd->mcodeptr++) = 0xd9;
2014 void emit_fldcw_membase(codegendata *cd, s4 basereg, s4 disp)
2016 *(cd->mcodeptr++) = 0xd9;
2017 emit_membase(cd, (basereg),(disp),5);
2021 void emit_wait(codegendata *cd)
2023 *(cd->mcodeptr++) = 0x9b;
2027 void emit_ffree_reg(codegendata *cd, s4 reg)
2029 *(cd->mcodeptr++) = 0xdd;
2030 *(cd->mcodeptr++) = 0xc0 + (0x07 & (u1) (reg));
2034 void emit_fdecstp(codegendata *cd)
2036 *(cd->mcodeptr++) = 0xd9;
2037 *(cd->mcodeptr++) = 0xf6;
2041 void emit_fincstp(codegendata *cd)
2043 *(cd->mcodeptr++) = 0xd9;
2044 *(cd->mcodeptr++) = 0xf7;
2047 #if defined(ENABLE_ESCAPE_CHECK)
2048 void emit_escape_check(codegendata *cd, s4 reg) {
2050 M_MOV_IMM(asm_escape_check, REG_ITMP3);
2052 M_IADD_IMM(4, REG_SP);
2057 * These are local overrides for various environment variables in Emacs.
2058 * Please do not remove this and leave it at the end of the file, where
2059 * Emacs will automagically detect them.
2060 * ---------------------------------------------------------------------
2063 * indent-tabs-mode: t