1 /* src/vm/jit/i386/codegen.h - code generation macros and definitions for i386
3 Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 Contact: cacao@cacaojvm.org
27 Authors: Andreas Krall
32 $Id: codegen.h 4616 2006-03-15 17:17:35Z twisti $
43 #include "vm/jit/jit.h"
46 #if defined(ENABLE_LSRA)
47 /* let LSRA allocate reserved registers (REG_ITMP[1|2|3]) */
48 # define LSRA_USES_REG_RES
51 /* some defines ***************************************************************/
53 #define PATCHER_CALL_SIZE 5 /* size in bytes of a patcher call */
56 /* additional functions and macros to generate code ***************************/
58 #define CALCOFFSETBYTES(var, reg, val) \
59 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
60 else if ((s4) (val) != 0) (var) += 1; \
61 else if ((reg) == EBP) (var) += 1;
64 #define CALCIMMEDIATEBYTES(var, val) \
65 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
69 /* gen_nullptr_check(objreg) */
71 #define gen_nullptr_check(objreg) \
75 codegen_add_nullpointerexception_ref(cd, cd->mcodeptr); \
78 #define gen_bound_check \
80 M_CMP_MEMBASE(s1, OFFSET(java_arrayheader, size), s2); \
82 codegen_add_arrayindexoutofboundsexception_ref(cd, cd->mcodeptr, s2); \
85 #define gen_div_check(v) \
87 if ((v)->flags & INMEMORY) \
88 M_CMP_IMM_MEMBASE(0, REG_SP, src->regoff * 4); \
90 M_TEST(src->regoff); \
92 codegen_add_arithmeticexception_ref(cd, cd->mcodeptr); \
96 /* MCODECHECK(icnt) */
98 #define MCODECHECK(icnt) \
99 if ((cd->mcodeptr + (icnt)) > (u1 *) cd->mcodeend) \
100 cd->mcodeptr = (u1 *) codegen_increase(cd, cd->mcodeptr)
104 generates an integer-move from register a to b.
105 if a and b are the same int-register, no code will be generated.
108 #define M_INTMOVE(reg,dreg) \
109 if ((reg) != (dreg)) { \
110 i386_mov_reg_reg(cd, (reg),(dreg)); \
115 generates a floating-point-move from register a to b.
116 if a and b are the same float-register, no code will be generated
119 #define M_FLTMOVE(reg,dreg) \
121 log_text("M_FLTMOVE"); \
126 #define M_LNGMEMMOVE(reg,dreg) \
128 i386_mov_membase_reg(cd, REG_SP, (reg) * 4, REG_ITMP1); \
129 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, (dreg) * 4); \
130 i386_mov_membase_reg(cd, REG_SP, (reg) * 4 + 4, REG_ITMP1); \
131 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, (dreg) * 4 + 4); \
136 this function generates code to fetch data from a pseudo-register
137 into a real register.
138 If the pseudo-register has actually been assigned to a real
139 register, no code will be emitted, since following operations
140 can use this register directly.
142 v: pseudoregister to be fetched from
143 tempregnum: temporary register to be used if v is actually spilled to ram
145 return: the register number, where the operand can be found after
146 fetching (this wil be either tempregnum or the register
147 number allready given to v)
150 #define var_to_reg_int(regnr,v,tempnr) \
152 if ((v)->flags & INMEMORY) { \
154 M_ILD(tempnr, REG_SP, (v)->regoff * 4); \
157 regnr = (v)->regoff; \
161 #define var_to_reg_lng(regnr,v,tempnr) \
163 if ((v)->flags & INMEMORY) { \
165 M_LLD(tempnr, REG_SP, (v)->regoff * 4); \
168 regnr = (v)->regoff; \
172 #define var_to_reg_flt(regnr,v,tempnr) \
173 if ((v)->type == TYPE_FLT) { \
174 if ((v)->flags & INMEMORY) { \
176 i386_flds_membase(cd, REG_SP, (v)->regoff * 4); \
180 i386_fld_reg(cd, (v)->regoff + fpu_st_offset); \
182 regnr = (v)->regoff; \
185 if ((v)->flags & INMEMORY) { \
187 i386_fldl_membase(cd, REG_SP, (v)->regoff * 4); \
191 i386_fld_reg(cd, (v)->regoff + fpu_st_offset); \
193 regnr = (v)->regoff; \
197 #define NEW_var_to_reg_flt(regnr,v,tempnr) \
198 if ((v)->type == TYPE_FLT) { \
199 if ((v)->flags & INMEMORY) { \
201 i386_flds_membase(cd, REG_SP, (v)->regoff * 4); \
205 regnr = (v)->regoff; \
208 if ((v)->flags & INMEMORY) { \
210 i386_fldl_membase(cd, REG_SP, (v)->regoff * 4); \
214 regnr = (v)->regoff; \
219 /* store_reg_to_var_xxx:
220 This function generates the code to store the result of an operation
221 back into a spilled pseudo-variable.
222 If the pseudo-variable has not been spilled in the first place, this
223 function will generate nothing.
225 v ............ Pseudovariable
226 tempregnum ... Number of the temporary registers as returned by
230 #define store_reg_to_var_int(sptr, tempregnum) \
231 if ((sptr)->flags & INMEMORY) { \
233 M_IST(tempregnum, REG_SP, (sptr)->regoff * 4); \
237 #define store_reg_to_var_lng(sptr, tempregnum) \
238 if ((sptr)->flags & INMEMORY) { \
240 M_LST(tempregnum, REG_SP, (sptr)->regoff * 4); \
244 #define store_reg_to_var_flt(sptr, tempregnum) \
245 if ((sptr)->type == TYPE_FLT) { \
246 if ((sptr)->flags & INMEMORY) { \
248 i386_fstps_membase(cd, REG_SP, (sptr)->regoff * 4); \
251 /* i386_fxch_reg((sptr)->regoff);*/ \
252 i386_fstp_reg(cd, (sptr)->regoff + fpu_st_offset); \
256 if ((sptr)->flags & INMEMORY) { \
258 i386_fstpl_membase(cd, REG_SP, (sptr)->regoff * 4); \
261 /* i386_fxch_reg((sptr)->regoff);*/ \
262 i386_fstp_reg(cd, (sptr)->regoff + fpu_st_offset); \
268 #define M_COPY(from,to) \
269 d = reg_of_var(rd, to, REG_ITMP1); \
270 if ((from->regoff != to->regoff) || \
271 ((from->flags ^ to->flags) & INMEMORY)) { \
272 if (IS_FLT_DBL_TYPE(from->type)) { \
273 var_to_reg_flt(s1, from, d); \
274 /*M_FLTMOVE(s1, d);*/ \
275 store_reg_to_var_flt(to, d); \
277 if (!IS_2_WORD_TYPE(from->type)) { \
278 if (to->flags & INMEMORY) { \
279 if (from->flags & INMEMORY) { \
280 i386_mov_membase_reg(cd, REG_SP, from->regoff * 4, REG_ITMP1); \
281 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, to->regoff * 4); \
283 i386_mov_reg_membase(cd, from->regoff, REG_SP, to->regoff * 4); \
286 if (from->flags & INMEMORY) { \
287 i386_mov_membase_reg(cd, REG_SP, from->regoff * 4, to->regoff); \
289 i386_mov_reg_reg(cd, from->regoff, to->regoff); \
293 M_LNGMEMMOVE(from->regoff, to->regoff); \
298 /* macros to create code ******************************************************/
313 /* opcodes for alu instructions */
341 I386_CC_B = 2, I386_CC_C = 2, I386_CC_NAE = 2,
342 I386_CC_BE = 6, I386_CC_NA = 6,
343 I386_CC_AE = 3, I386_CC_NB = 3, I386_CC_NC = 3,
344 I386_CC_E = 4, I386_CC_Z = 4,
345 I386_CC_NE = 5, I386_CC_NZ = 5,
346 I386_CC_A = 7, I386_CC_NBE = 7,
347 I386_CC_S = 8, I386_CC_LZ = 8,
348 I386_CC_NS = 9, I386_CC_GEZ = 9,
349 I386_CC_P = 0x0a, I386_CC_PE = 0x0a,
350 I386_CC_NP = 0x0b, I386_CC_PO = 0x0b,
351 I386_CC_L = 0x0c, I386_CC_NGE = 0x0c,
352 I386_CC_GE = 0x0d, I386_CC_NL = 0x0d,
353 I386_CC_LE = 0x0e, I386_CC_NG = 0x0e,
354 I386_CC_G = 0x0f, I386_CC_NLE = 0x0f,
359 /* modrm and stuff */
361 #define i386_address_byte(mod,reg,rm) \
362 *(cd->mcodeptr++) = ((((mod) & 0x03) << 6) | (((reg) & 0x07) << 3) | (((rm) & 0x07)));
365 #define i386_emit_reg(reg,rm) \
366 i386_address_byte(3,(reg),(rm));
369 #define i386_is_imm8(imm) \
370 (((int)(imm) >= -128 && (int)(imm) <= 127))
373 #define i386_emit_imm8(imm) \
374 *(cd->mcodeptr++) = (u1) ((imm) & 0xff);
377 #define i386_emit_imm16(imm) \
380 imb.i = (int) (imm); \
381 *(cd->mcodeptr++) = imb.b[0]; \
382 *(cd->mcodeptr++) = imb.b[1]; \
386 #define i386_emit_imm32(imm) \
389 imb.i = (int) (imm); \
390 *(cd->mcodeptr++) = imb.b[0]; \
391 *(cd->mcodeptr++) = imb.b[1]; \
392 *(cd->mcodeptr++) = imb.b[2]; \
393 *(cd->mcodeptr++) = imb.b[3]; \
397 #define i386_emit_mem(r,mem) \
399 i386_address_byte(0,(r),5); \
400 i386_emit_imm32((mem)); \
404 #define i386_emit_membase(basereg,disp,dreg) \
406 if ((basereg) == ESP) { \
408 i386_address_byte(0, (dreg), ESP); \
409 i386_address_byte(0, ESP, ESP); \
410 } else if (i386_is_imm8((disp))) { \
411 i386_address_byte(1, (dreg), ESP); \
412 i386_address_byte(0, ESP, ESP); \
413 i386_emit_imm8((disp)); \
415 i386_address_byte(2, (dreg), ESP); \
416 i386_address_byte(0, ESP, ESP); \
417 i386_emit_imm32((disp)); \
422 if ((disp) == 0 && (basereg) != EBP) { \
423 i386_address_byte(0, (dreg), (basereg)); \
427 if (i386_is_imm8((disp))) { \
428 i386_address_byte(1, (dreg), (basereg)); \
429 i386_emit_imm8((disp)); \
431 i386_address_byte(2, (dreg), (basereg)); \
432 i386_emit_imm32((disp)); \
437 #define i386_emit_membase32(basereg,disp,dreg) \
439 if ((basereg) == ESP) { \
440 i386_address_byte(2, (dreg), ESP); \
441 i386_address_byte(0, ESP, ESP); \
442 i386_emit_imm32((disp)); \
444 i386_address_byte(2, (dreg), (basereg)); \
445 i386_emit_imm32((disp)); \
450 #define i386_emit_memindex(reg,disp,basereg,indexreg,scale) \
452 if ((basereg) == -1) { \
453 i386_address_byte(0, (reg), 4); \
454 i386_address_byte((scale), (indexreg), 5); \
455 i386_emit_imm32((disp)); \
457 } else if ((disp) == 0 && (basereg) != EBP) { \
458 i386_address_byte(0, (reg), 4); \
459 i386_address_byte((scale), (indexreg), (basereg)); \
461 } else if (i386_is_imm8((disp))) { \
462 i386_address_byte(1, (reg), 4); \
463 i386_address_byte((scale), (indexreg), (basereg)); \
464 i386_emit_imm8 ((disp)); \
467 i386_address_byte(2, (reg), 4); \
468 i386_address_byte((scale), (indexreg), (basereg)); \
469 i386_emit_imm32((disp)); \
474 /* macros to create code ******************************************************/
476 #define M_ILD(a,b,disp) i386_mov_membase_reg(cd, (b), (disp), (a))
477 #define M_ALD(a,b,disp) M_ILD(a,b,disp)
479 #define M_ILD32(a,b,disp) i386_mov_membase32_reg(cd, (b), (disp), (a))
481 #define M_LLD(a,b,disp) \
483 M_ILD(GET_LOW_REG(a),b,disp); \
484 M_ILD(GET_HIGH_REG(a),b,disp + 4); \
487 #define M_LLD32(a,b,disp) \
489 M_ILD32(GET_LOW_REG(a),b,disp); \
490 M_ILD32(GET_HIGH_REG(a),b,disp + 4); \
493 #define M_IST(a,b,disp) i386_mov_reg_membase(cd, (a), (b), (disp))
494 #define M_IST_IMM(a,b,disp) i386_mov_imm_membase(cd, (u4) (a), (b), (disp))
495 #define M_AST(a,b,disp) M_IST(a,b,disp)
496 #define M_AST_IMM(a,b,disp) M_IST_IMM(a,b,disp)
498 #define M_IST32(a,b,disp) i386_mov_reg_membase32(cd, (a), (b), (disp))
499 #define M_IST32_IMM(a,b,disp) i386_mov_imm_membase32(cd, (u4) (a), (b), (disp))
501 #define M_LST(a,b,disp) \
503 M_IST(GET_LOW_REG(a),b,disp); \
504 M_IST(GET_HIGH_REG(a),b,disp + 4); \
507 #define M_LST32(a,b,disp) \
509 M_IST32(GET_LOW_REG(a),b,disp); \
510 M_IST32(GET_HIGH_REG(a),b,disp + 4); \
513 #define M_LST_IMM(a,b,disp) \
515 M_IST_IMM(a,b,disp); \
516 M_IST_IMM(a >> 32,b,disp + 4); \
519 #define M_LST32_IMM(a,b,disp) \
521 M_IST32_IMM(a,b,disp); \
522 M_IST32_IMM(a >> 32,b,disp + 4); \
525 #define M_IADD_IMM(a,b) i386_alu_imm_reg(cd, ALU_ADD, (a), (b))
526 #define M_IADD_IMM32(a,b) i386_alu_imm32_reg(cd, ALU_ADD, (a), (b))
527 #define M_ISUB_IMM(a,b) i386_alu_imm_reg(cd, ALU_SUB, (a), (b))
529 #define M_IADD_IMM_MEMBASE(a,b,c) i386_alu_imm_membase(cd, ALU_ADD, (a), (b), (c))
531 #define M_AADD_IMM(a,b) M_IADD_IMM(a,b)
532 #define M_AADD_IMM32(a,b) M_IADD_IMM32(a,b)
533 #define M_ASUB_IMM(a,b) M_ISUB_IMM(a,b)
535 #define M_OR_MEMBASE(a,b,c) i386_alu_membase_reg(cd, ALU_OR, (a), (b), (c))
536 #define M_XOR(a,b) i386_alu_reg_reg(cd, ALU_XOR, (a), (b))
537 #define M_CLR(a) M_XOR(a,a)
539 #define M_PUSH(a) i386_push_reg(cd, (a))
540 #define M_PUSH_IMM(a) i386_push_imm(cd, (s4) (a))
541 #define M_POP(a) i386_pop_reg(cd, (a))
543 #define M_MOV(a,b) i386_mov_reg_reg(cd, (a), (b))
544 #define M_MOV_IMM(a,b) i386_mov_imm_reg(cd, (u4) (a), (b))
546 #define M_TEST(a) i386_test_reg_reg(cd, (a), (a))
548 #define M_CMP(a,b) i386_alu_reg_reg(cd, ALU_CMP, (a), (b))
549 #define M_CMP_MEMBASE(a,b,c) i386_alu_membase_reg(cd, ALU_CMP, (a), (b), (c))
551 #define M_CMP_IMM_MEMBASE(a,b,c) i386_alu_imm_membase(cd, ALU_CMP, (a), (b), (c))
553 #define M_CALL(a) i386_call_reg(cd, (a))
554 #define M_CALL_IMM(a) i386_call_imm(cd, (a))
555 #define M_RET i386_ret(cd)
557 #define M_BEQ(a) i386_jcc(cd, I386_CC_E, (a))
558 #define M_BNE(a) i386_jcc(cd, I386_CC_NE, (a))
559 #define M_BLT(a) i386_jcc(cd, I386_CC_L, (a))
560 #define M_BLE(a) i386_jcc(cd, I386_CC_LE, (a))
561 #define M_BGE(a) i386_jcc(cd, I386_CC_GE, (a))
562 #define M_BGT(a) i386_jcc(cd, I386_CC_G, (a))
564 #define M_BBE(a) i386_jcc(cd, I386_CC_BE, (a))
565 #define M_BAE(a) i386_jcc(cd, I386_CC_AE, (a))
567 #define M_JMP(a) i386_jmp_reg(cd, (a))
568 #define M_JMP_IMM(a) i386_jmp_imm(cd, (a))
570 #define M_NOP i386_nop(cd)
573 /* function gen_resolvebranch **************************************************
575 backpatches a branch instruction
577 parameters: ip ... pointer to instruction after branch (void*)
578 so ... offset of instruction after branch (s4)
579 to ... offset of branch target (s4)
581 *******************************************************************************/
583 #define gen_resolvebranch(ip,so,to) \
584 *((void **) ((ip) - 4)) = (void **) ((to) - (so));
587 #endif /* _CODEGEN_H */
591 * These are local overrides for various environment variables in Emacs.
592 * Please do not remove this and leave it at the end of the file, where
593 * Emacs will automagically detect them.
594 * ---------------------------------------------------------------------
597 * indent-tabs-mode: t