1 /* src/vm/jit/i386/codegen.h - code generation macros and definitions for i386
3 Copyright (C) 1996-2005, 2006 R. Grafl, A. Krall, C. Kruegel,
4 C. Oates, R. Obermaisser, M. Platter, M. Probst, S. Ring,
5 E. Steiner, C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich,
6 J. Wenninger, Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25 Contact: cacao@cacaojvm.org
27 Authors: Andreas Krall
32 $Id: codegen.h 4611 2006-03-15 11:18:30Z twisti $
43 #include "vm/jit/jit.h"
46 #if defined(ENABLE_LSRA)
47 /* let LSRA allocate reserved registers (REG_ITMP[1|2|3]) */
48 # define LSRA_USES_REG_RES
51 /* some defines ***************************************************************/
53 #define PATCHER_CALL_SIZE 5 /* size in bytes of a patcher call */
56 /* additional functions and macros to generate code ***************************/
58 #define CALCOFFSETBYTES(var, reg, val) \
59 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
60 else if ((s4) (val) != 0) (var) += 1; \
61 else if ((reg) == EBP) (var) += 1;
64 #define CALCIMMEDIATEBYTES(var, val) \
65 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
69 /* gen_nullptr_check(objreg) */
71 #define gen_nullptr_check(objreg) \
73 i386_test_reg_reg(cd, (objreg), (objreg)); \
74 i386_jcc(cd, I386_CC_E, 0); \
75 codegen_addxnullrefs(cd, cd->mcodeptr); \
78 #define gen_bound_check \
80 i386_alu_membase_reg(cd, ALU_CMP, s1, OFFSET(java_arrayheader, size), s2); \
81 i386_jcc(cd, I386_CC_AE, 0); \
82 codegen_addxboundrefs(cd, cd->mcodeptr, s2); \
85 #define gen_div_check(v) \
87 if ((v)->flags & INMEMORY) { \
88 i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4); \
90 i386_test_reg_reg(cd, src->regoff, src->regoff); \
92 i386_jcc(cd, I386_CC_E, 0); \
93 codegen_addxdivrefs(cd, cd->mcodeptr); \
97 /* MCODECHECK(icnt) */
99 #define MCODECHECK(icnt) \
100 if ((cd->mcodeptr + (icnt)) > (u1 *) cd->mcodeend) \
101 cd->mcodeptr = (u1 *) codegen_increase(cd, cd->mcodeptr)
105 generates an integer-move from register a to b.
106 if a and b are the same int-register, no code will be generated.
109 #define M_INTMOVE(reg,dreg) \
110 if ((reg) != (dreg)) { \
111 i386_mov_reg_reg(cd, (reg),(dreg)); \
116 generates a floating-point-move from register a to b.
117 if a and b are the same float-register, no code will be generated
120 #define M_FLTMOVE(reg,dreg) \
122 log_text("M_FLTMOVE"); \
127 #define M_LNGMEMMOVE(reg,dreg) \
129 i386_mov_membase_reg(cd, REG_SP, (reg) * 4, REG_ITMP1); \
130 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, (dreg) * 4); \
131 i386_mov_membase_reg(cd, REG_SP, (reg) * 4 + 4, REG_ITMP1); \
132 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, (dreg) * 4 + 4); \
137 this function generates code to fetch data from a pseudo-register
138 into a real register.
139 If the pseudo-register has actually been assigned to a real
140 register, no code will be emitted, since following operations
141 can use this register directly.
143 v: pseudoregister to be fetched from
144 tempregnum: temporary register to be used if v is actually spilled to ram
146 return: the register number, where the operand can be found after
147 fetching (this wil be either tempregnum or the register
148 number allready given to v)
151 #define var_to_reg_int(regnr,v,tempnr) \
153 if ((v)->flags & INMEMORY) { \
155 M_ILD(tempnr, REG_SP, (v)->regoff * 4); \
158 regnr = (v)->regoff; \
162 #define var_to_reg_lng(regnr,v,tempnr) \
164 if ((v)->flags & INMEMORY) { \
166 M_LLD(tempnr, REG_SP, (v)->regoff * 4); \
169 regnr = (v)->regoff; \
173 #define var_to_reg_flt(regnr,v,tempnr) \
174 if ((v)->type == TYPE_FLT) { \
175 if ((v)->flags & INMEMORY) { \
177 i386_flds_membase(cd, REG_SP, (v)->regoff * 4); \
181 i386_fld_reg(cd, (v)->regoff + fpu_st_offset); \
183 regnr = (v)->regoff; \
186 if ((v)->flags & INMEMORY) { \
188 i386_fldl_membase(cd, REG_SP, (v)->regoff * 4); \
192 i386_fld_reg(cd, (v)->regoff + fpu_st_offset); \
194 regnr = (v)->regoff; \
198 #define NEW_var_to_reg_flt(regnr,v,tempnr) \
199 if ((v)->type == TYPE_FLT) { \
200 if ((v)->flags & INMEMORY) { \
202 i386_flds_membase(cd, REG_SP, (v)->regoff * 4); \
206 regnr = (v)->regoff; \
209 if ((v)->flags & INMEMORY) { \
211 i386_fldl_membase(cd, REG_SP, (v)->regoff * 4); \
215 regnr = (v)->regoff; \
220 /* store_reg_to_var_xxx:
221 This function generates the code to store the result of an operation
222 back into a spilled pseudo-variable.
223 If the pseudo-variable has not been spilled in the first place, this
224 function will generate nothing.
226 v ............ Pseudovariable
227 tempregnum ... Number of the temporary registers as returned by
231 #define store_reg_to_var_int(sptr, tempregnum) \
232 if ((sptr)->flags & INMEMORY) { \
234 M_IST(tempregnum, REG_SP, (sptr)->regoff * 4); \
238 #define store_reg_to_var_lng(sptr, tempregnum) \
239 if ((sptr)->flags & INMEMORY) { \
241 M_LST(tempregnum, REG_SP, (sptr)->regoff * 4); \
245 #define store_reg_to_var_flt(sptr, tempregnum) \
246 if ((sptr)->type == TYPE_FLT) { \
247 if ((sptr)->flags & INMEMORY) { \
249 i386_fstps_membase(cd, REG_SP, (sptr)->regoff * 4); \
252 /* i386_fxch_reg((sptr)->regoff);*/ \
253 i386_fstp_reg(cd, (sptr)->regoff + fpu_st_offset); \
257 if ((sptr)->flags & INMEMORY) { \
259 i386_fstpl_membase(cd, REG_SP, (sptr)->regoff * 4); \
262 /* i386_fxch_reg((sptr)->regoff);*/ \
263 i386_fstp_reg(cd, (sptr)->regoff + fpu_st_offset); \
269 #define M_COPY(from,to) \
270 d = reg_of_var(rd, to, REG_ITMP1); \
271 if ((from->regoff != to->regoff) || \
272 ((from->flags ^ to->flags) & INMEMORY)) { \
273 if (IS_FLT_DBL_TYPE(from->type)) { \
274 var_to_reg_flt(s1, from, d); \
275 /*M_FLTMOVE(s1, d);*/ \
276 store_reg_to_var_flt(to, d); \
278 if (!IS_2_WORD_TYPE(from->type)) { \
279 if (to->flags & INMEMORY) { \
280 if (from->flags & INMEMORY) { \
281 i386_mov_membase_reg(cd, REG_SP, from->regoff * 4, REG_ITMP1); \
282 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, to->regoff * 4); \
284 i386_mov_reg_membase(cd, from->regoff, REG_SP, to->regoff * 4); \
287 if (from->flags & INMEMORY) { \
288 i386_mov_membase_reg(cd, REG_SP, from->regoff * 4, to->regoff); \
290 i386_mov_reg_reg(cd, from->regoff, to->regoff); \
294 M_LNGMEMMOVE(from->regoff, to->regoff); \
299 /* macros to create code ******************************************************/
314 /* opcodes for alu instructions */
342 I386_CC_B = 2, I386_CC_C = 2, I386_CC_NAE = 2,
343 I386_CC_BE = 6, I386_CC_NA = 6,
344 I386_CC_AE = 3, I386_CC_NB = 3, I386_CC_NC = 3,
345 I386_CC_E = 4, I386_CC_Z = 4,
346 I386_CC_NE = 5, I386_CC_NZ = 5,
347 I386_CC_A = 7, I386_CC_NBE = 7,
348 I386_CC_S = 8, I386_CC_LZ = 8,
349 I386_CC_NS = 9, I386_CC_GEZ = 9,
350 I386_CC_P = 0x0a, I386_CC_PE = 0x0a,
351 I386_CC_NP = 0x0b, I386_CC_PO = 0x0b,
352 I386_CC_L = 0x0c, I386_CC_NGE = 0x0c,
353 I386_CC_GE = 0x0d, I386_CC_NL = 0x0d,
354 I386_CC_LE = 0x0e, I386_CC_NG = 0x0e,
355 I386_CC_G = 0x0f, I386_CC_NLE = 0x0f,
360 /* modrm and stuff */
362 #define i386_address_byte(mod,reg,rm) \
363 *(cd->mcodeptr++) = ((((mod) & 0x03) << 6) | (((reg) & 0x07) << 3) | (((rm) & 0x07)));
366 #define i386_emit_reg(reg,rm) \
367 i386_address_byte(3,(reg),(rm));
370 #define i386_is_imm8(imm) \
371 (((int)(imm) >= -128 && (int)(imm) <= 127))
374 #define i386_emit_imm8(imm) \
375 *(cd->mcodeptr++) = (u1) ((imm) & 0xff);
378 #define i386_emit_imm16(imm) \
381 imb.i = (int) (imm); \
382 *(cd->mcodeptr++) = imb.b[0]; \
383 *(cd->mcodeptr++) = imb.b[1]; \
387 #define i386_emit_imm32(imm) \
390 imb.i = (int) (imm); \
391 *(cd->mcodeptr++) = imb.b[0]; \
392 *(cd->mcodeptr++) = imb.b[1]; \
393 *(cd->mcodeptr++) = imb.b[2]; \
394 *(cd->mcodeptr++) = imb.b[3]; \
398 #define i386_emit_mem(r,mem) \
400 i386_address_byte(0,(r),5); \
401 i386_emit_imm32((mem)); \
405 #define i386_emit_membase(basereg,disp,dreg) \
407 if ((basereg) == ESP) { \
409 i386_address_byte(0, (dreg), ESP); \
410 i386_address_byte(0, ESP, ESP); \
411 } else if (i386_is_imm8((disp))) { \
412 i386_address_byte(1, (dreg), ESP); \
413 i386_address_byte(0, ESP, ESP); \
414 i386_emit_imm8((disp)); \
416 i386_address_byte(2, (dreg), ESP); \
417 i386_address_byte(0, ESP, ESP); \
418 i386_emit_imm32((disp)); \
423 if ((disp) == 0 && (basereg) != EBP) { \
424 i386_address_byte(0, (dreg), (basereg)); \
428 if (i386_is_imm8((disp))) { \
429 i386_address_byte(1, (dreg), (basereg)); \
430 i386_emit_imm8((disp)); \
432 i386_address_byte(2, (dreg), (basereg)); \
433 i386_emit_imm32((disp)); \
438 #define i386_emit_membase32(basereg,disp,dreg) \
440 if ((basereg) == ESP) { \
441 i386_address_byte(2, (dreg), ESP); \
442 i386_address_byte(0, ESP, ESP); \
443 i386_emit_imm32((disp)); \
445 i386_address_byte(2, (dreg), (basereg)); \
446 i386_emit_imm32((disp)); \
451 #define i386_emit_memindex(reg,disp,basereg,indexreg,scale) \
453 if ((basereg) == -1) { \
454 i386_address_byte(0, (reg), 4); \
455 i386_address_byte((scale), (indexreg), 5); \
456 i386_emit_imm32((disp)); \
458 } else if ((disp) == 0 && (basereg) != EBP) { \
459 i386_address_byte(0, (reg), 4); \
460 i386_address_byte((scale), (indexreg), (basereg)); \
462 } else if (i386_is_imm8((disp))) { \
463 i386_address_byte(1, (reg), 4); \
464 i386_address_byte((scale), (indexreg), (basereg)); \
465 i386_emit_imm8 ((disp)); \
468 i386_address_byte(2, (reg), 4); \
469 i386_address_byte((scale), (indexreg), (basereg)); \
470 i386_emit_imm32((disp)); \
475 /* macros to create code ******************************************************/
477 #define M_ILD(a,b,disp) i386_mov_membase_reg(cd, (b), (disp), (a))
478 #define M_ALD(a,b,disp) M_ILD(a,b,disp)
480 #define M_ILD32(a,b,disp) i386_mov_membase32_reg(cd, (b), (disp), (a))
482 #define M_LLD(a,b,disp) \
484 M_ILD(GET_LOW_REG(a),b,disp); \
485 M_ILD(GET_HIGH_REG(a),b,disp + 4); \
488 #define M_LLD32(a,b,disp) \
490 M_ILD32(GET_LOW_REG(a),b,disp); \
491 M_ILD32(GET_HIGH_REG(a),b,disp + 4); \
494 #define M_IST(a,b,disp) i386_mov_reg_membase(cd, (a), (b), (disp))
495 #define M_IST_IMM(a,b,disp) i386_mov_imm_membase(cd, (a), (b), (disp))
496 #define M_AST(a,b,disp) M_IST(a,b,disp)
497 #define M_AST_IMM(a,b,disp) M_IST_IMM(a,b,disp)
499 #define M_IST32(a,b,disp) i386_mov_reg_membase32(cd, (a), (b), (disp))
500 #define M_IST32_IMM(a,b,disp) i386_mov_imm_membase32(cd, (a), (b), (disp))
502 #define M_LST(a,b,disp) \
504 M_IST(GET_LOW_REG(a),b,disp); \
505 M_IST(GET_HIGH_REG(a),b,disp + 4); \
508 #define M_LST32(a,b,disp) \
510 M_IST32(GET_LOW_REG(a),b,disp); \
511 M_IST32(GET_HIGH_REG(a),b,disp + 4); \
514 #define M_LST_IMM(a,b,disp) \
516 M_IST_IMM(a,b,disp); \
517 M_IST_IMM(a >> 32,b,disp + 4); \
520 #define M_LST32_IMM(a,b,disp) \
522 M_IST32_IMM(a,b,disp); \
523 M_IST32_IMM(a >> 32,b,disp + 4); \
526 #define M_IADD_IMM(a,b) i386_alu_imm_reg(cd, ALU_ADD, (a), (b))
527 #define M_IADD_IMM32(a,b) i386_alu_imm32_reg(cd, ALU_ADD, (a), (b))
528 #define M_ISUB_IMM(a,b) i386_alu_imm_reg(cd, ALU_SUB, (a), (b))
530 #define M_IADD_IMM_MEMBASE(a,b,c) i386_alu_imm_membase(cd, ALU_ADD, (a), (b), (c))
532 #define M_AADD_IMM(a,b) M_IADD_IMM(a,b)
533 #define M_AADD_IMM32(a,b) M_IADD_IMM32(a,b)
534 #define M_ASUB_IMM(a,b) M_ISUB_IMM(a,b)
536 #define M_OR_MEMBASE(a,b,c) i386_alu_membase_reg(cd, ALU_OR, (a), (b), (c))
537 #define M_XOR(a,b) i386_alu_reg_reg(cd, ALU_XOR, (a), (b))
538 #define M_CLR(a) M_XOR(a,a)
540 #define M_PUSH(a) i386_push_reg(cd, (a))
541 #define M_PUSH_IMM(a) i386_push_imm(cd, (a))
542 #define M_POP(a) i386_pop_reg(cd, (a))
544 #define M_MOV(a,b) i386_mov_reg_reg(cd, (a), (b))
545 #define M_MOV_IMM(a,b) i386_mov_imm_reg(cd, (a), (b))
547 #define M_TEST(a) i386_test_reg_reg(cd, (a), (a))
549 #define M_CALL(a) i386_call_reg(cd, (a))
550 #define M_CALL_IMM(a) i386_call_imm(cd, (a))
551 #define M_RET i386_ret(cd)
553 #define M_BEQ(a) i386_jcc(cd, I386_CC_E, (a))
554 #define M_BNE(a) i386_jcc(cd, I386_CC_NE, (a))
555 #define M_BLT(a) i386_jcc(cd, I386_CC_L, (a))
556 #define M_BLE(a) i386_jcc(cd, I386_CC_LE, (a))
557 #define M_BGE(a) i386_jcc(cd, I386_CC_GE, (a))
558 #define M_BGT(a) i386_jcc(cd, I386_CC_G, (a))
560 #define M_BBE(a) i386_jcc(cd, I386_CC_BE, (a))
561 #define M_BAE(a) i386_jcc(cd, I386_CC_AE, (a))
563 #define M_JMP(a) i386_jmp_reg(cd, (a))
564 #define M_JMP_IMM(a) i386_jmp_imm(cd, (a))
566 #define M_NOP i386_nop(cd)
569 /* function gen_resolvebranch **************************************************
571 backpatches a branch instruction
573 parameters: ip ... pointer to instruction after branch (void*)
574 so ... offset of instruction after branch (s4)
575 to ... offset of branch target (s4)
577 *******************************************************************************/
579 #define gen_resolvebranch(ip,so,to) \
580 *((void **) ((ip) - 4)) = (void **) ((to) - (so));
583 #endif /* _CODEGEN_H */
587 * These are local overrides for various environment variables in Emacs.
588 * Please do not remove this and leave it at the end of the file, where
589 * Emacs will automagically detect them.
590 * ---------------------------------------------------------------------
593 * indent-tabs-mode: t