1 /* src/vm/jit/i386/codegen.h - code generation macros and definitions for i386
3 Copyright (C) 1996-2005 R. Grafl, A. Krall, C. Kruegel, C. Oates,
4 R. Obermaisser, M. Platter, M. Probst, S. Ring, E. Steiner,
5 C. Thalinger, D. Thuernbeck, P. Tomsich, C. Ullrich, J. Wenninger,
6 Institut f. Computersprachen - TU Wien
8 This file is part of CACAO.
10 This program is free software; you can redistribute it and/or
11 modify it under the terms of the GNU General Public License as
12 published by the Free Software Foundation; either version 2, or (at
13 your option) any later version.
15 This program is distributed in the hope that it will be useful, but
16 WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
25 Contact: cacao@complang.tuwien.ac.at
27 Authors: Andreas Krall
32 $Id: codegen.h 2676 2005-06-13 16:20:32Z twisti $
43 /* let LSRA allocate reserved registers (REG_ITMP[1|2|3]) */
44 #define LSRA_USES_REG_RES
47 /* additional functions and macros to generate code ***************************/
49 #define BlockPtrOfPC(pc) ((basicblock *) iptr->target)
53 #define COUNT_SPILLS count_spills++
59 #define CALCOFFSETBYTES(var, reg, val) \
60 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
61 else if ((s4) (val) != 0) (var) += 1; \
62 else if ((reg) == EBP) (var) += 1;
65 #define CALCIMMEDIATEBYTES(var, val) \
66 if ((s4) (val) < -128 || (s4) (val) > 127) (var) += 4; \
70 /* gen_nullptr_check(objreg) */
72 #define gen_nullptr_check(objreg) \
74 i386_test_reg_reg(cd, (objreg), (objreg)); \
75 i386_jcc(cd, I386_CC_E, 0); \
76 codegen_addxnullrefs(cd, cd->mcodeptr); \
79 #define gen_bound_check \
81 i386_alu_membase_reg(cd, ALU_CMP, s1, OFFSET(java_arrayheader, size), s2); \
82 i386_jcc(cd, I386_CC_AE, 0); \
83 codegen_addxboundrefs(cd, cd->mcodeptr, s2); \
86 #define gen_div_check(v) \
88 if ((v)->flags & INMEMORY) { \
89 i386_alu_imm_membase(cd, ALU_CMP, 0, REG_SP, src->regoff * 4); \
91 i386_test_reg_reg(cd, src->regoff, src->regoff); \
93 i386_jcc(cd, I386_CC_E, 0); \
94 codegen_addxdivrefs(cd, cd->mcodeptr); \
98 /* MCODECHECK(icnt) */
100 #define MCODECHECK(icnt) \
101 if ((cd->mcodeptr + (icnt)) > (u1 *) cd->mcodeend) \
102 cd->mcodeptr = (u1 *) codegen_increase(cd, cd->mcodeptr)
106 generates an integer-move from register a to b.
107 if a and b are the same int-register, no code will be generated.
110 #define M_INTMOVE(reg,dreg) \
111 if ((reg) != (dreg)) { \
112 i386_mov_reg_reg(cd, (reg),(dreg)); \
117 generates a floating-point-move from register a to b.
118 if a and b are the same float-register, no code will be generated
121 #define M_FLTMOVE(reg,dreg) \
123 log_text("M_FLTMOVE"); \
128 #define M_LNGMEMMOVE(reg,dreg) \
130 i386_mov_membase_reg(cd, REG_SP, (reg) * 4, REG_ITMP1); \
131 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, (dreg) * 4); \
132 i386_mov_membase_reg(cd, REG_SP, (reg) * 4 + 4, REG_ITMP1); \
133 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, (dreg) * 4 + 4); \
138 this function generates code to fetch data from a pseudo-register
139 into a real register.
140 If the pseudo-register has actually been assigned to a real
141 register, no code will be emitted, since following operations
142 can use this register directly.
144 v: pseudoregister to be fetched from
145 tempregnum: temporary register to be used if v is actually spilled to ram
147 return: the register number, where the operand can be found after
148 fetching (this wil be either tempregnum or the register
149 number allready given to v)
152 #define var_to_reg_int(regnr,v,tempnr) \
153 if ((v)->flags & INMEMORY) { \
155 i386_mov_membase_reg(cd, REG_SP, (v)->regoff * 4, tempnr); \
158 regnr = (v)->regoff; \
163 #define var_to_reg_flt(regnr,v,tempnr) \
164 if ((v)->type == TYPE_FLT) { \
165 if ((v)->flags & INMEMORY) { \
167 i386_flds_membase(cd, REG_SP, (v)->regoff * 4); \
171 i386_fld_reg(cd, (v)->regoff + fpu_st_offset); \
173 regnr = (v)->regoff; \
176 if ((v)->flags & INMEMORY) { \
178 i386_fldl_membase(cd, REG_SP, (v)->regoff * 4); \
182 i386_fld_reg(cd, (v)->regoff + fpu_st_offset); \
184 regnr = (v)->regoff; \
188 #define NEW_var_to_reg_flt(regnr,v,tempnr) \
189 if ((v)->type == TYPE_FLT) { \
190 if ((v)->flags & INMEMORY) { \
192 i386_flds_membase(cd, REG_SP, (v)->regoff * 4); \
196 regnr = (v)->regoff; \
199 if ((v)->flags & INMEMORY) { \
201 i386_fldl_membase(cd, REG_SP, (v)->regoff * 4); \
205 regnr = (v)->regoff; \
210 /* store_reg_to_var_xxx:
211 This function generates the code to store the result of an operation
212 back into a spilled pseudo-variable.
213 If the pseudo-variable has not been spilled in the first place, this
214 function will generate nothing.
216 v ............ Pseudovariable
217 tempregnum ... Number of the temporary registers as returned by
221 #define store_reg_to_var_int(sptr, tempregnum) \
222 if ((sptr)->flags & INMEMORY) { \
224 i386_mov_reg_membase(cd, tempregnum, REG_SP, (sptr)->regoff * 4); \
228 #define store_reg_to_var_flt(sptr, tempregnum) \
229 if ((sptr)->type == TYPE_FLT) { \
230 if ((sptr)->flags & INMEMORY) { \
232 i386_fstps_membase(cd, REG_SP, (sptr)->regoff * 4); \
235 /* i386_fxch_reg((sptr)->regoff);*/ \
236 i386_fstp_reg(cd, (sptr)->regoff + fpu_st_offset); \
240 if ((sptr)->flags & INMEMORY) { \
242 i386_fstpl_membase(cd, REG_SP, (sptr)->regoff * 4); \
245 /* i386_fxch_reg((sptr)->regoff);*/ \
246 i386_fstp_reg(cd, (sptr)->regoff + fpu_st_offset); \
252 #define M_COPY(from,to) \
253 d = reg_of_var(rd, to, REG_ITMP1); \
254 if ((from->regoff != to->regoff) || \
255 ((from->flags ^ to->flags) & INMEMORY)) { \
256 if (IS_FLT_DBL_TYPE(from->type)) { \
257 var_to_reg_flt(s1, from, d); \
258 /*M_FLTMOVE(s1, d);*/ \
259 store_reg_to_var_flt(to, d); \
261 if (!IS_2_WORD_TYPE(from->type)) { \
262 if (to->flags & INMEMORY) { \
263 if (from->flags & INMEMORY) { \
264 i386_mov_membase_reg(cd, REG_SP, from->regoff * 4, REG_ITMP1); \
265 i386_mov_reg_membase(cd, REG_ITMP1, REG_SP, to->regoff * 4); \
267 i386_mov_reg_membase(cd, from->regoff, REG_SP, to->regoff * 4); \
270 if (from->flags & INMEMORY) { \
271 i386_mov_membase_reg(cd, REG_SP, from->regoff * 4, to->regoff); \
273 i386_mov_reg_reg(cd, from->regoff, to->regoff); \
277 M_LNGMEMMOVE(from->regoff, to->regoff); \
282 /* macros to create code ******************************************************/
297 /* opcodes for alu instructions */
325 I386_CC_B = 2, I386_CC_C = 2, I386_CC_NAE = 2,
326 I386_CC_BE = 6, I386_CC_NA = 6,
327 I386_CC_AE = 3, I386_CC_NB = 3, I386_CC_NC = 3,
328 I386_CC_E = 4, I386_CC_Z = 4,
329 I386_CC_NE = 5, I386_CC_NZ = 5,
330 I386_CC_A = 7, I386_CC_NBE = 7,
331 I386_CC_S = 8, I386_CC_LZ = 8,
332 I386_CC_NS = 9, I386_CC_GEZ = 9,
333 I386_CC_P = 0x0a, I386_CC_PE = 0x0a,
334 I386_CC_NP = 0x0b, I386_CC_PO = 0x0b,
335 I386_CC_L = 0x0c, I386_CC_NGE = 0x0c,
336 I386_CC_GE = 0x0d, I386_CC_NL = 0x0d,
337 I386_CC_LE = 0x0e, I386_CC_NG = 0x0e,
338 I386_CC_G = 0x0f, I386_CC_NLE = 0x0f,
343 /* modrm and stuff */
345 #define i386_address_byte(mod,reg,rm) \
346 *(cd->mcodeptr++) = ((((mod) & 0x03) << 6) | (((reg) & 0x07) << 3) | (((rm) & 0x07)));
349 #define i386_emit_reg(reg,rm) \
350 i386_address_byte(3,(reg),(rm));
353 #define i386_is_imm8(imm) \
354 (((int)(imm) >= -128 && (int)(imm) <= 127))
357 #define i386_emit_imm8(imm) \
358 *(cd->mcodeptr++) = (u1) ((imm) & 0xff);
361 #define i386_emit_imm16(imm) \
364 imb.i = (int) (imm); \
365 *(cd->mcodeptr++) = imb.b[0]; \
366 *(cd->mcodeptr++) = imb.b[1]; \
370 #define i386_emit_imm32(imm) \
373 imb.i = (int) (imm); \
374 *(cd->mcodeptr++) = imb.b[0]; \
375 *(cd->mcodeptr++) = imb.b[1]; \
376 *(cd->mcodeptr++) = imb.b[2]; \
377 *(cd->mcodeptr++) = imb.b[3]; \
381 #define i386_emit_mem(r,mem) \
383 i386_address_byte(0,(r),5); \
384 i386_emit_imm32((mem)); \
388 #define i386_emit_membase(basereg,disp,dreg) \
390 if ((basereg) == ESP) { \
392 i386_address_byte(0, (dreg), ESP); \
393 i386_address_byte(0, ESP, ESP); \
394 } else if (i386_is_imm8((disp))) { \
395 i386_address_byte(1, (dreg), ESP); \
396 i386_address_byte(0, ESP, ESP); \
397 i386_emit_imm8((disp)); \
399 i386_address_byte(2, (dreg), ESP); \
400 i386_address_byte(0, ESP, ESP); \
401 i386_emit_imm32((disp)); \
406 if ((disp) == 0 && (basereg) != EBP) { \
407 i386_address_byte(0, (dreg), (basereg)); \
411 if (i386_is_imm8((disp))) { \
412 i386_address_byte(1, (dreg), (basereg)); \
413 i386_emit_imm8((disp)); \
415 i386_address_byte(2, (dreg), (basereg)); \
416 i386_emit_imm32((disp)); \
421 #define i386_emit_membase32(basereg,disp,dreg) \
423 if ((basereg) == ESP) { \
424 i386_address_byte(2, (dreg), ESP); \
425 i386_address_byte(0, ESP, ESP); \
426 i386_emit_imm32((disp)); \
428 i386_address_byte(2, (dreg), (basereg)); \
429 i386_emit_imm32((disp)); \
434 #define i386_emit_memindex(reg,disp,basereg,indexreg,scale) \
436 if ((basereg) == -1) { \
437 i386_address_byte(0, (reg), 4); \
438 i386_address_byte((scale), (indexreg), 5); \
439 i386_emit_imm32((disp)); \
441 } else if ((disp) == 0 && (basereg) != EBP) { \
442 i386_address_byte(0, (reg), 4); \
443 i386_address_byte((scale), (indexreg), (basereg)); \
445 } else if (i386_is_imm8((disp))) { \
446 i386_address_byte(1, (reg), 4); \
447 i386_address_byte((scale), (indexreg), (basereg)); \
448 i386_emit_imm8 ((disp)); \
451 i386_address_byte(2, (reg), 4); \
452 i386_address_byte((scale), (indexreg), (basereg)); \
453 i386_emit_imm32((disp)); \
458 /* macros to create code ******************************************************/
460 #define M_ILD(a,b,disp) i386_mov_membase_reg(cd, (b), (disp), (a))
462 #define M_IST(a,b,disp) i386_mov_reg_membase(cd, (a), (b), (disp))
464 #define M_IADD_IMM(a,b) i386_alu_imm_reg(cd, ALU_ADD, (a), (b))
465 #define M_ISUB_IMM(a,b) i386_alu_imm_reg(cd, ALU_SUB, (a), (b))
467 #define M_AADD_IMM(a,b) M_IADD_IMM(a,b)
468 #define M_ASUB_IMM(a,b) M_ISUB_IMM(a,b)
470 #define M_PUSH(a) i386_push_reg(cd, a)
471 #define M_PUSH_IMM(a) i386_push_imm(cd, a)
473 #define M_NOP i386_nop(cd)
476 /* function gen_resolvebranch **************************************************
478 backpatches a branch instruction
480 parameters: ip ... pointer to instruction after branch (void*)
481 so ... offset of instruction after branch (s4)
482 to ... offset of branch target (s4)
484 *******************************************************************************/
486 #define gen_resolvebranch(ip,so,to) \
487 *((void **) ((ip) - 4)) = (void **) ((to) - (so));
490 /* function prototypes */
492 void thread_restartcriticalsection(ucontext_t *);
494 #endif /* _CODEGEN_H */
498 * These are local overrides for various environment variables in Emacs.
499 * Please do not remove this and leave it at the end of the file, where
500 * Emacs will automagically detect them.
501 * ---------------------------------------------------------------------
504 * indent-tabs-mode: t